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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
/// @file       
/// @brief      Core tracelog module
///
 
`include "scr1_arch_description.svh"
`include "scr1_arch_types.svh"
`include "scr1_csr.svh"
 
`ifdef SCR1_TRGT_SIMULATION
 
module scr1_tracelog (
    input   logic                                 rst_n,                        // Tracelog reset
    input   logic                                 clk,                          // Tracelog clock
    input   logic [`SCR1_XLEN-1:0]                soc2pipe_fuse_mhartid_i,      // Fuse MHARTID
 
    // MPRF
`ifdef  SCR1_MPRF_RAM
    input   logic   [`SCR1_XLEN-1:0]            mprf2trace_int_i   [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
`else // SCR1_MPRF_RAM
    input   type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i,             // MPRF registers content
`endif // SCR1_MPRF_RAM
    input   logic                                 mprf2trace_wr_en_i,           // MPRF write enable
    input   logic [`SCR1_MPRF_AWIDTH-1:0]         mprf2trace_wr_addr_i,         // MPRF write address
    input   logic [`SCR1_XLEN-1:0]                mprf2trace_wr_data_i,         // MPRF write data
 
    // EXU
    input   logic                                 exu2trace_update_pc_en_i,     // PC updated flag
    input   logic [`SCR1_XLEN-1:0]                exu2trace_update_pc_i,        // Next PC value
 
    // IFU
    input   logic [`SCR1_IMEM_DWIDTH-1:0]         ifu2trace_instr_i,            // Current instruction from IFU stage
 
    // CSR
    input   logic                                 csr2trace_mstatus_mie_i,      // CSR MSTATUS.mie bit
    input   logic                                 csr2trace_mstatus_mpie_i,     // CSR MSTATUS.mpie bit
    input   logic [`SCR1_XLEN-1:6]                csr2trace_mtvec_base_i,       // CSR MTVEC.
    input   logic                                 csr2trace_mtvec_mode_i,       // CSR MTVEC.
    input   logic                                 csr2trace_mie_meie_i,         // CSR MIE.meie bit
    input   logic                                 csr2trace_mie_mtie_i,         // CSR MIE.mtie bit
    input   logic                                 csr2trace_mie_msie_i,         // CSR MIE.msie bit
    input   logic                                 csr2trace_mip_meip_i,         // CSR MIP.meip bit
    input   logic                                 csr2trace_mip_mtip_i,         // CSR MIP.mtip bit
    input   logic                                 csr2trace_mip_msip_i,         // CSR MIP.msip bit
 `ifdef SCR1_RVC_EXT
    input   logic [`SCR1_XLEN-1:1]                csr2trace_mepc_i,             // CSR MEPC register
 `else // SCR1_RVC_EXT
    input   logic [`SCR1_XLEN-1:2]                csr2trace_mepc_i,             // CSR MEPC register
 `endif // SCR1_RVC_EXT
    input   logic                                 csr2trace_mcause_irq_i,       // CSR MCAUSE.interrupt bit
    input   type_scr1_exc_code_e                  csr2trace_mcause_ec_i,        // CSR MCAUSE.exception_code bit
    input   logic [`SCR1_XLEN-1:0]                csr2trace_mtval_i,            // CSR MTVAL register
    input   logic                                 csr2trace_mstatus_mie_up_i,   // CSR MSTATUS.mie update flag
 
    // Events
    input   logic                                 csr2trace_e_exc_i,            // exception event
    input   logic                                 csr2trace_e_irq_i,            // interrupt event
    input   logic                                 pipe2trace_e_wake_i,          // pipe wakeup event
    input   logic                                 csr2trace_e_mret_i            // MRET instruction
);
 
//-------------------------------------------------------------------------------
// Local types declaration
//-------------------------------------------------------------------------------
typedef struct {
    logic [`SCR1_XLEN-1:0]      INT_00_ZERO ;
    logic [`SCR1_XLEN-1:0]      INT_01_RA   ;
    logic [`SCR1_XLEN-1:0]      INT_02_SP   ;
    logic [`SCR1_XLEN-1:0]      INT_03_GP   ;
    logic [`SCR1_XLEN-1:0]      INT_04_TP   ;
    logic [`SCR1_XLEN-1:0]      INT_05_T0   ;
    logic [`SCR1_XLEN-1:0]      INT_06_T1   ;
    logic [`SCR1_XLEN-1:0]      INT_07_T2   ;
    logic [`SCR1_XLEN-1:0]      INT_08_S0   ;
    logic [`SCR1_XLEN-1:0]      INT_09_S1   ;
    logic [`SCR1_XLEN-1:0]      INT_10_A0   ;
    logic [`SCR1_XLEN-1:0]      INT_11_A1   ;
    logic [`SCR1_XLEN-1:0]      INT_12_A2   ;
    logic [`SCR1_XLEN-1:0]      INT_13_A3   ;
    logic [`SCR1_XLEN-1:0]      INT_14_A4   ;
    logic [`SCR1_XLEN-1:0]      INT_15_A5   ;
`ifndef SCR1_RVE_EXT
    logic [`SCR1_XLEN-1:0]      INT_16_A6   ;
    logic [`SCR1_XLEN-1:0]      INT_17_A7   ;
    logic [`SCR1_XLEN-1:0]      INT_18_S2   ;
    logic [`SCR1_XLEN-1:0]      INT_19_S3   ;
    logic [`SCR1_XLEN-1:0]      INT_20_S4   ;
    logic [`SCR1_XLEN-1:0]      INT_21_S5   ;
    logic [`SCR1_XLEN-1:0]      INT_22_S6   ;
    logic [`SCR1_XLEN-1:0]      INT_23_S7   ;
    logic [`SCR1_XLEN-1:0]      INT_24_S8   ;
    logic [`SCR1_XLEN-1:0]      INT_25_S9   ;
    logic [`SCR1_XLEN-1:0]      INT_26_S10  ;
    logic [`SCR1_XLEN-1:0]      INT_27_S11  ;
    logic [`SCR1_XLEN-1:0]      INT_28_T3   ;
    logic [`SCR1_XLEN-1:0]      INT_29_T4   ;
    logic [`SCR1_XLEN-1:0]      INT_30_T5   ;
    logic [`SCR1_XLEN-1:0]      INT_31_T6   ;
`endif // SCR1_RVE_EXT
} type_scr1_ireg_name_s;
 
typedef struct packed {
    logic [`SCR1_XLEN-1:0]  mstatus;
    logic [`SCR1_XLEN-1:0]  mtvec;
    logic [`SCR1_XLEN-1:0]  mie;
    logic [`SCR1_XLEN-1:0]  mip;
    logic [`SCR1_XLEN-1:0]  mepc;
    logic [`SCR1_XLEN-1:0]  mcause;
    logic [`SCR1_XLEN-1:0]  mtval;
} type_scr1_csr_trace_s;
 
//-------------------------------------------------------------------------------
// Local Signal Declaration
//-------------------------------------------------------------------------------
 
type_scr1_ireg_name_s               mprf_int_alias;
 
`ifdef SCR1_TRACE_LOG_EN
 
time                                current_time;
 
// Tracelog control signals
logic                               trace_flag;
logic                               trace_update;
logic                               trace_update_r;
byte                                event_type;
 
logic [`SCR1_XLEN-1:0]              trace_pc;
logic [`SCR1_XLEN-1:0]              trace_npc;
logic [`SCR1_IMEM_DWIDTH-1:0]       trace_instr;
 
type_scr1_csr_trace_s               csr_trace1;
 
// File handlers
int unsigned                        trace_fhandler_core;
 
// MPRF signals
logic                               mprf_up;
logic [`SCR1_MPRF_AWIDTH-1:0]       mprf_addr;
logic [`SCR1_XLEN-1:0]              mprf_wdata;
 
string                              hart;
string                              test_name;
 
`endif // SCR1_TRACE_LOG_EN
 
//-------------------------------------------------------------------------------
// Local tasks
//-------------------------------------------------------------------------------
 
`ifdef SCR1_TRACE_LOG_EN
 
task trace_write_common;
    $fwrite(trace_fhandler_core, "%16d  ", current_time);
    // $fwrite(trace_fhandler_core, " 0  ");
    $fwrite(trace_fhandler_core, " %s  ",  event_type);
    $fwrite(trace_fhandler_core, " %8x  ", trace_pc);
    $fwrite(trace_fhandler_core, " %8x  ", trace_instr);
    $fwrite(trace_fhandler_core, " %8x  ", trace_npc);
endtask // trace_write_common
 
task trace_write_int_walias;
    case (mprf_addr)
 
        1  :  $fwrite(trace_fhandler_core, " x01_ra    ");
        2  :  $fwrite(trace_fhandler_core, " x02_sp    ");
        3  :  $fwrite(trace_fhandler_core, " x03_gp    ");
        4  :  $fwrite(trace_fhandler_core, " x04_tp    ");
        5  :  $fwrite(trace_fhandler_core, " x05_t0    ");
        6  :  $fwrite(trace_fhandler_core, " x06_t1    ");
        7  :  $fwrite(trace_fhandler_core, " x07_t2    ");
        8  :  $fwrite(trace_fhandler_core, " x08_s0    ");
        9  :  $fwrite(trace_fhandler_core, " x09_s1    ");
        10 :  $fwrite(trace_fhandler_core, " x10_a0    ");
        11 :  $fwrite(trace_fhandler_core, " x11_a1    ");
        12 :  $fwrite(trace_fhandler_core, " x12_a2    ");
        13 :  $fwrite(trace_fhandler_core, " x13_a3    ");
        14 :  $fwrite(trace_fhandler_core, " x14_a4    ");
        15 :  $fwrite(trace_fhandler_core, " x15_a5    ");
`ifndef SCR1_RVE_EXT
        16 :  $fwrite(trace_fhandler_core, " x16_a6    ");
        17 :  $fwrite(trace_fhandler_core, " x17_a7    ");
        18 :  $fwrite(trace_fhandler_core, " x18_s2    ");
        19 :  $fwrite(trace_fhandler_core, " x19_s3    ");
        20 :  $fwrite(trace_fhandler_core, " x20_s4    ");
        21 :  $fwrite(trace_fhandler_core, " x21_s5    ");
        22 :  $fwrite(trace_fhandler_core, " x22_s6    ");
        23 :  $fwrite(trace_fhandler_core, " x23_s7    ");
        24 :  $fwrite(trace_fhandler_core, " x24_s8    ");
        25 :  $fwrite(trace_fhandler_core, " x25_s9    ");
        26 :  $fwrite(trace_fhandler_core, " x26_s10   ");
        27 :  $fwrite(trace_fhandler_core, " x27_s11   ");
        28 :  $fwrite(trace_fhandler_core, " x28_t3    ");
        29 :  $fwrite(trace_fhandler_core, " x29_t4    ");
        30 :  $fwrite(trace_fhandler_core, " x30_t5    ");
        31 :  $fwrite(trace_fhandler_core, " x31_t6    ");
`endif // SCR1_RVE_EXT
        default: begin
              $fwrite(trace_fhandler_core, " xxx       ");
        end
    endcase
endtask
 
`endif // SCR1_TRACE_LOG_EN
 
//-------------------------------------------------------------------------------
// MPRF Registers assignment
//-------------------------------------------------------------------------------
assign mprf_int_alias.INT_00_ZERO   = '0;
assign mprf_int_alias.INT_01_RA     = mprf2trace_int_i[1];
assign mprf_int_alias.INT_02_SP     = mprf2trace_int_i[2];
assign mprf_int_alias.INT_03_GP     = mprf2trace_int_i[3];
assign mprf_int_alias.INT_04_TP     = mprf2trace_int_i[4];
assign mprf_int_alias.INT_05_T0     = mprf2trace_int_i[5];
assign mprf_int_alias.INT_06_T1     = mprf2trace_int_i[6];
assign mprf_int_alias.INT_07_T2     = mprf2trace_int_i[7];
assign mprf_int_alias.INT_08_S0     = mprf2trace_int_i[8];
assign mprf_int_alias.INT_09_S1     = mprf2trace_int_i[9];
assign mprf_int_alias.INT_10_A0     = mprf2trace_int_i[10];
assign mprf_int_alias.INT_11_A1     = mprf2trace_int_i[11];
assign mprf_int_alias.INT_12_A2     = mprf2trace_int_i[12];
assign mprf_int_alias.INT_13_A3     = mprf2trace_int_i[13];
assign mprf_int_alias.INT_14_A4     = mprf2trace_int_i[14];
assign mprf_int_alias.INT_15_A5     = mprf2trace_int_i[15];
`ifndef SCR1_RVE_EXT
assign mprf_int_alias.INT_16_A6     = mprf2trace_int_i[16];
assign mprf_int_alias.INT_17_A7     = mprf2trace_int_i[17];
assign mprf_int_alias.INT_18_S2     = mprf2trace_int_i[18];
assign mprf_int_alias.INT_19_S3     = mprf2trace_int_i[19];
assign mprf_int_alias.INT_20_S4     = mprf2trace_int_i[20];
assign mprf_int_alias.INT_21_S5     = mprf2trace_int_i[21];
assign mprf_int_alias.INT_22_S6     = mprf2trace_int_i[22];
assign mprf_int_alias.INT_23_S7     = mprf2trace_int_i[23];
assign mprf_int_alias.INT_24_S8     = mprf2trace_int_i[24];
assign mprf_int_alias.INT_25_S9     = mprf2trace_int_i[25];
assign mprf_int_alias.INT_26_S10    = mprf2trace_int_i[26];
assign mprf_int_alias.INT_27_S11    = mprf2trace_int_i[27];
assign mprf_int_alias.INT_28_T3     = mprf2trace_int_i[28];
assign mprf_int_alias.INT_29_T4     = mprf2trace_int_i[29];
assign mprf_int_alias.INT_30_T5     = mprf2trace_int_i[30];
assign mprf_int_alias.INT_31_T6     = mprf2trace_int_i[31];
`endif // SCR1_RVE_EXT
 
//-------------------------------------------------------------------------------
// Legacy time counter
//-------------------------------------------------------------------------------
// The counter is left for compatibility with the current UVM environment
 
int     time_cnt;
 
always_ff @(negedge rst_n, posedge clk) begin
    if (~rst_n) begin
        time_cnt    <= 0;
    end else begin
        time_cnt    <= time_cnt + 1;
    end
end
 
//-------------------------------------------------------------------------------
// Initial part pipeline tracelog
//-------------------------------------------------------------------------------
 
`ifdef SCR1_TRACE_LOG_EN
// Files opening and writing initial header
initial begin
    $timeformat(-9, 0, " ns", 10);
    #1 hart.hextoa(soc2pipe_fuse_mhartid_i);
 
    trace_fhandler_core = $fopen({"tracelog_core_", hart, ".log"}, "w");
 
    // Writing initial header
    $fwrite(trace_fhandler_core,  "# RTL_ID %h\n", SCR1_CSR_MIMPID);
    $fwrite(trace_fhandler_core,  "#\n");
    // $fwrite(trace_fhandler_core,  "# R - return from trap:\n");
    // $fwrite(trace_fhandler_core,  "#    1 - MRET\n");
    // $fwrite(trace_fhandler_core,  "#    0 - no return\n");
    $fwrite(trace_fhandler_core,  "# Events:\n");
    $fwrite(trace_fhandler_core,  "#    N - no event\n");
    $fwrite(trace_fhandler_core,  "#    E - exception\n");
    $fwrite(trace_fhandler_core,  "#    I - interrupt\n");
    $fwrite(trace_fhandler_core,  "#    W - wakeup\n");
end
 
// Core reset logging and header printing
always @(posedge rst_n) begin
    $fwrite(trace_fhandler_core, "# =====================================================================================\n");
`ifndef VERILATOR
    $fwrite(trace_fhandler_core, "# %14t : Core Reset\n", $time());
`else
    $fwrite(trace_fhandler_core, "# : Core Reset\n");
`endif
    $fwrite(trace_fhandler_core, "# =====================================================================================\n");
    $fwrite(trace_fhandler_core,  "# Test: %s\n", test_name);
    $fwrite(trace_fhandler_core,  "#           Time  ");
    // $fwrite(trace_fhandler_core,  " R  ");
    $fwrite(trace_fhandler_core,  " Ev ");
    $fwrite(trace_fhandler_core,  " Curr_PC   ");
    $fwrite(trace_fhandler_core,  " Instr     ");
    $fwrite(trace_fhandler_core,  " Next_PC   ");
    $fwrite(trace_fhandler_core,  " Reg       ");
    $fwrite(trace_fhandler_core,  " Value     ");
    $fwrite(trace_fhandler_core, "\n");
    $fwrite(trace_fhandler_core, "# =====================================================================================\n");
end
 
//-------------------------------------------------------------------------------
// Common trace part
//-------------------------------------------------------------------------------
 
assign trace_flag   = 1'b1;
assign trace_update = (exu2trace_update_pc_en_i | mprf2trace_wr_en_i) & trace_flag;
 
always_ff @(posedge clk) begin
    if (~rst_n) begin
        current_time    <= 0;
        event_type      <= "N";
 
        trace_pc        <= 'x;
        trace_npc       <= 'x;
        trace_instr     <= 'x;
 
        trace_update_r  <= 1'b0;
 
        mprf_up         <= '0;
        mprf_addr       <= '0;
        mprf_wdata      <= '0;
    end else begin
        trace_update_r <= trace_update;
        if (trace_update) begin
`ifdef VERILATOR
            current_time  <= time_cnt;
`else
            current_time  <= $time();
`endif
            trace_pc      <= trace_npc;
            trace_npc     <= exu2trace_update_pc_i;
            trace_instr   <= ifu2trace_instr_i;
 
            if (csr2trace_e_exc_i) begin
                // Exception
                event_type  <= "E";
            end
            else if (csr2trace_e_irq_i) begin
                // IRQ
                event_type  <= "I";
            end
            else if (pipe2trace_e_wake_i) begin
                // Wake
                event_type <= "W";
            end
            // if (csr2trace_e_mret_i) begin
            //     // MRET
            //     event_type  <= "R";
            // end
            else begin
                // No event
                event_type <= "N";
            end
        end
 
        // Write log signals
        mprf_up    <= mprf2trace_wr_en_i;
        mprf_addr  <= mprf2trace_wr_en_i ? mprf2trace_wr_addr_i : 'x;
        mprf_wdata <= mprf2trace_wr_en_i ? mprf2trace_wr_data_i : 'x;
    end
end
 
//-------------------------------------------------------------------------------
// Core MPRF logging
//-------------------------------------------------------------------------------
 
always_ff @(negedge rst_n, posedge clk) begin
    if (~rst_n) begin
    end else begin
        if (trace_update_r) begin
 
            trace_write_common();
 
            case (event_type)
                "W"     : begin
                    // Wakeup
                    if (csr_trace1.mip & csr_trace1.mie) begin
                        $fwrite(trace_fhandler_core, " mip        %08x\n", csr_trace1.mip );
                        trace_write_common();
                        $fwrite(trace_fhandler_core, " mie        %08x", csr_trace1.mie );
                    end
                end
                "N"     : begin
                    // Regular
                    if (mprf_up && mprf_addr != 0) begin
                        // $fwrite(trace_fhandler_core, " x%2d      %08x", mprf_addr, mprf_wdata);
                        trace_write_int_walias();
                        $fwrite(trace_fhandler_core, " %08x", mprf_wdata);
                    end else begin
                        $fwrite(trace_fhandler_core, " ---        --------");
                    end
                end
                "R"     : begin
                    // MRET
                    $fwrite(trace_fhandler_core, " mstatus    %08x", csr_trace1.mstatus);
                end
                "E", "I": begin
                    // IRQ/Exception
                    $fwrite(trace_fhandler_core, " mstatus    %08x\n", csr_trace1.mstatus);
                    trace_write_common();
                    $fwrite(trace_fhandler_core, " mepc       %08x\n", csr_trace1.mepc);
                    trace_write_common();
                    $fwrite(trace_fhandler_core, " mcause     %08x\n", csr_trace1.mcause);
                    trace_write_common();
                    $fwrite(trace_fhandler_core, " mtval      %08x",   csr_trace1.mtval);
                end
                default : begin
                    $fwrite(trace_fhandler_core,  "\n");
                end
            endcase
            $fwrite(trace_fhandler_core,  "\n");
        end
    end
end
 
//-------------------------------------------------------------------------------
// Core CSR logging
//-------------------------------------------------------------------------------
 
always_comb begin
    csr_trace1.mtvec        = {csr2trace_mtvec_base_i, 4'd0, 2'(csr2trace_mtvec_mode_i)};
    csr_trace1.mepc         =
`ifdef SCR1_RVC_EXT
                              {csr2trace_mepc_i, 1'b0};
`else // SCR1_RVC_EXT
                              {csr2trace_mepc_i, 2'b00};
`endif // SCR1_RVC_EXT
    csr_trace1.mcause       = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};
    csr_trace1.mtval        = csr2trace_mtval_i;
 
    csr_trace1.mstatus      = '0;
    csr_trace1.mie          = '0;
    csr_trace1.mip          = '0;
 
    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET]     = csr2trace_mstatus_mie_i;
    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET]    = csr2trace_mstatus_mpie_i;
    csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET]   = SCR1_CSR_MSTATUS_MPP;
    csr_trace1.mie[SCR1_CSR_MIE_MSIE_OFFSET]            = csr2trace_mie_msie_i;
    csr_trace1.mie[SCR1_CSR_MIE_MTIE_OFFSET]            = csr2trace_mie_mtie_i;
    csr_trace1.mie[SCR1_CSR_MIE_MEIE_OFFSET]            = csr2trace_mie_meie_i;
    csr_trace1.mip[SCR1_CSR_MIE_MSIE_OFFSET]            = csr2trace_mip_msip_i;
    csr_trace1.mip[SCR1_CSR_MIE_MTIE_OFFSET]            = csr2trace_mip_mtip_i;
    csr_trace1.mip[SCR1_CSR_MIE_MEIE_OFFSET]            = csr2trace_mip_meip_i;
end
 
`endif // SCR1_TRACE_LOG_EN
 
endmodule : scr1_tracelog
 
`endif // SCR1_TRGT_SIMULATION

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [pipeline/] [scr1_tracelog.sv] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details`
2			`/// @file`
3			`/// @brief Core tracelog module`
4			`///`
5
6			`include "scr1_arch_description.svh"
7			`include "scr1_arch_types.svh"
8			`include "scr1_csr.svh"
9
10			`ifdef SCR1_TRGT_SIMULATION
11
12			`module scr1_tracelog (`
13			`input logic rst_n, // Tracelog reset`
14			`input logic clk, // Tracelog clock`
15			input logic [`SCR1_XLEN-1:0] soc2pipe_fuse_mhartid_i, // Fuse MHARTID
16
17			`// MPRF`
18			`ifdef SCR1_MPRF_RAM
19			input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
20			`else // SCR1_MPRF_RAM
21			input type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i, // MPRF registers content
22			`endif // SCR1_MPRF_RAM
23			`input logic mprf2trace_wr_en_i, // MPRF write enable`
24			input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
25			input logic [`SCR1_XLEN-1:0] mprf2trace_wr_data_i, // MPRF write data
26
27			`// EXU`
28			`input logic exu2trace_update_pc_en_i, // PC updated flag`
29			input logic [`SCR1_XLEN-1:0] exu2trace_update_pc_i, // Next PC value
30
31			`// IFU`
32			input logic [`SCR1_IMEM_DWIDTH-1:0] ifu2trace_instr_i, // Current instruction from IFU stage
33
34			`// CSR`
35			`input logic csr2trace_mstatus_mie_i, // CSR MSTATUS.mie bit`
36			`input logic csr2trace_mstatus_mpie_i, // CSR MSTATUS.mpie bit`
37			input logic [`SCR1_XLEN-1:6] csr2trace_mtvec_base_i, // CSR MTVEC.
38			`input logic csr2trace_mtvec_mode_i, // CSR MTVEC.`
39			`input logic csr2trace_mie_meie_i, // CSR MIE.meie bit`
40			`input logic csr2trace_mie_mtie_i, // CSR MIE.mtie bit`
41			`input logic csr2trace_mie_msie_i, // CSR MIE.msie bit`
42			`input logic csr2trace_mip_meip_i, // CSR MIP.meip bit`
43			`input logic csr2trace_mip_mtip_i, // CSR MIP.mtip bit`
44			`input logic csr2trace_mip_msip_i, // CSR MIP.msip bit`
45			`ifdef SCR1_RVC_EXT
46			input logic [`SCR1_XLEN-1:1] csr2trace_mepc_i, // CSR MEPC register
47			`else // SCR1_RVC_EXT
48			input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
49			`endif // SCR1_RVC_EXT
50			`input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit`
51			`input type_scr1_exc_code_e csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit`
52			input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
53			`input logic csr2trace_mstatus_mie_up_i, // CSR MSTATUS.mie update flag`
54
55			`// Events`
56			`input logic csr2trace_e_exc_i, // exception event`
57			`input logic csr2trace_e_irq_i, // interrupt event`
58			`input logic pipe2trace_e_wake_i, // pipe wakeup event`
59			`input logic csr2trace_e_mret_i // MRET instruction`
60			`);`
61
62			`//-------------------------------------------------------------------------------`
63			`// Local types declaration`
64			`//-------------------------------------------------------------------------------`
65			`typedef struct {`
66			logic [`SCR1_XLEN-1:0] INT_00_ZERO ;
67			logic [`SCR1_XLEN-1:0] INT_01_RA ;
68			logic [`SCR1_XLEN-1:0] INT_02_SP ;
69			logic [`SCR1_XLEN-1:0] INT_03_GP ;
70			logic [`SCR1_XLEN-1:0] INT_04_TP ;
71			logic [`SCR1_XLEN-1:0] INT_05_T0 ;
72			logic [`SCR1_XLEN-1:0] INT_06_T1 ;
73			logic [`SCR1_XLEN-1:0] INT_07_T2 ;
74			logic [`SCR1_XLEN-1:0] INT_08_S0 ;
75			logic [`SCR1_XLEN-1:0] INT_09_S1 ;
76			logic [`SCR1_XLEN-1:0] INT_10_A0 ;
77			logic [`SCR1_XLEN-1:0] INT_11_A1 ;
78			logic [`SCR1_XLEN-1:0] INT_12_A2 ;
79			logic [`SCR1_XLEN-1:0] INT_13_A3 ;
80			logic [`SCR1_XLEN-1:0] INT_14_A4 ;
81			logic [`SCR1_XLEN-1:0] INT_15_A5 ;
82			`ifndef SCR1_RVE_EXT
83			logic [`SCR1_XLEN-1:0] INT_16_A6 ;
84			logic [`SCR1_XLEN-1:0] INT_17_A7 ;
85			logic [`SCR1_XLEN-1:0] INT_18_S2 ;
86			logic [`SCR1_XLEN-1:0] INT_19_S3 ;
87			logic [`SCR1_XLEN-1:0] INT_20_S4 ;
88			logic [`SCR1_XLEN-1:0] INT_21_S5 ;
89			logic [`SCR1_XLEN-1:0] INT_22_S6 ;
90			logic [`SCR1_XLEN-1:0] INT_23_S7 ;
91			logic [`SCR1_XLEN-1:0] INT_24_S8 ;
92			logic [`SCR1_XLEN-1:0] INT_25_S9 ;
93			logic [`SCR1_XLEN-1:0] INT_26_S10 ;
94			logic [`SCR1_XLEN-1:0] INT_27_S11 ;
95			logic [`SCR1_XLEN-1:0] INT_28_T3 ;
96			logic [`SCR1_XLEN-1:0] INT_29_T4 ;
97			logic [`SCR1_XLEN-1:0] INT_30_T5 ;
98			logic [`SCR1_XLEN-1:0] INT_31_T6 ;
99			`endif // SCR1_RVE_EXT
100			`} type_scr1_ireg_name_s;`
101
102			`typedef struct packed {`
103			logic [`SCR1_XLEN-1:0] mstatus;
104			logic [`SCR1_XLEN-1:0] mtvec;
105			logic [`SCR1_XLEN-1:0] mie;
106			logic [`SCR1_XLEN-1:0] mip;
107			logic [`SCR1_XLEN-1:0] mepc;
108			logic [`SCR1_XLEN-1:0] mcause;
109			logic [`SCR1_XLEN-1:0] mtval;
110			`} type_scr1_csr_trace_s;`
111
112			`//-------------------------------------------------------------------------------`
113			`// Local Signal Declaration`
114			`//-------------------------------------------------------------------------------`
115
116			`type_scr1_ireg_name_s mprf_int_alias;`
117
118			`ifdef SCR1_TRACE_LOG_EN
119
120			`time current_time;`
121
122			`// Tracelog control signals`
123			`logic trace_flag;`
124			`logic trace_update;`
125			`logic trace_update_r;`
126			`byte event_type;`
127
128			logic [`SCR1_XLEN-1:0] trace_pc;
129			logic [`SCR1_XLEN-1:0] trace_npc;
130			logic [`SCR1_IMEM_DWIDTH-1:0] trace_instr;
131
132			`type_scr1_csr_trace_s csr_trace1;`
133
134			`// File handlers`
135			`int unsigned trace_fhandler_core;`
136
137			`// MPRF signals`
138			`logic mprf_up;`
139			logic [`SCR1_MPRF_AWIDTH-1:0] mprf_addr;
140			logic [`SCR1_XLEN-1:0] mprf_wdata;
141
142			`string hart;`
143			`string test_name;`
144
145			`endif // SCR1_TRACE_LOG_EN
146
147			`//-------------------------------------------------------------------------------`
148			`// Local tasks`
149			`//-------------------------------------------------------------------------------`
150
151			`ifdef SCR1_TRACE_LOG_EN
152
153			`task trace_write_common;`
154			`$fwrite(trace_fhandler_core, "%16d ", current_time);`
155			`// $fwrite(trace_fhandler_core, " 0 ");`
156			`$fwrite(trace_fhandler_core, " %s ", event_type);`
157			`$fwrite(trace_fhandler_core, " %8x ", trace_pc);`
158			`$fwrite(trace_fhandler_core, " %8x ", trace_instr);`
159			`$fwrite(trace_fhandler_core, " %8x ", trace_npc);`
160			`endtask // trace_write_common`
161
162			`task trace_write_int_walias;`
163			`case (mprf_addr)`
164
165			`1 : $fwrite(trace_fhandler_core, " x01_ra ");`
166			`2 : $fwrite(trace_fhandler_core, " x02_sp ");`
167			`3 : $fwrite(trace_fhandler_core, " x03_gp ");`
168			`4 : $fwrite(trace_fhandler_core, " x04_tp ");`
169			`5 : $fwrite(trace_fhandler_core, " x05_t0 ");`
170			`6 : $fwrite(trace_fhandler_core, " x06_t1 ");`
171			`7 : $fwrite(trace_fhandler_core, " x07_t2 ");`
172			`8 : $fwrite(trace_fhandler_core, " x08_s0 ");`
173			`9 : $fwrite(trace_fhandler_core, " x09_s1 ");`
174			`10 : $fwrite(trace_fhandler_core, " x10_a0 ");`
175			`11 : $fwrite(trace_fhandler_core, " x11_a1 ");`
176			`12 : $fwrite(trace_fhandler_core, " x12_a2 ");`
177			`13 : $fwrite(trace_fhandler_core, " x13_a3 ");`
178			`14 : $fwrite(trace_fhandler_core, " x14_a4 ");`
179			`15 : $fwrite(trace_fhandler_core, " x15_a5 ");`
180			`ifndef SCR1_RVE_EXT
181			`16 : $fwrite(trace_fhandler_core, " x16_a6 ");`
182			`17 : $fwrite(trace_fhandler_core, " x17_a7 ");`
183			`18 : $fwrite(trace_fhandler_core, " x18_s2 ");`
184			`19 : $fwrite(trace_fhandler_core, " x19_s3 ");`
185			`20 : $fwrite(trace_fhandler_core, " x20_s4 ");`
186			`21 : $fwrite(trace_fhandler_core, " x21_s5 ");`
187			`22 : $fwrite(trace_fhandler_core, " x22_s6 ");`
188			`23 : $fwrite(trace_fhandler_core, " x23_s7 ");`
189			`24 : $fwrite(trace_fhandler_core, " x24_s8 ");`
190			`25 : $fwrite(trace_fhandler_core, " x25_s9 ");`
191			`26 : $fwrite(trace_fhandler_core, " x26_s10 ");`
192			`27 : $fwrite(trace_fhandler_core, " x27_s11 ");`
193			`28 : $fwrite(trace_fhandler_core, " x28_t3 ");`
194			`29 : $fwrite(trace_fhandler_core, " x29_t4 ");`
195			`30 : $fwrite(trace_fhandler_core, " x30_t5 ");`
196			`31 : $fwrite(trace_fhandler_core, " x31_t6 ");`
197			`endif // SCR1_RVE_EXT
198			`default: begin`
199			`$fwrite(trace_fhandler_core, " xxx ");`
200			`end`
201			`endcase`
202			`endtask`
203
204			`endif // SCR1_TRACE_LOG_EN
205
206			`//-------------------------------------------------------------------------------`
207			`// MPRF Registers assignment`
208			`//-------------------------------------------------------------------------------`
209			`assign mprf_int_alias.INT_00_ZERO = '0;`
210			`assign mprf_int_alias.INT_01_RA = mprf2trace_int_i[1];`
211			`assign mprf_int_alias.INT_02_SP = mprf2trace_int_i[2];`
212			`assign mprf_int_alias.INT_03_GP = mprf2trace_int_i[3];`
213			`assign mprf_int_alias.INT_04_TP = mprf2trace_int_i[4];`
214			`assign mprf_int_alias.INT_05_T0 = mprf2trace_int_i[5];`
215			`assign mprf_int_alias.INT_06_T1 = mprf2trace_int_i[6];`
216			`assign mprf_int_alias.INT_07_T2 = mprf2trace_int_i[7];`
217			`assign mprf_int_alias.INT_08_S0 = mprf2trace_int_i[8];`
218			`assign mprf_int_alias.INT_09_S1 = mprf2trace_int_i[9];`
219			`assign mprf_int_alias.INT_10_A0 = mprf2trace_int_i[10];`
220			`assign mprf_int_alias.INT_11_A1 = mprf2trace_int_i[11];`
221			`assign mprf_int_alias.INT_12_A2 = mprf2trace_int_i[12];`
222			`assign mprf_int_alias.INT_13_A3 = mprf2trace_int_i[13];`
223			`assign mprf_int_alias.INT_14_A4 = mprf2trace_int_i[14];`
224			`assign mprf_int_alias.INT_15_A5 = mprf2trace_int_i[15];`
225			`ifndef SCR1_RVE_EXT
226			`assign mprf_int_alias.INT_16_A6 = mprf2trace_int_i[16];`
227			`assign mprf_int_alias.INT_17_A7 = mprf2trace_int_i[17];`
228			`assign mprf_int_alias.INT_18_S2 = mprf2trace_int_i[18];`
229			`assign mprf_int_alias.INT_19_S3 = mprf2trace_int_i[19];`
230			`assign mprf_int_alias.INT_20_S4 = mprf2trace_int_i[20];`
231			`assign mprf_int_alias.INT_21_S5 = mprf2trace_int_i[21];`
232			`assign mprf_int_alias.INT_22_S6 = mprf2trace_int_i[22];`
233			`assign mprf_int_alias.INT_23_S7 = mprf2trace_int_i[23];`
234			`assign mprf_int_alias.INT_24_S8 = mprf2trace_int_i[24];`
235			`assign mprf_int_alias.INT_25_S9 = mprf2trace_int_i[25];`
236			`assign mprf_int_alias.INT_26_S10 = mprf2trace_int_i[26];`
237			`assign mprf_int_alias.INT_27_S11 = mprf2trace_int_i[27];`
238			`assign mprf_int_alias.INT_28_T3 = mprf2trace_int_i[28];`
239			`assign mprf_int_alias.INT_29_T4 = mprf2trace_int_i[29];`
240			`assign mprf_int_alias.INT_30_T5 = mprf2trace_int_i[30];`
241			`assign mprf_int_alias.INT_31_T6 = mprf2trace_int_i[31];`
242			`endif // SCR1_RVE_EXT
243
244			`//-------------------------------------------------------------------------------`
245			`// Legacy time counter`
246			`//-------------------------------------------------------------------------------`
247			`// The counter is left for compatibility with the current UVM environment`
248
249			`int time_cnt;`
250
251			`always_ff @(negedge rst_n, posedge clk) begin`
252			`if (~rst_n) begin`
253			`time_cnt <= 0;`
254			`end else begin`
255			`time_cnt <= time_cnt + 1;`
256			`end`
257			`end`
258
259			`//-------------------------------------------------------------------------------`
260			`// Initial part pipeline tracelog`
261			`//-------------------------------------------------------------------------------`
262
263			`ifdef SCR1_TRACE_LOG_EN
264			`// Files opening and writing initial header`
265			`initial begin`
266			`$timeformat(-9, 0, " ns", 10);`
267			`#1 hart.hextoa(soc2pipe_fuse_mhartid_i);`
268
269			`trace_fhandler_core = $fopen({"tracelog_core_", hart, ".log"}, "w");`
270
271			`// Writing initial header`
272			`$fwrite(trace_fhandler_core, "# RTL_ID %h\n", SCR1_CSR_MIMPID);`
273			`$fwrite(trace_fhandler_core, "#\n");`
274			`// $fwrite(trace_fhandler_core, "# R - return from trap:\n");`
275			`// $fwrite(trace_fhandler_core, "# 1 - MRET\n");`
276			`// $fwrite(trace_fhandler_core, "# 0 - no return\n");`
277			`$fwrite(trace_fhandler_core, "# Events:\n");`
278			`$fwrite(trace_fhandler_core, "# N - no event\n");`
279			`$fwrite(trace_fhandler_core, "# E - exception\n");`
280			`$fwrite(trace_fhandler_core, "# I - interrupt\n");`
281			`$fwrite(trace_fhandler_core, "# W - wakeup\n");`
282			`end`
283
284			`// Core reset logging and header printing`
285			`always @(posedge rst_n) begin`
286			`$fwrite(trace_fhandler_core, "# =====================================================================================\n");`
287			`ifndef VERILATOR
288			`$fwrite(trace_fhandler_core, "# %14t : Core Reset\n", $time());`
289			`else
290			`$fwrite(trace_fhandler_core, "# : Core Reset\n");`
291			`endif
292			`$fwrite(trace_fhandler_core, "# =====================================================================================\n");`
293			`$fwrite(trace_fhandler_core, "# Test: %s\n", test_name);`
294			`$fwrite(trace_fhandler_core, "# Time ");`
295			`// $fwrite(trace_fhandler_core, " R ");`
296			`$fwrite(trace_fhandler_core, " Ev ");`
297			`$fwrite(trace_fhandler_core, " Curr_PC ");`
298			`$fwrite(trace_fhandler_core, " Instr ");`
299			`$fwrite(trace_fhandler_core, " Next_PC ");`
300			`$fwrite(trace_fhandler_core, " Reg ");`
301			`$fwrite(trace_fhandler_core, " Value ");`
302			`$fwrite(trace_fhandler_core, "\n");`
303			`$fwrite(trace_fhandler_core, "# =====================================================================================\n");`
304			`end`
305
306			`//-------------------------------------------------------------------------------`
307			`// Common trace part`
308			`//-------------------------------------------------------------------------------`
309
310			`assign trace_flag = 1'b1;`
311			`assign trace_update = (exu2trace_update_pc_en_i \| mprf2trace_wr_en_i) & trace_flag;`
312
313			`always_ff @(posedge clk) begin`
314			`if (~rst_n) begin`
315			`current_time <= 0;`
316			`event_type <= "N";`
317
318			`trace_pc <= 'x;`
319			`trace_npc <= 'x;`
320			`trace_instr <= 'x;`
321
322			`trace_update_r <= 1'b0;`
323
324			`mprf_up <= '0;`
325			`mprf_addr <= '0;`
326			`mprf_wdata <= '0;`
327			`end else begin`
328			`trace_update_r <= trace_update;`
329			`if (trace_update) begin`
330			`ifdef VERILATOR
331			`current_time <= time_cnt;`
332			`else
333			`current_time <= $time();`
334			`endif
335			`trace_pc <= trace_npc;`
336			`trace_npc <= exu2trace_update_pc_i;`
337			`trace_instr <= ifu2trace_instr_i;`
338
339			`if (csr2trace_e_exc_i) begin`
340			`// Exception`
341			`event_type <= "E";`
342			`end`
343			`else if (csr2trace_e_irq_i) begin`
344			`// IRQ`
345			`event_type <= "I";`
346			`end`
347			`else if (pipe2trace_e_wake_i) begin`
348			`// Wake`
349			`event_type <= "W";`
350			`end`
351			`// if (csr2trace_e_mret_i) begin`
352			`// // MRET`
353			`// event_type <= "R";`
354			`// end`
355			`else begin`
356			`// No event`
357			`event_type <= "N";`
358			`end`
359			`end`
360
361			`// Write log signals`
362			`mprf_up <= mprf2trace_wr_en_i;`
363			`mprf_addr <= mprf2trace_wr_en_i ? mprf2trace_wr_addr_i : 'x;`
364			`mprf_wdata <= mprf2trace_wr_en_i ? mprf2trace_wr_data_i : 'x;`
365			`end`
366			`end`
367
368			`//-------------------------------------------------------------------------------`
369			`// Core MPRF logging`
370			`//-------------------------------------------------------------------------------`
371
372			`always_ff @(negedge rst_n, posedge clk) begin`
373			`if (~rst_n) begin`
374			`end else begin`
375			`if (trace_update_r) begin`
376
377			`trace_write_common();`
378
379			`case (event_type)`
380			`"W" : begin`
381			`// Wakeup`
382			`if (csr_trace1.mip & csr_trace1.mie) begin`
383			`$fwrite(trace_fhandler_core, " mip %08x\n", csr_trace1.mip );`
384			`trace_write_common();`
385			`$fwrite(trace_fhandler_core, " mie %08x", csr_trace1.mie );`
386			`end`
387			`end`
388			`"N" : begin`
389			`// Regular`
390			`if (mprf_up && mprf_addr != 0) begin`
391			`// $fwrite(trace_fhandler_core, " x%2d %08x", mprf_addr, mprf_wdata);`
392			`trace_write_int_walias();`
393			`$fwrite(trace_fhandler_core, " %08x", mprf_wdata);`
394			`end else begin`
395			`$fwrite(trace_fhandler_core, " --- --------");`
396			`end`
397			`end`
398			`"R" : begin`
399			`// MRET`
400			`$fwrite(trace_fhandler_core, " mstatus %08x", csr_trace1.mstatus);`
401			`end`
402			`"E", "I": begin`
403			`// IRQ/Exception`
404			`$fwrite(trace_fhandler_core, " mstatus %08x\n", csr_trace1.mstatus);`
405			`trace_write_common();`
406			`$fwrite(trace_fhandler_core, " mepc %08x\n", csr_trace1.mepc);`
407			`trace_write_common();`
408			`$fwrite(trace_fhandler_core, " mcause %08x\n", csr_trace1.mcause);`
409			`trace_write_common();`
410			`$fwrite(trace_fhandler_core, " mtval %08x", csr_trace1.mtval);`
411			`end`
412			`default : begin`
413			`$fwrite(trace_fhandler_core, "\n");`
414			`end`
415			`endcase`
416			`$fwrite(trace_fhandler_core, "\n");`
417			`end`
418			`end`
419			`end`
420
421			`//-------------------------------------------------------------------------------`
422			`// Core CSR logging`
423			`//-------------------------------------------------------------------------------`
424
425			`always_comb begin`
426			`csr_trace1.mtvec = {csr2trace_mtvec_base_i, 4'd0, 2'(csr2trace_mtvec_mode_i)};`
427			`csr_trace1.mepc =`
428			`ifdef SCR1_RVC_EXT
429			`{csr2trace_mepc_i, 1'b0};`
430			`else // SCR1_RVC_EXT
431			`{csr2trace_mepc_i, 2'b00};`
432			`endif // SCR1_RVC_EXT
433			`csr_trace1.mcause = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};`
434			`csr_trace1.mtval = csr2trace_mtval_i;`
435
436			`csr_trace1.mstatus = '0;`
437			`csr_trace1.mie = '0;`
438			`csr_trace1.mip = '0;`
439
440			`csr_trace1.mstatus[SCR1_CSR_MSTATUS_MIE_OFFSET] = csr2trace_mstatus_mie_i;`
441			`csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPIE_OFFSET] = csr2trace_mstatus_mpie_i;`
442			`csr_trace1.mstatus[SCR1_CSR_MSTATUS_MPP_OFFSET+1:SCR1_CSR_MSTATUS_MPP_OFFSET] = SCR1_CSR_MSTATUS_MPP;`
443			`csr_trace1.mie[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mie_msie_i;`
444			`csr_trace1.mie[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mie_mtie_i;`
445			`csr_trace1.mie[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mie_meie_i;`
446			`csr_trace1.mip[SCR1_CSR_MIE_MSIE_OFFSET] = csr2trace_mip_msip_i;`
447			`csr_trace1.mip[SCR1_CSR_MIE_MTIE_OFFSET] = csr2trace_mip_mtip_i;`
448			`csr_trace1.mip[SCR1_CSR_MIE_MEIE_OFFSET] = csr2trace_mip_meip_i;`
449			`end`
450
451			`endif // SCR1_TRACE_LOG_EN
452
453			`endmodule : scr1_tracelog`
454
455			`endif // SCR1_TRGT_SIMULATION