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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [primitives/] [scr1_reset_cells.sv] - Blame information for rev 11

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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
/// @file       
/// @brief      Cells for reset handling
///
 
//--------------------------------------------------------------------
// Reset Buffer Cell
//--------------------------------------------------------------------
module scr1_reset_buf_cell (
    input   logic           rst_n,
    input   logic           clk,
    input   logic           test_mode,
    input   logic           test_rst_n,
    input   logic           reset_n_in,
    output  logic           reset_n_out,
    output  logic           reset_n_status
);
 
logic       reset_n_ff;
logic       reset_n_status_ff;
logic       rst_n_mux;
 
assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
 
always_ff @(negedge rst_n_mux, posedge clk) begin
    if (~rst_n_mux) begin
        reset_n_ff <= 1'b0;
    end else begin
        reset_n_ff <= reset_n_in;
    end
end
 
assign reset_n_out = (test_mode == 1'b1) ? test_rst_n : reset_n_ff;
 
always_ff @(negedge rst_n_mux, posedge clk) begin
    if (~rst_n_mux) begin
        reset_n_status_ff <= 1'b0;
    end else begin
        reset_n_status_ff <= reset_n_in;
    end
end
assign reset_n_status = reset_n_status_ff;
 
endmodule : scr1_reset_buf_cell
 
//--------------------------------------------------------------------
// Reset CDC Synchronization Cell
//--------------------------------------------------------------------
module scr1_reset_sync_cell #(
    parameter int unsigned STAGES_AMOUNT = 2
) (
    input   logic           rst_n,
    input   logic           clk,
    input   logic           test_rst_n,
    input   logic           test_mode,
    input   logic           rst_n_in,
    output  logic           rst_n_out
);
 
logic [STAGES_AMOUNT-1:0]   rst_n_dff;
logic                       local_rst_n_in;
 
assign local_rst_n_in = (test_mode == 1'b1) ? test_rst_n : rst_n;
 
generate
 
if (STAGES_AMOUNT == 1)
 
begin : gen_reset_sync_cell_single
    always_ff @(negedge local_rst_n_in, posedge clk) begin
        if (~local_rst_n_in) begin
            rst_n_dff <= 1'b0;
        end else begin
            rst_n_dff <= rst_n_in;
        end
    end
end : gen_reset_sync_cell_single
 
else // STAGES_AMOUNT > 1
 
begin : gen_reset_sync_cell_multi
    always_ff @(negedge local_rst_n_in, posedge clk)
    begin
        if (~local_rst_n_in) begin
            rst_n_dff <= '0;
        end else begin
            rst_n_dff <= {rst_n_dff[STAGES_AMOUNT-2:0], rst_n_in};
        end
    end
end : gen_reset_sync_cell_multi
 
endgenerate
 
assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_dff[STAGES_AMOUNT-1];
 
endmodule : scr1_reset_sync_cell
 
//--------------------------------------------------------------------
// Data CDC/RDC Synchronization Cell
//--------------------------------------------------------------------
module scr1_data_sync_cell #(
    parameter int unsigned  STAGES_AMOUNT = 1
) (
    input   logic           rst_n,
    input   logic           clk,
    input   logic           data_in,
    output  logic           data_out
);
 
logic [STAGES_AMOUNT-1:0] data_dff;
 
generate
 
if (STAGES_AMOUNT == 1)
 
begin : gen_data_sync_cell_single
    always_ff @(negedge rst_n, posedge clk)
    begin
        if (~rst_n) begin
            data_dff <= 1'b0;
        end else begin
            data_dff <= data_in;
        end
    end
end : gen_data_sync_cell_single
 
else // STAGES_AMOUNT > 1
 
begin : gen_data_sync_cell_multi
    always_ff @(negedge rst_n, posedge clk)
    begin
        if (~rst_n) begin
            data_dff <= '0;
        end else begin
            data_dff <= {data_dff[STAGES_AMOUNT-2:0], data_in};
        end
    end
end : gen_data_sync_cell_multi
 
endgenerate
 
assign data_out = data_dff[STAGES_AMOUNT-1];
 
endmodule : scr1_data_sync_cell
 
//--------------------------------------------------------------------
// Reset / RDC Qualifyer Adapter Cell
//   (Reset Generation Cell w/ RDC Qualifyer Adaptation circuitry)
//--------------------------------------------------------------------
// Total stages amount =
//    1 Front Sync stage \
//  + 1 (delay introduced by the reset output buffer register)
//--------------------------------------------------------------------
module scr1_reset_qlfy_adapter_cell_sync (
    input   logic           rst_n,
    input   logic           clk,
    input   logic           test_rst_n,
    input   logic           test_mode,
    input   logic           reset_n_in_sync,
    output  logic           reset_n_out_qlfy,
    output  logic           reset_n_out,
    output  logic           reset_n_status
);
 
logic rst_n_mux;
logic reset_n_front_ff;
 
// Front sync stage
assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;
 
always_ff @(negedge rst_n_mux, posedge clk) begin
    if (~rst_n_mux) begin
        reset_n_front_ff    <= 1'b0;
    end else begin
        reset_n_front_ff    <= reset_n_in_sync;
    end
end
 
//   Sync reset output for all reset qualifier chains targeting this reset domain
// (for reset-domain-crossings with the given reset domain as a destination).
assign reset_n_out_qlfy = reset_n_front_ff;
 
// Reset output buffer
scr1_reset_buf_cell
i_reset_output_buf (
    .rst_n              (rst_n),
    .clk                (clk),
    .test_mode          (test_mode),
    .test_rst_n         (test_rst_n),
    .reset_n_in         (reset_n_front_ff),
    .reset_n_out        (reset_n_out),
    .reset_n_status     (reset_n_status)
);
 
endmodule : scr1_reset_qlfy_adapter_cell_sync
 
module scr1_reset_and2_cell (
    input   logic [1:0]     rst_n_in,
    input   logic           test_rst_n,
    input   logic           test_mode,
    output  logic           rst_n_out
);
 
assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
 
endmodule : scr1_reset_and2_cell
 
 
module scr1_reset_and3_cell (
    input   logic [2:0]     rst_n_in,
    input   logic           test_rst_n,
    input   logic           test_mode,
    output  logic           rst_n_out
);
 
assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);
 
endmodule : scr1_reset_and3_cell
 
 
module scr1_reset_mux2_cell (
    input   logic [1:0]     rst_n_in,
    input   logic           select,
    input   logic           test_rst_n,
    input   logic           test_mode,
    output  logic           rst_n_out
);
 
assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_in[select];
 
endmodule : scr1_reset_mux2_cell

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [primitives/] [scr1_reset_cells.sv] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details`
2			`/// @file`
3			`/// @brief Cells for reset handling`
4			`///`
5
6			`//--------------------------------------------------------------------`
7			`// Reset Buffer Cell`
8			`//--------------------------------------------------------------------`
9			`module scr1_reset_buf_cell (`
10			`input logic rst_n,`
11			`input logic clk,`
12			`input logic test_mode,`
13			`input logic test_rst_n,`
14			`input logic reset_n_in,`
15			`output logic reset_n_out,`
16			`output logic reset_n_status`
17			`);`
18
19			`logic reset_n_ff;`
20			`logic reset_n_status_ff;`
21			`logic rst_n_mux;`
22
23			`assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;`
24
25			`always_ff @(negedge rst_n_mux, posedge clk) begin`
26			`if (~rst_n_mux) begin`
27			`reset_n_ff <= 1'b0;`
28			`end else begin`
29			`reset_n_ff <= reset_n_in;`
30			`end`
31			`end`
32
33			`assign reset_n_out = (test_mode == 1'b1) ? test_rst_n : reset_n_ff;`
34
35			`always_ff @(negedge rst_n_mux, posedge clk) begin`
36			`if (~rst_n_mux) begin`
37			`reset_n_status_ff <= 1'b0;`
38			`end else begin`
39			`reset_n_status_ff <= reset_n_in;`
40			`end`
41			`end`
42			`assign reset_n_status = reset_n_status_ff;`
43
44			`endmodule : scr1_reset_buf_cell`
45
46			`//--------------------------------------------------------------------`
47			`// Reset CDC Synchronization Cell`
48			`//--------------------------------------------------------------------`
49			`module scr1_reset_sync_cell #(`
50			`parameter int unsigned STAGES_AMOUNT = 2`
51			`) (`
52			`input logic rst_n,`
53			`input logic clk,`
54			`input logic test_rst_n,`
55			`input logic test_mode,`
56			`input logic rst_n_in,`
57			`output logic rst_n_out`
58			`);`
59
60			`logic [STAGES_AMOUNT-1:0] rst_n_dff;`
61			`logic local_rst_n_in;`
62
63			`assign local_rst_n_in = (test_mode == 1'b1) ? test_rst_n : rst_n;`
64
65			`generate`
66
67			`if (STAGES_AMOUNT == 1)`
68
69			`begin : gen_reset_sync_cell_single`
70			`always_ff @(negedge local_rst_n_in, posedge clk) begin`
71			`if (~local_rst_n_in) begin`
72			`rst_n_dff <= 1'b0;`
73			`end else begin`
74			`rst_n_dff <= rst_n_in;`
75			`end`
76			`end`
77			`end : gen_reset_sync_cell_single`
78
79			`else // STAGES_AMOUNT > 1`
80
81			`begin : gen_reset_sync_cell_multi`
82			`always_ff @(negedge local_rst_n_in, posedge clk)`
83			`begin`
84			`if (~local_rst_n_in) begin`
85			`rst_n_dff <= '0;`
86			`end else begin`
87			`rst_n_dff <= {rst_n_dff[STAGES_AMOUNT-2:0], rst_n_in};`
88			`end`
89			`end`
90			`end : gen_reset_sync_cell_multi`
91
92			`endgenerate`
93
94			`assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_dff[STAGES_AMOUNT-1];`
95
96			`endmodule : scr1_reset_sync_cell`
97
98			`//--------------------------------------------------------------------`
99			`// Data CDC/RDC Synchronization Cell`
100			`//--------------------------------------------------------------------`
101			`module scr1_data_sync_cell #(`
102			`parameter int unsigned STAGES_AMOUNT = 1`
103			`) (`
104			`input logic rst_n,`
105			`input logic clk,`
106			`input logic data_in,`
107			`output logic data_out`
108			`);`
109
110			`logic [STAGES_AMOUNT-1:0] data_dff;`
111
112			`generate`
113
114			`if (STAGES_AMOUNT == 1)`
115
116			`begin : gen_data_sync_cell_single`
117			`always_ff @(negedge rst_n, posedge clk)`
118			`begin`
119			`if (~rst_n) begin`
120			`data_dff <= 1'b0;`
121			`end else begin`
122			`data_dff <= data_in;`
123			`end`
124			`end`
125			`end : gen_data_sync_cell_single`
126
127			`else // STAGES_AMOUNT > 1`
128
129			`begin : gen_data_sync_cell_multi`
130			`always_ff @(negedge rst_n, posedge clk)`
131			`begin`
132			`if (~rst_n) begin`
133			`data_dff <= '0;`
134			`end else begin`
135			`data_dff <= {data_dff[STAGES_AMOUNT-2:0], data_in};`
136			`end`
137			`end`
138			`end : gen_data_sync_cell_multi`
139
140			`endgenerate`
141
142			`assign data_out = data_dff[STAGES_AMOUNT-1];`
143
144			`endmodule : scr1_data_sync_cell`
145
146			`//--------------------------------------------------------------------`
147			`// Reset / RDC Qualifyer Adapter Cell`
148			`// (Reset Generation Cell w/ RDC Qualifyer Adaptation circuitry)`
149			`//--------------------------------------------------------------------`
150			`// Total stages amount =`
151			`// 1 Front Sync stage \`
152			`// + 1 (delay introduced by the reset output buffer register)`
153			`//--------------------------------------------------------------------`
154			`module scr1_reset_qlfy_adapter_cell_sync (`
155			`input logic rst_n,`
156			`input logic clk,`
157			`input logic test_rst_n,`
158			`input logic test_mode,`
159			`input logic reset_n_in_sync,`
160			`output logic reset_n_out_qlfy,`
161			`output logic reset_n_out,`
162			`output logic reset_n_status`
163			`);`
164
165			`logic rst_n_mux;`
166			`logic reset_n_front_ff;`
167
168			`// Front sync stage`
169			`assign rst_n_mux = (test_mode == 1'b1) ? test_rst_n : rst_n;`
170
171			`always_ff @(negedge rst_n_mux, posedge clk) begin`
172			`if (~rst_n_mux) begin`
173			`reset_n_front_ff <= 1'b0;`
174			`end else begin`
175			`reset_n_front_ff <= reset_n_in_sync;`
176			`end`
177			`end`
178
179			`// Sync reset output for all reset qualifier chains targeting this reset domain`
180			`// (for reset-domain-crossings with the given reset domain as a destination).`
181			`assign reset_n_out_qlfy = reset_n_front_ff;`
182
183			`// Reset output buffer`
184			`scr1_reset_buf_cell`
185			`i_reset_output_buf (`
186			`.rst_n (rst_n),`
187			`.clk (clk),`
188			`.test_mode (test_mode),`
189			`.test_rst_n (test_rst_n),`
190			`.reset_n_in (reset_n_front_ff),`
191			`.reset_n_out (reset_n_out),`
192			`.reset_n_status (reset_n_status)`
193			`);`
194
195			`endmodule : scr1_reset_qlfy_adapter_cell_sync`
196
197			`module scr1_reset_and2_cell (`
198			`input logic [1:0] rst_n_in,`
199			`input logic test_rst_n,`
200			`input logic test_mode,`
201			`output logic rst_n_out`
202			`);`
203
204			`assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);`
205
206			`endmodule : scr1_reset_and2_cell`
207
208
209			`module scr1_reset_and3_cell (`
210			`input logic [2:0] rst_n_in,`
211			`input logic test_rst_n,`
212			`input logic test_mode,`
213			`output logic rst_n_out`
214			`);`
215
216			`assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : (&rst_n_in);`
217
218			`endmodule : scr1_reset_and3_cell`
219
220
221			`module scr1_reset_mux2_cell (`
222			`input logic [1:0] rst_n_in,`
223			`input logic select,`
224			`input logic test_rst_n,`
225			`input logic test_mode,`
226			`output logic rst_n_out`
227			`);`
228
229			`assign rst_n_out = (test_mode == 1'b1) ? test_rst_n : rst_n_in[select];`
230
231			`endmodule : scr1_reset_mux2_cell`