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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [scr1_core_top.sv] - Blame information for rev 21

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/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
/// @file       
/// @brief      SCR1 core top
///
 
`include "scr1_arch_description.svh"
`include "scr1_arch_types.svh"
`include "scr1_memif.svh"
 
`ifdef SCR1_DBG_EN
`include "scr1_tapc.svh"
`include "scr1_dm.svh"
`include "scr1_hdu.svh"
`endif // SCR1_DBG_EN
 
`ifdef SCR1_IPIC_EN
`include "scr1_ipic.svh"
`endif // SCR1_IPIC_EN
 
module scr1_core_top (
    // Common
    input   logic                                   pwrup_rst_n,                // Power-Up reset
    input   logic                                   rst_n,                      // Regular reset
    input   logic                                   cpu_rst_n,                  // CPU reset
    input   logic                                   test_mode,                  // DFT Test Mode
    input   logic                                   test_rst_n,                 // DFT Test Reset
    input   logic                                   clk,                        // Core clock
    output  logic                                   core_rst_n_o,               // Core reset
    output  logic                                   core_rdc_qlfy_o,            // Core RDC qualifier
`ifdef SCR1_DBG_EN
    output  logic                                   sys_rst_n_o,                // System reset
    output  logic                                   sys_rdc_qlfy_o,             // System RDC qualifier
`endif // SCR1_DBG_EN
 
    // Fuses
    input   logic [`SCR1_XLEN-1:0]                  core_fuse_mhartid_i,        // Fuse MHARTID value
`ifdef SCR1_DBG_EN
    input   logic [31:0]                            tapc_fuse_idcode_i,         // Fuse IDCODE value
`endif // SCR1_DBG_EN
 
    // IRQ
`ifdef SCR1_IPIC_EN
    input   logic [SCR1_IRQ_LINES_NUM-1:0]          core_irq_lines_i,           // External interrupt request lines
`else
    input   logic                                   core_irq_ext_i,             // External interrupt request
`endif // SCR1_IPIC_EN
    input   logic                                   core_irq_soft_i,            // Software generated interrupt request
    input   logic                                   core_irq_mtimer_i,          // Machine timer interrupt request
 
    // Memory-mapped external timer
    input   logic [63:0]                            core_mtimer_val_i,          // Machine timer value
 
`ifdef SCR1_DBG_EN
    // Debug Interface
    input   logic                                   tapc_trst_n,                // Test Reset (TRSTn)
    input   logic                                   tapc_tck,                   // Test Clock (TCK)
    input   logic                                   tapc_tms,                   // Test Mode Select (TMS)
    input   logic                                   tapc_tdi,                   // Test Data Input (TDI)
    output  logic                                   tapc_tdo,                   // Test Data Output (TDO)
    output  logic                                   tapc_tdo_en,                // TDO Enable, signal for TDO buffer control
`endif // SCR1_DBG_EN
 
    // Instruction Memory Interface
    input   logic                                   imem2core_req_ack_i,        // IMEM request acknowledge
    output  logic                                   core2imem_req_o,            // IMEM request
    output  logic                                   core2imem_cmd_o,            // IMEM command
    output  logic [`SCR1_IMEM_AWIDTH-1:0]           core2imem_addr_o,           // IMEM address
    input   logic [`SCR1_IMEM_DWIDTH-1:0]           imem2core_rdata_i,          // IMEM read data
    input   logic [1:0]                             imem2core_resp_i,           // IMEM response
 
    // Data Memory Interface
    input   logic                                   dmem2core_req_ack_i,        // DMEM request acknowledge
    output  logic                                   core2dmem_req_o,            // DMEM request
    output  logic                                   core2dmem_cmd_o,            // DMEM command
    output  logic[1:0]                             core2dmem_width_o,          // DMEM data width
    output  logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o,           // DMEM address
    output  logic [`SCR1_DMEM_DWIDTH-1:0]           core2dmem_wdata_o,          // DMEM write data
    input   logic [`SCR1_DMEM_DWIDTH-1:0]           dmem2core_rdata_i,          // DMEM read data
    input   logic [1:0]                             dmem2core_resp_i            // DMEM response
);
 
//-------------------------------------------------------------------------------
// Local parameters
//-------------------------------------------------------------------------------
localparam int unsigned SCR1_CORE_TOP_RST_SYNC_STAGES_NUM               = 2;
 
//-------------------------------------------------------------------------------
// Local signals declaration
//-------------------------------------------------------------------------------
 
// Reset Logic
`ifdef SCR1_DBG_EN
`else // SCR1_DBG_EN
logic                                           core_rst_n_in_sync;
logic                                           core_rst_n_qlfy;
logic                                           core_rst_n_status;
`endif // SCR1_DBG_EN
logic                                           core_rst_n;
logic                                           core_rst_n_status_sync;
logic                                           core_rst_status;
logic                                           core2hdu_rdc_qlfy;
logic                                           core2dm_rdc_qlfy;
logic                                           pwrup_rst_n_sync;
logic                                           rst_n_sync;
logic                                           cpu_rst_n_sync;
 
`ifdef SCR1_DBG_EN
// TAPC-DM Interface
logic                                           tapc_dmi_ch_sel;
logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]            tapc_dmi_ch_id;
logic                                           tapc_dmi_ch_capture;
logic                                           tapc_dmi_ch_shift;
logic                                           tapc_dmi_ch_update;
logic                                           tapc_dmi_ch_tdi;
logic                                           tapc_dmi_ch_tdo;
//
logic                                           tapc_dmi_ch_sel_tapout;
logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]            tapc_dmi_ch_id_tapout;
logic                                           tapc_dmi_ch_capture_tapout;
logic                                           tapc_dmi_ch_shift_tapout;
logic                                           tapc_dmi_ch_update_tapout;
logic                                           tapc_dmi_ch_tdi_tapout;
logic                                           tapc_dmi_ch_tdo_tapin;
//
logic                                           dmi_req;
logic                                           dmi_wr;
logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0]             dmi_addr;
logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]             dmi_wdata;
logic                                           dmi_resp;
logic [SCR1_DBG_DMI_DATA_WIDTH-1:0]             dmi_rdata;
// TAPC-SCU Interface
logic                                           tapc_scu_ch_sel;
logic                                           tapc_scu_ch_sel_tapout;
logic                                           tapc_scu_ch_tdo;
logic                                           tapc_ch_tdo;
// SCU nets
logic                                           sys_rst_n;
logic                                           sys_rst_status;
logic                                           hdu_rst_n;
logic                                           hdu2dm_rdc_qlfy;
logic                                           ndm_rst_n;
logic                                           dm_rst_n;
logic                                           hart_rst_n;
`endif // SCR1_DBG_EN
 
`ifdef SCR1_DBG_EN
// DM-Pipeline Interface
// HART Run Control i/f
logic                                           dm_active;
logic                                           dm_cmd_req;
type_scr1_hdu_dbgstates_e                       dm_cmd;
logic                                           dm_cmd_resp;
logic                                           dm_cmd_resp_qlfy;
logic                                           dm_cmd_rcode;
logic                                           dm_hart_event;
logic                                           dm_hart_event_qlfy;
type_scr1_hdu_hartstatus_s                      dm_hart_status;
type_scr1_hdu_hartstatus_s                      dm_hart_status_qlfy;
// Program Buffer - HART instruction execution i/f
logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]            dm_pbuf_addr;
logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0]            dm_pbuf_addr_qlfy;
logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0]           dm_pbuf_instr;
// HART Abstract Data regs i/f
logic                                           dm_dreg_req;
logic                                           dm_dreg_req_qlfy;
logic                                           dm_dreg_wr;
logic [SCR1_HDU_DATA_REG_WIDTH-1:0]             dm_dreg_wdata;
logic                                           dm_dreg_resp;
logic                                           dm_dreg_fail;
logic [SCR1_HDU_DATA_REG_WIDTH-1:0]             dm_dreg_rdata;
 
logic [`SCR1_XLEN-1 : 0]                        dm_pc_sample;
logic [`SCR1_XLEN-1 : 0]                        dm_pc_sample_qlfy;
`endif // SCR1_DBG_EN
 
`ifdef SCR1_CLKCTRL_EN
// Global clock gating logic
logic                                           sleep_pipe;
logic                                           wake_pipe;
logic                                           clk_pipe;
logic                                           clk_pipe_en;
logic                                           clk_dbgc;
logic                                           clk_alw_on;
`endif // SCR1_CLKCTRL_EN
 
 
//-------------------------------------------------------------------------------
// Reset Logic
//-------------------------------------------------------------------------------
`ifdef SCR1_DBG_EN
scr1_scu    i_scu (
    // Global signals
    .pwrup_rst_n                (pwrup_rst_n        ),
    .rst_n                      (rst_n              ),
    .cpu_rst_n                  (cpu_rst_n          ),
    .test_mode                  (test_mode          ),
    .test_rst_n                 (test_rst_n         ),
    .clk                        (clk                ),
 
    // TAPC scan-chains
    .tapcsync2scu_ch_sel_i      (tapc_scu_ch_sel    ),
    .tapcsync2scu_ch_id_i       ('0                 ),
    .tapcsync2scu_ch_capture_i  (tapc_dmi_ch_capture),
    .tapcsync2scu_ch_shift_i    (tapc_dmi_ch_shift  ),
    .tapcsync2scu_ch_update_i   (tapc_dmi_ch_update ),
    .tapcsync2scu_ch_tdi_i      (tapc_dmi_ch_tdi    ),
    .scu2tapcsync_ch_tdo_o      (tapc_scu_ch_tdo    ),
 
    // Input sync resets:
    .ndm_rst_n_i                (ndm_rst_n          ),
    .hart_rst_n_i               (hart_rst_n         ),
 
    // Generated resets
    .sys_rst_n_o                (sys_rst_n          ),
    .core_rst_n_o               (core_rst_n         ),
    .dm_rst_n_o                 (dm_rst_n           ),
    .hdu_rst_n_o                (hdu_rst_n          ),
 
    // Resets statuses
    .sys_rst_status_o           (sys_rst_status     ),
    .core_rst_status_o          (core_rst_status    ),
 
    // Reset Domain Crossing (RDC) qualifiers
    .sys_rdc_qlfy_o             (sys_rdc_qlfy_o     ),
    .core_rdc_qlfy_o            (core_rdc_qlfy_o    ),
    .core2hdu_rdc_qlfy_o        (core2hdu_rdc_qlfy  ),
    .core2dm_rdc_qlfy_o         (core2dm_rdc_qlfy   ),
    .hdu2dm_rdc_qlfy_o          (hdu2dm_rdc_qlfy    )
);
 
assign sys_rst_n_o      = sys_rst_n;
 
// Reset inputs are assumed synchronous
assign pwrup_rst_n_sync = pwrup_rst_n;
 
`else // SCR1_DBG_EN
 
// Reset inputs are assumed synchronous
assign pwrup_rst_n_sync   = pwrup_rst_n;
assign rst_n_sync         = rst_n;
assign cpu_rst_n_sync     = cpu_rst_n;
assign core_rst_n_in_sync = rst_n_sync & cpu_rst_n_sync;
 
// Core Reset: core_rst_n
scr1_reset_qlfy_adapter_cell_sync i_core_rstn_qlfy_adapter_cell_sync (
    .rst_n              (pwrup_rst_n_sync  ),
    .clk                (clk               ),
    .test_rst_n         (test_rst_n        ),
    .test_mode          (test_mode         ),
    .reset_n_in_sync    (core_rst_n_in_sync),
    .reset_n_out_qlfy   (core_rst_n_qlfy   ),
    .reset_n_out        (core_rst_n        ),
    .reset_n_status     (core_rst_n_status )
);
 
scr1_data_sync_cell #(
    .STAGES_AMOUNT      (SCR1_CORE_TOP_RST_SYNC_STAGES_NUM)
) i_core_rstn_status_sync (
    .rst_n               (pwrup_rst_n_sync      ),
    .clk                 (clk                   ),
    .data_in             (core_rst_n_status     ),
    .data_out            (core_rst_n_status_sync)
);
 
assign core_rst_status      = ~core_rst_n_status_sync;
assign core_rdc_qlfy_o      = core_rst_n_qlfy;
 
`endif // SCR1_DBG_EN
assign core_rst_n_o         = core_rst_n;
 
//-------------------------------------------------------------------------------
// SCR1 pipeline
//-------------------------------------------------------------------------------
scr1_pipe_top i_pipe_top (
    // Control
    .pipe_rst_n                     (core_rst_n             ),
`ifdef SCR1_DBG_EN
    .pipe2hdu_rdc_qlfy_i            (core2hdu_rdc_qlfy      ),
    .dbg_rst_n                      (hdu_rst_n              ),
`endif // SCR1_DBG_EN
`ifndef SCR1_CLKCTRL_EN
    .clk                            (clk                    ),
`else // SCR1_CLKCTRL_EN
    .clk                            (clk_pipe               ),
    .pipe2clkctl_sleep_req_o        (sleep_pipe             ),
    .pipe2clkctl_wake_req_o         (wake_pipe              ),
    .clkctl2pipe_clk_alw_on_i       (clk_alw_on             ),
    .clkctl2pipe_clk_dbgc_i         (clk_dbgc               ),
    .clkctl2pipe_clk_en_i           (clk_pipe_en            ),
`endif // SCR1_CLKCTRL_EN
 
    // Instruction memory interface
    .pipe2imem_req_o                (core2imem_req_o        ),
    .pipe2imem_cmd_o                (core2imem_cmd_o        ),
    .pipe2imem_addr_o               (core2imem_addr_o       ),
    .imem2pipe_req_ack_i            (imem2core_req_ack_i    ),
    .imem2pipe_rdata_i              (imem2core_rdata_i      ),
    .imem2pipe_resp_i               (imem2core_resp_i       ),
 
    // Data memory interface
    .pipe2dmem_req_o                (core2dmem_req_o        ),
    .pipe2dmem_cmd_o                (core2dmem_cmd_o        ),
    .pipe2dmem_width_o              (core2dmem_width_o      ),
    .pipe2dmem_addr_o               (core2dmem_addr_o       ),
    .pipe2dmem_wdata_o              (core2dmem_wdata_o      ),
    .dmem2pipe_req_ack_i            (dmem2core_req_ack_i    ),
    .dmem2pipe_rdata_i              (dmem2core_rdata_i      ),
    .dmem2pipe_resp_i               (dmem2core_resp_i       ),
 
`ifdef SCR1_DBG_EN
    // Debug interface:
    .dbg_en                         (1'b1                   ),
    // Debug interface:
    // DM <-> Pipeline: HART Run Control i/f
    .dm2pipe_active_i               (dm_active              ),
    .dm2pipe_cmd_req_i              (dm_cmd_req             ),
    .dm2pipe_cmd_i                  (dm_cmd                 ),
    .pipe2dm_cmd_resp_o             (dm_cmd_resp            ),
    .pipe2dm_cmd_rcode_o            (dm_cmd_rcode           ),
    .pipe2dm_hart_event_o           (dm_hart_event          ),
    .pipe2dm_hart_status_o          (dm_hart_status         ),
 
    // DM <-> Pipeline: Program Buffer - HART instruction execution i/f
    .pipe2dm_pbuf_addr_o            (dm_pbuf_addr           ),
    .dm2pipe_pbuf_instr_i           (dm_pbuf_instr          ),
 
    // DM <-> Pipeline: HART Abstract Data regs i/f
    .pipe2dm_dreg_req_o             (dm_dreg_req            ),
    .pipe2dm_dreg_wr_o              (dm_dreg_wr             ),
    .pipe2dm_dreg_wdata_o           (dm_dreg_wdata          ),
    .dm2pipe_dreg_resp_i            (dm_dreg_resp           ),
    .dm2pipe_dreg_fail_i            (dm_dreg_fail           ),
    .dm2pipe_dreg_rdata_i           (dm_dreg_rdata          ),
 
    // DM <-> Pipeline: PC i/f
    .pipe2dm_pc_sample_o            (dm_pc_sample           ),
`endif // SCR1_DBG_EN
 
    // IRQ
`ifdef SCR1_IPIC_EN
    .soc2pipe_irq_lines_i           (core_irq_lines_i       ),
`else // SCR1_IPIC_EN
    .soc2pipe_irq_ext_i             (core_irq_ext_i         ),
`endif // SCR1_IPIC_EN
    .soc2pipe_irq_soft_i            (core_irq_soft_i        ),
    .soc2pipe_irq_mtimer_i          (core_irq_mtimer_i      ),
 
    // Memory-mapped external timer
    .soc2pipe_mtimer_val_i          (core_mtimer_val_i      ),
 
    // Fuse
    .soc2pipe_fuse_mhartid_i        (core_fuse_mhartid_i    )
);
 
 
`ifdef SCR1_DBG_EN
//-------------------------------------------------------------------------------
// TAP Controller (TAPC)
//-------------------------------------------------------------------------------
scr1_tapc i_tapc (
    // JTAG signals
    .tapc_trst_n                    (tapc_trst_n               ),
    .tapc_tck                       (tapc_tck                  ),
    .tapc_tms                       (tapc_tms                  ),
    .tapc_tdi                       (tapc_tdi                  ),
    .tapc_tdo                       (tapc_tdo                  ),
    .tapc_tdo_en                    (tapc_tdo_en               ),
 
    // Fuses
    .soc2tapc_fuse_idcode_i         (tapc_fuse_idcode_i        ),
 
    // DMI/SCU scan-chains
    .tapc2tapcsync_scu_ch_sel_o     (tapc_scu_ch_sel_tapout    ),
    .tapc2tapcsync_dmi_ch_sel_o     (tapc_dmi_ch_sel_tapout    ),
    .tapc2tapcsync_ch_id_o          (tapc_dmi_ch_id_tapout     ),
    .tapc2tapcsync_ch_capture_o     (tapc_dmi_ch_capture_tapout),
    .tapc2tapcsync_ch_shift_o       (tapc_dmi_ch_shift_tapout  ),
    .tapc2tapcsync_ch_update_o      (tapc_dmi_ch_update_tapout ),
    .tapc2tapcsync_ch_tdi_o         (tapc_dmi_ch_tdi_tapout    ),
    .tapcsync2tapc_ch_tdo_i         (tapc_dmi_ch_tdo_tapin     )
);
 
scr1_tapc_synchronizer i_tapc_synchronizer (
    // System common signals
    .pwrup_rst_n                    (pwrup_rst_n_sync          ),
    .dm_rst_n                       (dm_rst_n                  ),
    .clk                            (clk                       ),
 
    // JTAG common signals
    .tapc_trst_n                    (tapc_trst_n               ),
    .tapc_tck                       (tapc_tck                  ),
 
    // DMI/SCU scan-chains
    .tapc2tapcsync_scu_ch_sel_i     (tapc_scu_ch_sel_tapout    ),
    .tapcsync2scu_ch_sel_o          (tapc_scu_ch_sel           ),
    .tapc2tapcsync_dmi_ch_sel_i     (tapc_dmi_ch_sel_tapout    ),
    .tapcsync2dmi_ch_sel_o          (tapc_dmi_ch_sel           ),
 
    .tapc2tapcsync_ch_id_i          (tapc_dmi_ch_id_tapout     ),
    .tapcsync2core_ch_id_o          (tapc_dmi_ch_id            ),
    .tapc2tapcsync_ch_capture_i     (tapc_dmi_ch_capture_tapout),
    .tapcsync2core_ch_capture_o     (tapc_dmi_ch_capture       ),
    .tapc2tapcsync_ch_shift_i       (tapc_dmi_ch_shift_tapout  ),
    .tapcsync2core_ch_shift_o       (tapc_dmi_ch_shift         ),
    .tapc2tapcsync_ch_update_i      (tapc_dmi_ch_update_tapout ),
    .tapcsync2core_ch_update_o      (tapc_dmi_ch_update        ),
    .tapc2tapcsync_ch_tdi_i         (tapc_dmi_ch_tdi_tapout    ),
    .tapcsync2core_ch_tdi_o         (tapc_dmi_ch_tdi           ),
    .tapc2tapcsync_ch_tdo_i         (tapc_dmi_ch_tdo_tapin     ),
    .tapcsync2core_ch_tdo_o         (tapc_ch_tdo               )
);
assign tapc_ch_tdo = (tapc_scu_ch_tdo & tapc_scu_ch_sel)
                   | (tapc_dmi_ch_tdo & tapc_dmi_ch_sel);
 
scr1_dmi i_dmi (
    .rst_n                      (dm_rst_n           ),
    .clk                        (clk                ),
 
    // TAP scan-chains
    .tapcsync2dmi_ch_sel_i      (tapc_dmi_ch_sel    ),
    .tapcsync2dmi_ch_id_i       (tapc_dmi_ch_id     ),
    .tapcsync2dmi_ch_capture_i  (tapc_dmi_ch_capture),
    .tapcsync2dmi_ch_shift_i    (tapc_dmi_ch_shift  ),
    .tapcsync2dmi_ch_update_i   (tapc_dmi_ch_update ),
    .tapcsync2dmi_ch_tdi_i      (tapc_dmi_ch_tdi    ),
    .dmi2tapcsync_ch_tdo_o      (tapc_dmi_ch_tdo    ),
 
    // DMI
    .dm2dmi_resp_i              (dmi_resp           ),
    .dm2dmi_rdata_i             (dmi_rdata          ),
    .dmi2dm_req_o               (dmi_req            ),
    .dmi2dm_wr_o                (dmi_wr             ),
    .dmi2dm_addr_o              (dmi_addr           ),
    .dmi2dm_wdata_o             (dmi_wdata          )
);
 
`endif // SCR1_DBG_EN
 
 
`ifdef SCR1_DBG_EN
 
//-------------------------------------------------------------------------------
// Debug Module (DM)
//-------------------------------------------------------------------------------
assign dm_cmd_resp_qlfy    = dm_cmd_resp   & {$bits(dm_cmd_resp){hdu2dm_rdc_qlfy}};
assign dm_hart_event_qlfy  = dm_hart_event & {$bits(dm_hart_event){hdu2dm_rdc_qlfy}};
assign dm_hart_status_qlfy.dbg_state = hdu2dm_rdc_qlfy ? dm_hart_status.dbg_state
                                                       : SCR1_HDU_DBGSTATE_RESET;
assign dm_hart_status_qlfy.except    = dm_hart_status.except;
assign dm_hart_status_qlfy.ebreak    = dm_hart_status.ebreak;
assign dm_pbuf_addr_qlfy   = dm_pbuf_addr  & {$bits(dm_pbuf_addr){hdu2dm_rdc_qlfy}};
assign dm_dreg_req_qlfy    = dm_dreg_req   & {$bits(dm_dreg_req){hdu2dm_rdc_qlfy}};
assign dm_pc_sample_qlfy   = dm_pc_sample  & {$bits(dm_pc_sample){core2dm_rdc_qlfy}};
 
scr1_dm i_dm (
    // Common signals
    .rst_n                      (dm_rst_n               ),
    .clk                        (clk                    ),
 
    // DM internal interface
    .dmi2dm_req_i               (dmi_req                ),
    .dmi2dm_wr_i                (dmi_wr                 ),
    .dmi2dm_addr_i              (dmi_addr               ),
    .dmi2dm_wdata_i             (dmi_wdata              ),
    .dm2dmi_resp_o              (dmi_resp               ),
    .dm2dmi_rdata_o             (dmi_rdata              ),
 
    // DM <-> Pipeline: HART Run Control i/f
    .ndm_rst_n_o                (ndm_rst_n              ),
    .hart_rst_n_o               (hart_rst_n             ),
    .dm2pipe_active_o           (dm_active              ),
    .dm2pipe_cmd_req_o          (dm_cmd_req             ),
    .dm2pipe_cmd_o              (dm_cmd                 ),
    .pipe2dm_cmd_resp_i         (dm_cmd_resp_qlfy       ),
    .pipe2dm_cmd_rcode_i        (dm_cmd_rcode           ),
    .pipe2dm_hart_event_i       (dm_hart_event_qlfy     ),
    .pipe2dm_hart_status_i      (dm_hart_status_qlfy    ),
 
    .soc2dm_fuse_mhartid_i      (core_fuse_mhartid_i    ),
    .pipe2dm_pc_sample_i        (dm_pc_sample_qlfy      ),
 
    // DM <-> Pipeline: HART Abstract Command / Program Buffer i/f
    .pipe2dm_pbuf_addr_i        (dm_pbuf_addr_qlfy      ),
    .dm2pipe_pbuf_instr_o       (dm_pbuf_instr          ),
 
    // DM <-> Pipeline: HART Abstract Data regs i/f
    .pipe2dm_dreg_req_i         (dm_dreg_req_qlfy       ),
    .pipe2dm_dreg_wr_i          (dm_dreg_wr             ),
    .pipe2dm_dreg_wdata_i       (dm_dreg_wdata          ),
    .dm2pipe_dreg_resp_o        (dm_dreg_resp           ),
    .dm2pipe_dreg_fail_o        (dm_dreg_fail           ),
    .dm2pipe_dreg_rdata_o       (dm_dreg_rdata          )
);
`endif // SCR1_DBG_EN
 
 
`ifdef SCR1_CLKCTRL_EN
//-------------------------------------------------------------------------------
// Global clock gating logic
//-------------------------------------------------------------------------------
scr1_clk_ctrl i_clk_ctrl (
    .clk                            (clk        ),
    .rst_n                          (core_rst_n ),
    .test_mode                      (test_mode  ),
    .test_rst_n                     (test_rst_n ),
 
    // Sleep/wake interface
    .pipe2clkctl_sleep_req_i        (sleep_pipe ),
    .pipe2clkctl_wake_req_i         (wake_pipe  ),
 
    // Clocks
    .clkctl2pipe_clk_alw_on_o       (clk_alw_on ),
    .clkctl2pipe_clk_o              (clk_pipe   ),
    .clkctl2pipe_clk_en_o           (clk_pipe_en),
    .clkctl2pipe_clk_dbgc_o         (clk_dbgc   )
);
`endif // SCR1_CLKCTRL_EN
 
endmodule : scr1_core_top

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [scr1_core_top.sv] - Blame information for rev 21

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details`
2			`/// @file`
3			`/// @brief SCR1 core top`
4			`///`
5
6			`include "scr1_arch_description.svh"
7			`include "scr1_arch_types.svh"
8			`include "scr1_memif.svh"
9
10			`ifdef SCR1_DBG_EN
11			`include "scr1_tapc.svh"
12			`include "scr1_dm.svh"
13			`include "scr1_hdu.svh"
14			`endif // SCR1_DBG_EN
15
16			`ifdef SCR1_IPIC_EN
17			`include "scr1_ipic.svh"
18			`endif // SCR1_IPIC_EN
19
20			`module scr1_core_top (`
21			`// Common`
22			`input logic pwrup_rst_n, // Power-Up reset`
23			`input logic rst_n, // Regular reset`
24			`input logic cpu_rst_n, // CPU reset`
25			`input logic test_mode, // DFT Test Mode`
26			`input logic test_rst_n, // DFT Test Reset`
27			`input logic clk, // Core clock`
28			`output logic core_rst_n_o, // Core reset`
29			`output logic core_rdc_qlfy_o, // Core RDC qualifier`
30			`ifdef SCR1_DBG_EN
31			`output logic sys_rst_n_o, // System reset`
32			`output logic sys_rdc_qlfy_o, // System RDC qualifier`
33			`endif // SCR1_DBG_EN
34
35			`// Fuses`
36			input logic [`SCR1_XLEN-1:0] core_fuse_mhartid_i, // Fuse MHARTID value
37			`ifdef SCR1_DBG_EN
38			`input logic [31:0] tapc_fuse_idcode_i, // Fuse IDCODE value`
39			`endif // SCR1_DBG_EN
40
41			`// IRQ`
42			`ifdef SCR1_IPIC_EN
43			`input logic [SCR1_IRQ_LINES_NUM-1:0] core_irq_lines_i, // External interrupt request lines`
44			`else
45			`input logic core_irq_ext_i, // External interrupt request`
46			`endif // SCR1_IPIC_EN
47			`input logic core_irq_soft_i, // Software generated interrupt request`
48			`input logic core_irq_mtimer_i, // Machine timer interrupt request`
49
50			`// Memory-mapped external timer`
51			`input logic [63:0] core_mtimer_val_i, // Machine timer value`
52
53			`ifdef SCR1_DBG_EN
54			`// Debug Interface`
55			`input logic tapc_trst_n, // Test Reset (TRSTn)`
56			`input logic tapc_tck, // Test Clock (TCK)`
57			`input logic tapc_tms, // Test Mode Select (TMS)`
58			`input logic tapc_tdi, // Test Data Input (TDI)`
59			`output logic tapc_tdo, // Test Data Output (TDO)`
60			`output logic tapc_tdo_en, // TDO Enable, signal for TDO buffer control`
61			`endif // SCR1_DBG_EN
62
63			`// Instruction Memory Interface`
64			`input logic imem2core_req_ack_i, // IMEM request acknowledge`
65			`output logic core2imem_req_o, // IMEM request`
66	21	dinesha	`output logic core2imem_cmd_o, // IMEM command`
67	11	dinesha	output logic [`SCR1_IMEM_AWIDTH-1:0] core2imem_addr_o, // IMEM address
68			input logic [`SCR1_IMEM_DWIDTH-1:0] imem2core_rdata_i, // IMEM read data
69	21	dinesha	`input logic [1:0] imem2core_resp_i, // IMEM response`
70	11	dinesha
71			`// Data Memory Interface`
72			`input logic dmem2core_req_ack_i, // DMEM request acknowledge`
73			`output logic core2dmem_req_o, // DMEM request`
74	21	dinesha	`output logic core2dmem_cmd_o, // DMEM command`
75			`output logic[1:0] core2dmem_width_o, // DMEM data width`
76	11	dinesha	output logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o, // DMEM address
77			output logic [`SCR1_DMEM_DWIDTH-1:0] core2dmem_wdata_o, // DMEM write data
78			input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2core_rdata_i, // DMEM read data
79	21	dinesha	`input logic [1:0] dmem2core_resp_i // DMEM response`
80	11	dinesha	`);`
81
82			`//-------------------------------------------------------------------------------`
83			`// Local parameters`
84			`//-------------------------------------------------------------------------------`
85			`localparam int unsigned SCR1_CORE_TOP_RST_SYNC_STAGES_NUM = 2;`
86
87			`//-------------------------------------------------------------------------------`
88			`// Local signals declaration`
89			`//-------------------------------------------------------------------------------`
90
91			`// Reset Logic`
92			`ifdef SCR1_DBG_EN
93			`else // SCR1_DBG_EN
94			`logic core_rst_n_in_sync;`
95			`logic core_rst_n_qlfy;`
96			`logic core_rst_n_status;`
97			`endif // SCR1_DBG_EN
98			`logic core_rst_n;`
99			`logic core_rst_n_status_sync;`
100			`logic core_rst_status;`
101			`logic core2hdu_rdc_qlfy;`
102			`logic core2dm_rdc_qlfy;`
103			`logic pwrup_rst_n_sync;`
104			`logic rst_n_sync;`
105			`logic cpu_rst_n_sync;`
106
107			`ifdef SCR1_DBG_EN
108			`// TAPC-DM Interface`
109			`logic tapc_dmi_ch_sel;`
110			`logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc_dmi_ch_id;`
111			`logic tapc_dmi_ch_capture;`
112			`logic tapc_dmi_ch_shift;`
113			`logic tapc_dmi_ch_update;`
114			`logic tapc_dmi_ch_tdi;`
115			`logic tapc_dmi_ch_tdo;`
116			`//`
117			`logic tapc_dmi_ch_sel_tapout;`
118			`logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc_dmi_ch_id_tapout;`
119			`logic tapc_dmi_ch_capture_tapout;`
120			`logic tapc_dmi_ch_shift_tapout;`
121			`logic tapc_dmi_ch_update_tapout;`
122			`logic tapc_dmi_ch_tdi_tapout;`
123			`logic tapc_dmi_ch_tdo_tapin;`
124			`//`
125			`logic dmi_req;`
126			`logic dmi_wr;`
127			`logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0] dmi_addr;`
128			`logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi_wdata;`
129			`logic dmi_resp;`
130			`logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi_rdata;`
131			`// TAPC-SCU Interface`
132			`logic tapc_scu_ch_sel;`
133			`logic tapc_scu_ch_sel_tapout;`
134			`logic tapc_scu_ch_tdo;`
135			`logic tapc_ch_tdo;`
136			`// SCU nets`
137			`logic sys_rst_n;`
138			`logic sys_rst_status;`
139			`logic hdu_rst_n;`
140			`logic hdu2dm_rdc_qlfy;`
141			`logic ndm_rst_n;`
142			`logic dm_rst_n;`
143			`logic hart_rst_n;`
144			`endif // SCR1_DBG_EN
145
146			`ifdef SCR1_DBG_EN
147			`// DM-Pipeline Interface`
148			`// HART Run Control i/f`
149			`logic dm_active;`
150			`logic dm_cmd_req;`
151			`type_scr1_hdu_dbgstates_e dm_cmd;`
152			`logic dm_cmd_resp;`
153			`logic dm_cmd_resp_qlfy;`
154			`logic dm_cmd_rcode;`
155			`logic dm_hart_event;`
156			`logic dm_hart_event_qlfy;`
157			`type_scr1_hdu_hartstatus_s dm_hart_status;`
158			`type_scr1_hdu_hartstatus_s dm_hart_status_qlfy;`
159			`// Program Buffer - HART instruction execution i/f`
160			`logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] dm_pbuf_addr;`
161			`logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] dm_pbuf_addr_qlfy;`
162			`logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm_pbuf_instr;`
163			`// HART Abstract Data regs i/f`
164			`logic dm_dreg_req;`
165			`logic dm_dreg_req_qlfy;`
166			`logic dm_dreg_wr;`
167			`logic [SCR1_HDU_DATA_REG_WIDTH-1:0] dm_dreg_wdata;`
168			`logic dm_dreg_resp;`
169			`logic dm_dreg_fail;`
170			`logic [SCR1_HDU_DATA_REG_WIDTH-1:0] dm_dreg_rdata;`
171
172			logic [`SCR1_XLEN-1 : 0] dm_pc_sample;
173			logic [`SCR1_XLEN-1 : 0] dm_pc_sample_qlfy;
174			`endif // SCR1_DBG_EN
175
176			`ifdef SCR1_CLKCTRL_EN
177			`// Global clock gating logic`
178			`logic sleep_pipe;`
179			`logic wake_pipe;`
180			`logic clk_pipe;`
181			`logic clk_pipe_en;`
182			`logic clk_dbgc;`
183			`logic clk_alw_on;`
184			`endif // SCR1_CLKCTRL_EN
185
186
187			`//-------------------------------------------------------------------------------`
188			`// Reset Logic`
189			`//-------------------------------------------------------------------------------`
190			`ifdef SCR1_DBG_EN
191			`scr1_scu i_scu (`
192			`// Global signals`
193			`.pwrup_rst_n (pwrup_rst_n ),`
194			`.rst_n (rst_n ),`
195			`.cpu_rst_n (cpu_rst_n ),`
196			`.test_mode (test_mode ),`
197			`.test_rst_n (test_rst_n ),`
198			`.clk (clk ),`
199
200			`// TAPC scan-chains`
201			`.tapcsync2scu_ch_sel_i (tapc_scu_ch_sel ),`
202			`.tapcsync2scu_ch_id_i ('0 ),`
203			`.tapcsync2scu_ch_capture_i (tapc_dmi_ch_capture),`
204			`.tapcsync2scu_ch_shift_i (tapc_dmi_ch_shift ),`
205			`.tapcsync2scu_ch_update_i (tapc_dmi_ch_update ),`
206			`.tapcsync2scu_ch_tdi_i (tapc_dmi_ch_tdi ),`
207			`.scu2tapcsync_ch_tdo_o (tapc_scu_ch_tdo ),`
208
209			`// Input sync resets:`
210			`.ndm_rst_n_i (ndm_rst_n ),`
211			`.hart_rst_n_i (hart_rst_n ),`
212
213			`// Generated resets`
214			`.sys_rst_n_o (sys_rst_n ),`
215			`.core_rst_n_o (core_rst_n ),`
216			`.dm_rst_n_o (dm_rst_n ),`
217			`.hdu_rst_n_o (hdu_rst_n ),`
218
219			`// Resets statuses`
220			`.sys_rst_status_o (sys_rst_status ),`
221			`.core_rst_status_o (core_rst_status ),`
222
223			`// Reset Domain Crossing (RDC) qualifiers`
224			`.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),`
225			`.core_rdc_qlfy_o (core_rdc_qlfy_o ),`
226			`.core2hdu_rdc_qlfy_o (core2hdu_rdc_qlfy ),`
227			`.core2dm_rdc_qlfy_o (core2dm_rdc_qlfy ),`
228			`.hdu2dm_rdc_qlfy_o (hdu2dm_rdc_qlfy )`
229			`);`
230
231			`assign sys_rst_n_o = sys_rst_n;`
232
233			`// Reset inputs are assumed synchronous`
234			`assign pwrup_rst_n_sync = pwrup_rst_n;`
235
236			`else // SCR1_DBG_EN
237
238			`// Reset inputs are assumed synchronous`
239			`assign pwrup_rst_n_sync = pwrup_rst_n;`
240			`assign rst_n_sync = rst_n;`
241			`assign cpu_rst_n_sync = cpu_rst_n;`
242			`assign core_rst_n_in_sync = rst_n_sync & cpu_rst_n_sync;`
243
244			`// Core Reset: core_rst_n`
245			`scr1_reset_qlfy_adapter_cell_sync i_core_rstn_qlfy_adapter_cell_sync (`
246			`.rst_n (pwrup_rst_n_sync ),`
247			`.clk (clk ),`
248			`.test_rst_n (test_rst_n ),`
249			`.test_mode (test_mode ),`
250			`.reset_n_in_sync (core_rst_n_in_sync),`
251			`.reset_n_out_qlfy (core_rst_n_qlfy ),`
252			`.reset_n_out (core_rst_n ),`
253			`.reset_n_status (core_rst_n_status )`
254			`);`
255
256			`scr1_data_sync_cell #(`
257			`.STAGES_AMOUNT (SCR1_CORE_TOP_RST_SYNC_STAGES_NUM)`
258			`) i_core_rstn_status_sync (`
259			`.rst_n (pwrup_rst_n_sync ),`
260			`.clk (clk ),`
261			`.data_in (core_rst_n_status ),`
262			`.data_out (core_rst_n_status_sync)`
263			`);`
264
265			`assign core_rst_status = ~core_rst_n_status_sync;`
266			`assign core_rdc_qlfy_o = core_rst_n_qlfy;`
267
268			`endif // SCR1_DBG_EN
269			`assign core_rst_n_o = core_rst_n;`
270
271			`//-------------------------------------------------------------------------------`
272			`// SCR1 pipeline`
273			`//-------------------------------------------------------------------------------`
274			`scr1_pipe_top i_pipe_top (`
275			`// Control`
276			`.pipe_rst_n (core_rst_n ),`
277			`ifdef SCR1_DBG_EN
278			`.pipe2hdu_rdc_qlfy_i (core2hdu_rdc_qlfy ),`
279			`.dbg_rst_n (hdu_rst_n ),`
280			`endif // SCR1_DBG_EN
281			`ifndef SCR1_CLKCTRL_EN
282			`.clk (clk ),`
283			`else // SCR1_CLKCTRL_EN
284			`.clk (clk_pipe ),`
285			`.pipe2clkctl_sleep_req_o (sleep_pipe ),`
286			`.pipe2clkctl_wake_req_o (wake_pipe ),`
287			`.clkctl2pipe_clk_alw_on_i (clk_alw_on ),`
288			`.clkctl2pipe_clk_dbgc_i (clk_dbgc ),`
289			`.clkctl2pipe_clk_en_i (clk_pipe_en ),`
290			`endif // SCR1_CLKCTRL_EN
291
292			`// Instruction memory interface`
293			`.pipe2imem_req_o (core2imem_req_o ),`
294			`.pipe2imem_cmd_o (core2imem_cmd_o ),`
295			`.pipe2imem_addr_o (core2imem_addr_o ),`
296			`.imem2pipe_req_ack_i (imem2core_req_ack_i ),`
297			`.imem2pipe_rdata_i (imem2core_rdata_i ),`
298			`.imem2pipe_resp_i (imem2core_resp_i ),`
299
300			`// Data memory interface`
301			`.pipe2dmem_req_o (core2dmem_req_o ),`
302			`.pipe2dmem_cmd_o (core2dmem_cmd_o ),`
303			`.pipe2dmem_width_o (core2dmem_width_o ),`
304			`.pipe2dmem_addr_o (core2dmem_addr_o ),`
305			`.pipe2dmem_wdata_o (core2dmem_wdata_o ),`
306			`.dmem2pipe_req_ack_i (dmem2core_req_ack_i ),`
307			`.dmem2pipe_rdata_i (dmem2core_rdata_i ),`
308			`.dmem2pipe_resp_i (dmem2core_resp_i ),`
309
310			`ifdef SCR1_DBG_EN
311			`// Debug interface:`
312			`.dbg_en (1'b1 ),`
313			`// Debug interface:`
314			`// DM <-> Pipeline: HART Run Control i/f`
315			`.dm2pipe_active_i (dm_active ),`
316			`.dm2pipe_cmd_req_i (dm_cmd_req ),`
317			`.dm2pipe_cmd_i (dm_cmd ),`
318			`.pipe2dm_cmd_resp_o (dm_cmd_resp ),`
319			`.pipe2dm_cmd_rcode_o (dm_cmd_rcode ),`
320			`.pipe2dm_hart_event_o (dm_hart_event ),`
321			`.pipe2dm_hart_status_o (dm_hart_status ),`
322
323			`// DM <-> Pipeline: Program Buffer - HART instruction execution i/f`
324			`.pipe2dm_pbuf_addr_o (dm_pbuf_addr ),`
325			`.dm2pipe_pbuf_instr_i (dm_pbuf_instr ),`
326
327			`// DM <-> Pipeline: HART Abstract Data regs i/f`
328			`.pipe2dm_dreg_req_o (dm_dreg_req ),`
329			`.pipe2dm_dreg_wr_o (dm_dreg_wr ),`
330			`.pipe2dm_dreg_wdata_o (dm_dreg_wdata ),`
331			`.dm2pipe_dreg_resp_i (dm_dreg_resp ),`
332			`.dm2pipe_dreg_fail_i (dm_dreg_fail ),`
333			`.dm2pipe_dreg_rdata_i (dm_dreg_rdata ),`
334
335			`// DM <-> Pipeline: PC i/f`
336			`.pipe2dm_pc_sample_o (dm_pc_sample ),`
337			`endif // SCR1_DBG_EN
338
339			`// IRQ`
340			`ifdef SCR1_IPIC_EN
341			`.soc2pipe_irq_lines_i (core_irq_lines_i ),`
342			`else // SCR1_IPIC_EN
343			`.soc2pipe_irq_ext_i (core_irq_ext_i ),`
344			`endif // SCR1_IPIC_EN
345			`.soc2pipe_irq_soft_i (core_irq_soft_i ),`
346			`.soc2pipe_irq_mtimer_i (core_irq_mtimer_i ),`
347
348			`// Memory-mapped external timer`
349			`.soc2pipe_mtimer_val_i (core_mtimer_val_i ),`
350
351			`// Fuse`
352			`.soc2pipe_fuse_mhartid_i (core_fuse_mhartid_i )`
353			`);`
354
355
356			`ifdef SCR1_DBG_EN
357			`//-------------------------------------------------------------------------------`
358			`// TAP Controller (TAPC)`
359			`//-------------------------------------------------------------------------------`
360			`scr1_tapc i_tapc (`
361			`// JTAG signals`
362			`.tapc_trst_n (tapc_trst_n ),`
363			`.tapc_tck (tapc_tck ),`
364			`.tapc_tms (tapc_tms ),`
365			`.tapc_tdi (tapc_tdi ),`
366			`.tapc_tdo (tapc_tdo ),`
367			`.tapc_tdo_en (tapc_tdo_en ),`
368
369			`// Fuses`
370			`.soc2tapc_fuse_idcode_i (tapc_fuse_idcode_i ),`
371
372			`// DMI/SCU scan-chains`
373			`.tapc2tapcsync_scu_ch_sel_o (tapc_scu_ch_sel_tapout ),`
374			`.tapc2tapcsync_dmi_ch_sel_o (tapc_dmi_ch_sel_tapout ),`
375			`.tapc2tapcsync_ch_id_o (tapc_dmi_ch_id_tapout ),`
376			`.tapc2tapcsync_ch_capture_o (tapc_dmi_ch_capture_tapout),`
377			`.tapc2tapcsync_ch_shift_o (tapc_dmi_ch_shift_tapout ),`
378			`.tapc2tapcsync_ch_update_o (tapc_dmi_ch_update_tapout ),`
379			`.tapc2tapcsync_ch_tdi_o (tapc_dmi_ch_tdi_tapout ),`
380			`.tapcsync2tapc_ch_tdo_i (tapc_dmi_ch_tdo_tapin )`
381			`);`
382
383			`scr1_tapc_synchronizer i_tapc_synchronizer (`
384			`// System common signals`
385			`.pwrup_rst_n (pwrup_rst_n_sync ),`
386			`.dm_rst_n (dm_rst_n ),`
387			`.clk (clk ),`
388
389			`// JTAG common signals`
390			`.tapc_trst_n (tapc_trst_n ),`
391			`.tapc_tck (tapc_tck ),`
392
393			`// DMI/SCU scan-chains`
394			`.tapc2tapcsync_scu_ch_sel_i (tapc_scu_ch_sel_tapout ),`
395			`.tapcsync2scu_ch_sel_o (tapc_scu_ch_sel ),`
396			`.tapc2tapcsync_dmi_ch_sel_i (tapc_dmi_ch_sel_tapout ),`
397			`.tapcsync2dmi_ch_sel_o (tapc_dmi_ch_sel ),`
398
399			`.tapc2tapcsync_ch_id_i (tapc_dmi_ch_id_tapout ),`
400			`.tapcsync2core_ch_id_o (tapc_dmi_ch_id ),`
401			`.tapc2tapcsync_ch_capture_i (tapc_dmi_ch_capture_tapout),`
402			`.tapcsync2core_ch_capture_o (tapc_dmi_ch_capture ),`
403			`.tapc2tapcsync_ch_shift_i (tapc_dmi_ch_shift_tapout ),`
404			`.tapcsync2core_ch_shift_o (tapc_dmi_ch_shift ),`
405			`.tapc2tapcsync_ch_update_i (tapc_dmi_ch_update_tapout ),`
406			`.tapcsync2core_ch_update_o (tapc_dmi_ch_update ),`
407			`.tapc2tapcsync_ch_tdi_i (tapc_dmi_ch_tdi_tapout ),`
408			`.tapcsync2core_ch_tdi_o (tapc_dmi_ch_tdi ),`
409			`.tapc2tapcsync_ch_tdo_i (tapc_dmi_ch_tdo_tapin ),`
410			`.tapcsync2core_ch_tdo_o (tapc_ch_tdo )`
411			`);`
412			`assign tapc_ch_tdo = (tapc_scu_ch_tdo & tapc_scu_ch_sel)`
413			`\| (tapc_dmi_ch_tdo & tapc_dmi_ch_sel);`
414
415			`scr1_dmi i_dmi (`
416			`.rst_n (dm_rst_n ),`
417			`.clk (clk ),`
418
419			`// TAP scan-chains`
420			`.tapcsync2dmi_ch_sel_i (tapc_dmi_ch_sel ),`
421			`.tapcsync2dmi_ch_id_i (tapc_dmi_ch_id ),`
422			`.tapcsync2dmi_ch_capture_i (tapc_dmi_ch_capture),`
423			`.tapcsync2dmi_ch_shift_i (tapc_dmi_ch_shift ),`
424			`.tapcsync2dmi_ch_update_i (tapc_dmi_ch_update ),`
425			`.tapcsync2dmi_ch_tdi_i (tapc_dmi_ch_tdi ),`
426			`.dmi2tapcsync_ch_tdo_o (tapc_dmi_ch_tdo ),`
427
428			`// DMI`
429			`.dm2dmi_resp_i (dmi_resp ),`
430			`.dm2dmi_rdata_i (dmi_rdata ),`
431			`.dmi2dm_req_o (dmi_req ),`
432			`.dmi2dm_wr_o (dmi_wr ),`
433			`.dmi2dm_addr_o (dmi_addr ),`
434			`.dmi2dm_wdata_o (dmi_wdata )`
435			`);`
436
437			`endif // SCR1_DBG_EN
438
439
440			`ifdef SCR1_DBG_EN
441
442			`//-------------------------------------------------------------------------------`
443			`// Debug Module (DM)`
444			`//-------------------------------------------------------------------------------`
445			`assign dm_cmd_resp_qlfy = dm_cmd_resp & {$bits(dm_cmd_resp){hdu2dm_rdc_qlfy}};`
446			`assign dm_hart_event_qlfy = dm_hart_event & {$bits(dm_hart_event){hdu2dm_rdc_qlfy}};`
447			`assign dm_hart_status_qlfy.dbg_state = hdu2dm_rdc_qlfy ? dm_hart_status.dbg_state`
448			`: SCR1_HDU_DBGSTATE_RESET;`
449			`assign dm_hart_status_qlfy.except = dm_hart_status.except;`
450			`assign dm_hart_status_qlfy.ebreak = dm_hart_status.ebreak;`
451			`assign dm_pbuf_addr_qlfy = dm_pbuf_addr & {$bits(dm_pbuf_addr){hdu2dm_rdc_qlfy}};`
452			`assign dm_dreg_req_qlfy = dm_dreg_req & {$bits(dm_dreg_req){hdu2dm_rdc_qlfy}};`
453			`assign dm_pc_sample_qlfy = dm_pc_sample & {$bits(dm_pc_sample){core2dm_rdc_qlfy}};`
454
455			`scr1_dm i_dm (`
456			`// Common signals`
457			`.rst_n (dm_rst_n ),`
458			`.clk (clk ),`
459
460			`// DM internal interface`
461			`.dmi2dm_req_i (dmi_req ),`
462			`.dmi2dm_wr_i (dmi_wr ),`
463			`.dmi2dm_addr_i (dmi_addr ),`
464			`.dmi2dm_wdata_i (dmi_wdata ),`
465			`.dm2dmi_resp_o (dmi_resp ),`
466			`.dm2dmi_rdata_o (dmi_rdata ),`
467
468			`// DM <-> Pipeline: HART Run Control i/f`
469			`.ndm_rst_n_o (ndm_rst_n ),`
470			`.hart_rst_n_o (hart_rst_n ),`
471			`.dm2pipe_active_o (dm_active ),`
472			`.dm2pipe_cmd_req_o (dm_cmd_req ),`
473			`.dm2pipe_cmd_o (dm_cmd ),`
474			`.pipe2dm_cmd_resp_i (dm_cmd_resp_qlfy ),`
475			`.pipe2dm_cmd_rcode_i (dm_cmd_rcode ),`
476			`.pipe2dm_hart_event_i (dm_hart_event_qlfy ),`
477			`.pipe2dm_hart_status_i (dm_hart_status_qlfy ),`
478
479			`.soc2dm_fuse_mhartid_i (core_fuse_mhartid_i ),`
480			`.pipe2dm_pc_sample_i (dm_pc_sample_qlfy ),`
481
482			`// DM <-> Pipeline: HART Abstract Command / Program Buffer i/f`
483			`.pipe2dm_pbuf_addr_i (dm_pbuf_addr_qlfy ),`
484			`.dm2pipe_pbuf_instr_o (dm_pbuf_instr ),`
485
486			`// DM <-> Pipeline: HART Abstract Data regs i/f`
487			`.pipe2dm_dreg_req_i (dm_dreg_req_qlfy ),`
488			`.pipe2dm_dreg_wr_i (dm_dreg_wr ),`
489			`.pipe2dm_dreg_wdata_i (dm_dreg_wdata ),`
490			`.dm2pipe_dreg_resp_o (dm_dreg_resp ),`
491			`.dm2pipe_dreg_fail_o (dm_dreg_fail ),`
492			`.dm2pipe_dreg_rdata_o (dm_dreg_rdata )`
493			`);`
494			`endif // SCR1_DBG_EN
495
496
497			`ifdef SCR1_CLKCTRL_EN
498			`//-------------------------------------------------------------------------------`
499			`// Global clock gating logic`
500			`//-------------------------------------------------------------------------------`
501			`scr1_clk_ctrl i_clk_ctrl (`
502			`.clk (clk ),`
503			`.rst_n (core_rst_n ),`
504			`.test_mode (test_mode ),`
505			`.test_rst_n (test_rst_n ),`
506
507			`// Sleep/wake interface`
508			`.pipe2clkctl_sleep_req_i (sleep_pipe ),`
509			`.pipe2clkctl_wake_req_i (wake_pipe ),`
510
511			`// Clocks`
512			`.clkctl2pipe_clk_alw_on_o (clk_alw_on ),`
513			`.clkctl2pipe_clk_o (clk_pipe ),`
514			`.clkctl2pipe_clk_en_o (clk_pipe_en),`
515			`.clkctl2pipe_clk_dbgc_o (clk_dbgc )`
516			`);`
517			`endif // SCR1_CLKCTRL_EN
518
519			`endmodule : scr1_core_top`