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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief Debug Module Interface (DMI)
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///
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//------------------------------------------------------------------------------
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//
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// Functionality:
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// - Provides TAPC with access to Debug Module (DM) and DTMCS
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//
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// Structure:
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// - DMI <-> TAP interface
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// - DMI <-> DM interface
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//
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//------------------------------------------------------------------------------
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`include "scr1_arch_description.svh"
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`ifdef SCR1_DBG_EN
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`include "scr1_dm.svh"
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module scr1_dmi (
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// System
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input logic rst_n, // DMI unit reset
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input logic clk, // DMI unit clock
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// TAP interface
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input logic tapcsync2dmi_ch_sel_i, // Debug Transport Module Chain Select
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input logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapcsync2dmi_ch_id_i, // Debug Transport Module Chain ID
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input logic tapcsync2dmi_ch_capture_i, // Debug Transport Module Chain Capture
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input logic tapcsync2dmi_ch_shift_i, // Debug Transport Module Chain Shift
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input logic tapcsync2dmi_ch_update_i, // Debug Transport Module Chain Update
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input logic tapcsync2dmi_ch_tdi_i, // Debug Transport Module Chain TDI
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output logic dmi2tapcsync_ch_tdo_o, // Debug Transport Module Chain TDO
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// DM interface
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input logic dm2dmi_resp_i, // DMI response
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input logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dm2dmi_rdata_i, // DMI read data
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output logic dmi2dm_req_o, // DMI request
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output logic dmi2dm_wr_o, // DMI write
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output logic [SCR1_DBG_DMI_ADDR_WIDTH-1:0] dmi2dm_addr_o, // DMI address
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output logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dmi2dm_wdata_o // DMI write data
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);
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//------------------------------------------------------------------------------
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// Local parameters declaration
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//------------------------------------------------------------------------------
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// Debug Transport Module Status parameters
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//------------------------------------------------------------------------------
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localparam DTMCS_RESERVEDB_HI = 5'd31;
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localparam DTMCS_RESERVEDB_LO = 5'd18;
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localparam DTMCS_DMIHARDRESET = 5'd17;
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localparam DTMCS_DMIRESET = 5'd16;
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localparam DTMCS_RESERVEDA = 5'd15;
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localparam DTMCS_IDLE_HI = 5'd14;
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localparam DTMCS_IDLE_LO = 5'd12;
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localparam DTMCS_DMISTAT_HI = 5'd11;
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localparam DTMCS_DMISTAT_LO = 5'd10;
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localparam DTMCS_ABITS_HI = 5'd9;
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localparam DTMCS_ABITS_LO = 5'd4;
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localparam DTMCS_VERSION_HI = 5'd3;
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localparam DTMCS_VERSION_LO = 5'd0;
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// Debug Module Interface parameters
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//------------------------------------------------------------------------------
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localparam DMI_OP_LO = 5'd0;
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localparam DMI_OP_HI = DMI_OP_LO + SCR1_DBG_DMI_OP_WIDTH - 1;
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localparam DMI_DATA_LO = DMI_OP_HI + 1;
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localparam DMI_DATA_HI = DMI_DATA_LO + SCR1_DBG_DMI_DATA_WIDTH - 1;
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localparam DMI_ADDR_LO = DMI_DATA_HI + 1;
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localparam DMI_ADDR_HI = DMI_ADDR_LO + SCR1_DBG_DMI_ADDR_WIDTH - 1;
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//------------------------------------------------------------------------------
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// Local signals declaration
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//------------------------------------------------------------------------------
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// TAP data register
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logic tap_dr_upd;
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logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_ff;
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logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_shift;
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logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_rdata;
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logic [SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:0] tap_dr_next;
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// DM read data register
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logic dm_rdata_upd;
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logic [SCR1_DBG_DMI_DATA_WIDTH-1:0] dm_rdata_ff;
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logic tapc_dmi_access_req;
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logic tapc_dtmcs_sel;
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//------------------------------------------------------------------------------
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// DMI <-> TAP interface
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//------------------------------------------------------------------------------
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// TAPC read data multiplexer
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//------------------------------------------------------------------------------
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assign tapc_dtmcs_sel = (tapcsync2dmi_ch_id_i == 1'd1);
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// DMI operation is always successful in the current implementation
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always_comb begin
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tap_dr_rdata = '0;
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if(tapc_dtmcs_sel) begin
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tap_dr_rdata[DTMCS_RESERVEDB_HI:DTMCS_RESERVEDB_LO] = 'b0;
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tap_dr_rdata[DTMCS_DMIHARDRESET] = 'b0;
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tap_dr_rdata[DTMCS_DMIRESET] = 'b0;
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tap_dr_rdata[DTMCS_RESERVEDA] = 'b0;
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tap_dr_rdata[DTMCS_IDLE_HI:DTMCS_IDLE_LO] = 'b0;
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tap_dr_rdata[DTMCS_DMISTAT_HI:DTMCS_DMISTAT_LO] = 'b0;
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tap_dr_rdata[DTMCS_ABITS_HI :DTMCS_ABITS_LO] = SCR1_DBG_DMI_ADDR_WIDTH;
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tap_dr_rdata[DTMCS_VERSION_LO] = 1'b1;
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end else begin
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tap_dr_rdata[DMI_ADDR_HI:DMI_ADDR_LO] = 'b0;
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tap_dr_rdata[DMI_DATA_HI:DMI_DATA_LO] = dm_rdata_ff;
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tap_dr_rdata[DMI_OP_HI :DMI_OP_LO] = 'b0;
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end
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end
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assign tap_dr_shift = tapc_dtmcs_sel
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? {9'b0, tapcsync2dmi_ch_tdi_i, tap_dr_ff[SCR1_DBG_DMI_DR_DTMCS_WIDTH-1:1]}
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: {tapcsync2dmi_ch_tdi_i, tap_dr_ff[SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH-1:1]};
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// TAP data register
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//------------------------------------------------------------------------------
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assign tap_dr_upd = tapcsync2dmi_ch_capture_i | tapcsync2dmi_ch_shift_i;
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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tap_dr_ff <= '0;
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end else if(tap_dr_upd) begin
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tap_dr_ff <= tap_dr_next;
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end
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end
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assign tap_dr_next = tapcsync2dmi_ch_capture_i ? tap_dr_rdata
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: tapcsync2dmi_ch_shift_i ? tap_dr_shift
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: tap_dr_ff;
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assign dmi2tapcsync_ch_tdo_o = tap_dr_ff[0];
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//------------------------------------------------------------------------------
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// DMI <-> DM interface
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//------------------------------------------------------------------------------
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assign tapc_dmi_access_req = tapcsync2dmi_ch_update_i & tapcsync2dmi_ch_sel_i
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& (tapcsync2dmi_ch_id_i == 2'd2);
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always_comb begin
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dmi2dm_req_o = 1'b0;
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dmi2dm_wr_o = 1'b0;
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dmi2dm_addr_o = 1'b0;
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dmi2dm_wdata_o = 1'b0;
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if(tapc_dmi_access_req) begin
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dmi2dm_req_o = tap_dr_ff[DMI_OP_HI :DMI_OP_LO] != 2'b00;
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dmi2dm_wr_o = tap_dr_ff[DMI_OP_HI :DMI_OP_LO] == 2'b10;
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dmi2dm_addr_o = tap_dr_ff[DMI_ADDR_HI:DMI_ADDR_LO];
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dmi2dm_wdata_o = tap_dr_ff[DMI_DATA_HI:DMI_DATA_LO];
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end
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end
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// DM read data register
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//------------------------------------------------------------------------------
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assign dm_rdata_upd = dmi2dm_req_o & dm2dmi_resp_i & ~dmi2dm_wr_o;
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always_ff @(posedge clk, negedge rst_n) begin
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if (~rst_n) begin
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dm_rdata_ff <= '0;
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end else if (dm_rdata_upd) begin
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dm_rdata_ff <= dm2dmi_rdata_i;
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end
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end
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endmodule : scr1_dmi
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`endif // SCR1_DBG_EN
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