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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
/// @file 
/// @brief System Control Unit (SCU)
///
 
//------------------------------------------------------------------------------
 //
 // Functionality:
 // - Generates System, Core, HDU and DM resets and their qualifier signals
 // - Provides debugger with software System and Core resets generation functionality
 // - Allows to set the behavior of DM and HDU resets
 // - Shows resets Statuses and Sticky Statuses
 
 // Structure:
 // - TAPC scan-chain interface
 // - SCU CSRs write/read interface
 // - SCU CSRS:
 //   - CONTROL register
 //   - MODE register
 //   - STATUS register
 //   - STICKY_STATUS register
 // - Reset logic
 //   - System Reset
 //   - Core Reset
 //   - DM Reset
 //   - HDU Reset
//------------------------------------------------------------------------------
 
`include "scr1_arch_description.svh"
`include "scr1_scu.svh"
 
`ifdef SCR1_DBG_EN
 
module scr1_scu (
    // Global signals
    input  logic        pwrup_rst_n,                  // Power-Up Reset
    input  logic        rst_n,                        // Regular Reset
    input  logic        cpu_rst_n,                    // CPU Reset
    input  logic        test_mode,                    // DFT Test Mode
    input  logic        test_rst_n,                   // DFT Test Reset
    input  logic        clk,                          // SCU clock
 
    // TAPC scan-chains
    input  logic        tapcsync2scu_ch_sel_i,        // TAPC Chain Select
    input  logic        tapcsync2scu_ch_id_i,         // TAPC Chain ID
    input  logic        tapcsync2scu_ch_capture_i,    // TAPC Chain Capture
    input  logic        tapcsync2scu_ch_shift_i,      // TAPC Chain Shift
    input  logic        tapcsync2scu_ch_update_i,     // TAPC Chain Update
    input  logic        tapcsync2scu_ch_tdi_i,        // TAPC Chain TDI
    output logic        scu2tapcsync_ch_tdo_o,        // TAPC Chain TDO
 
    // Input sync resets:
    input  logic        ndm_rst_n_i,                  // Non-DM Reset input from DM
    input  logic        hart_rst_n_i,                 // HART Reset from DM
 
    // Generated resets
    output logic        sys_rst_n_o,                  // System/Cluster Reset
    output logic        core_rst_n_o,                 // Core Reset
    output logic        dm_rst_n_o,                   // Debug Module Reset
    output logic        hdu_rst_n_o,                  // HART Debug Unit Reset
 
    // Resets statuses
    output logic        sys_rst_status_o,             // System Reset Status (sync'ed to POR reset domain)
    output logic        core_rst_status_o,            // Core Reset Status (sync'ed to POR reset domain)
 
    // Reset Domain Crossing (RDC) qualifiers
    output logic        sys_rdc_qlfy_o,               // System/Cluster-to-ExternalSOC Reset Domain Crossing Qualifier
    output logic        core_rdc_qlfy_o,              // Core-to-ExternalSOC Reset Domain Crossing Qualifier
    output logic        core2hdu_rdc_qlfy_o,          // Core-to-HDU Reset Domain Crossing Qualifier
    output logic        core2dm_rdc_qlfy_o,           // Core-to-DM Reset Domain Crossing Qualifier
    output logic        hdu2dm_rdc_qlfy_o             // HDU-to-DM Reset Domain Crossing Qualifier
);
 
//------------------------------------------------------------------------------
// Local Parameters
//======================================================================================================================
localparam int unsigned SCR1_SCU_RST_SYNC_STAGES_NUM        = 2;
 
//------------------------------------------------------------------------------
// Local Signals
//------------------------------------------------------------------------------
 
// SCU CSR write/read i/f
//------------------------------------------------------------------------------
 
// TAPC scan-chain control logic
logic                                       scu_csr_req;
logic                                       tapc_dr_cap_req;
logic                                       tapc_dr_shft_req;
logic                                       tapc_dr_upd_req;
 
// TAPC shift register signals
logic                                       tapc_shift_upd;
type_scr1_scu_sysctrl_dr_s                  tapc_shift_ff;
type_scr1_scu_sysctrl_dr_s                  tapc_shift_next;
 
// TAPC shadow register signals
type_scr1_scu_sysctrl_dr_s                  tapc_shadow_ff;
 
// SCU CSR write/read i/f
//------------------------------------------------------------------------------
 
logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0]  scu_csr_wdata;
logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0]  scu_csr_rdata;
 
// SCU CSRs signals
//------------------------------------------------------------------------------
 
// Control register
type_scr1_scu_sysctrl_control_reg_s         scu_control_ff;
logic                                       scu_control_wr_req;
 
// Mode register
type_scr1_scu_sysctrl_mode_reg_s            scu_mode_ff;
logic                                       scu_mode_wr_req;
 
// Status register
type_scr1_scu_sysctrl_status_reg_s          scu_status_ff;
type_scr1_scu_sysctrl_status_reg_s          scu_status_ff_dly;
type_scr1_scu_sysctrl_status_reg_s          scu_status_ff_posedge;
 
// Sticky Status register
type_scr1_scu_sysctrl_status_reg_s          scu_sticky_sts_ff;
logic                                       scu_sticky_sts_wr_req;
 
// Reset logic signals
//------------------------------------------------------------------------------
 
// Input resets synchronization signals
logic                                       pwrup_rst_n_sync;
logic                                       rst_n_sync;
logic                                       cpu_rst_n_sync;
 
// System Reset signals
logic                                       sys_rst_n_in;
logic                                       sys_rst_n_status;
logic                                       sys_rst_n_status_sync;
logic                                       sys_rst_n_qlfy;
logic                                       sys_reset_n;
 
// Core Reset signals
logic                                       core_rst_n_in_sync;
logic                                       core_rst_n_status;
logic                                       core_rst_n_status_sync;
logic                                       core_rst_n_qlfy;
logic                                       core_reset_n;
 
// HDU Reset signals
logic                                       hdu_rst_n_in_sync;
logic                                       hdu_rst_n_status;
logic                                       hdu_rst_n_status_sync;
logic                                       hdu_rst_n_qlfy;
 
// DM Reset signals
logic                                       dm_rst_n_in;
logic                                       dm_rst_n_status;
 
//------------------------------------------------------------------------------
// TAPC scan-chain i/f
//------------------------------------------------------------------------------
//
 // Consists of the following functional units:
 // - TAPC scan-chain control logic
 // - TAPC shift register
 // - TAPC shadow register
//
 
// TAPC scan-chain control logic
//------------------------------------------------------------------------------
 
assign scu_csr_req      = tapcsync2scu_ch_sel_i & (tapcsync2scu_ch_id_i == '0);
assign tapc_dr_cap_req  = scu_csr_req & tapcsync2scu_ch_capture_i;
assign tapc_dr_shft_req = scu_csr_req & tapcsync2scu_ch_shift_i;
assign tapc_dr_upd_req  = scu_csr_req & tapcsync2scu_ch_update_i;
 
// TAPC shift register
//------------------------------------------------------------------------------
 
assign tapc_shift_upd = tapc_dr_cap_req | tapc_dr_shft_req;
 
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        tapc_shift_ff <= '0;
    end else if (tapc_shift_upd) begin
        tapc_shift_ff <= tapc_shift_next;
    end
end
 
assign tapc_shift_next = tapc_dr_cap_req  ? tapc_shadow_ff
                       : tapc_dr_shft_req ? {tapcsync2scu_ch_tdi_i, tapc_shift_ff[SCR1_SCU_DR_SYSCTRL_WIDTH-1:1]}// cp.5
                                          : tapc_shift_ff;
 
// TAPC shadow register
//------------------------------------------------------------------------------
 
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        tapc_shadow_ff      <= '0;
    end else if (tapc_dr_upd_req) begin
        tapc_shadow_ff.op   <= tapc_shift_ff.op;
        tapc_shadow_ff.addr <= tapc_shift_ff.addr;
        tapc_shadow_ff.data <= scu_csr_wdata;
    end
end
 
assign scu2tapcsync_ch_tdo_o = tapc_shift_ff[0];
 
//------------------------------------------------------------------------------
// SCU CSRs write/read interface
//------------------------------------------------------------------------------
 
// Write interface
//------------------------------------------------------------------------------
 
// Register selection logic
always_comb begin
    scu_control_wr_req    = 1'b0;
    scu_mode_wr_req       = 1'b0;
    scu_sticky_sts_wr_req = 1'b0;
 
    if (tapc_dr_upd_req && (tapc_shift_ff.op != SCR1_SCU_SYSCTRL_OP_READ)) begin
        case (tapc_shift_ff.addr)
            SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_control_wr_req    = 1'b1;
            SCR1_SCU_SYSCTRL_ADDR_MODE   : scu_mode_wr_req       = 1'b1;
            SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_sticky_sts_wr_req = (tapc_shift_ff.op == SCR1_SCU_SYSCTRL_OP_CLRBITS);
            default                      : begin end
        endcase
    end
end
 
// Write data construction
always_comb begin
    scu_csr_wdata = '0;
 
    if (tapc_dr_upd_req) begin
        case (tapc_shift_ff.op)
            SCR1_SCU_SYSCTRL_OP_WRITE  : scu_csr_wdata = tapc_shift_ff.data;
            SCR1_SCU_SYSCTRL_OP_READ   : scu_csr_wdata = scu_csr_rdata;
            SCR1_SCU_SYSCTRL_OP_SETBITS: scu_csr_wdata = scu_csr_rdata |   tapc_shift_ff.data;
            SCR1_SCU_SYSCTRL_OP_CLRBITS: scu_csr_wdata = scu_csr_rdata & (~tapc_shift_ff.data);
            default                    : begin end
        endcase
    end
end
 
// Read interface
//------------------------------------------------------------------------------
 
// Read data multiplexer
always_comb begin
    scu_csr_rdata = '0;
 
    if (tapc_dr_upd_req) begin
        case (tapc_shift_ff.addr)
            SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_csr_rdata = scu_control_ff;
            SCR1_SCU_SYSCTRL_ADDR_MODE   : scu_csr_rdata = scu_mode_ff;
            SCR1_SCU_SYSCTRL_ADDR_STATUS : scu_csr_rdata = scu_status_ff;
            SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_csr_rdata = scu_sticky_sts_ff;
            default                      : scu_csr_rdata = 'x;
        endcase
    end
end
 
//------------------------------------------------------------------------------
// SCU CSRs
//------------------------------------------------------------------------------
//
 // Registers:
 // - CONTROL register
 // - MODE register
 // - STATUS register
 // - STICKY_STATUS register
//
 
// CONTROL register
//------------------------------------------------------------------------------
// Allows debugger to generate System and Core resets
 
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        scu_control_ff <= '0;
    end else if (scu_control_wr_req) begin
        scu_control_ff <= scu_csr_wdata;
    end
end
 
// MODE register
//------------------------------------------------------------------------------
// Sets reset behavior for DM Reset and HDU Reset signals
 
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        scu_mode_ff <= '0;
    end else if (scu_mode_wr_req) begin
        scu_mode_ff <= scu_csr_wdata;
    end
end
 
// STATUS register
//------------------------------------------------------------------------------
// Holds the status of every output reset signal (System, Core, DM and HDU)
 
assign scu_status_ff.sys_reset  = sys_rst_status_o ;
assign scu_status_ff.core_reset = core_rst_status_o;
assign scu_status_ff.dm_reset   = ~dm_rst_n_status;
assign scu_status_ff.hdu_reset  = ~hdu_rst_n_status_sync;
 
// Status Register positive edge detection logic
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        scu_status_ff_dly <= '0;
    end else begin
        scu_status_ff_dly <= scu_status_ff;
    end
end
 
assign scu_status_ff_posedge = scu_status_ff & ~scu_status_ff_dly;
 
// STICKY_STATUS register
//------------------------------------------------------------------------------
// For every output reset signal shows if it was asserted since the last bit clearing
integer i;
always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin
    if (~pwrup_rst_n_sync) begin
        scu_sticky_sts_ff <= '0;
    end else begin
        for (i = 0; i < SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH ; i=i+1) begin // cp.4
            if (scu_status_ff_posedge[i]) begin
                scu_sticky_sts_ff[i] <= 1'b1;
            end else if (scu_sticky_sts_wr_req) begin
                scu_sticky_sts_ff[i] <= scu_csr_wdata[i];
            end
        end
    end
end
 
//------------------------------------------------------------------------------
// Reset logic
//------------------------------------------------------------------------------
//
 // Consists of the following functional units:
 // - System Reset logic
 // - Core Reset logic
 // - Hart Debug Unit Reset logic
 // - Debug Module Reset logic
//
 
// Reset inputs are assumed synchronous
assign pwrup_rst_n_sync = pwrup_rst_n;
assign rst_n_sync       = rst_n;
assign cpu_rst_n_sync   = cpu_rst_n;
 
// Intermediate resets:
assign sys_reset_n  = ~scu_control_ff.sys_reset;
assign core_reset_n = ~scu_control_ff.core_reset;
 
// System/Cluster Reset: sys_rst_n_o
//------------------------------------------------------------------------------
 
scr1_reset_qlfy_adapter_cell_sync   i_sys_rstn_qlfy_adapter_cell_sync (
    .rst_n                          (pwrup_rst_n_sync),
    .clk                            (clk             ),
    .test_rst_n                     (test_rst_n      ),
    .test_mode                      (test_mode       ),
    .reset_n_in_sync                (sys_rst_n_in    ),
    .reset_n_out_qlfy               (sys_rst_n_qlfy  ),
    .reset_n_out                    (sys_rst_n_o     ),
    .reset_n_status                 (sys_rst_n_status)
);
 
assign sys_rst_n_in = sys_reset_n & ndm_rst_n_i & rst_n_sync;
 
scr1_data_sync_cell #(
    .STAGES_AMOUNT       (SCR1_SCU_RST_SYNC_STAGES_NUM)
) i_sys_rstn_status_sync (
    .rst_n               (pwrup_rst_n_sync     ),
    .clk                 (clk                  ),
    .data_in             (sys_rst_n_status     ),
    .data_out            (sys_rst_n_status_sync)
);
 
assign sys_rst_status_o = ~sys_rst_n_status_sync;
 
// System/Cluster-to-ExternalSOC RDC qualifier
assign sys_rdc_qlfy_o = sys_rst_n_qlfy;
 
// Core Reset: core_rst_n_o
//------------------------------------------------------------------------------
 
scr1_reset_qlfy_adapter_cell_sync   i_core_rstn_qlfy_adapter_cell_sync (
    .rst_n                          (pwrup_rst_n_sync  ),
    .clk                            (clk               ),
    .test_rst_n                     (test_rst_n        ),
    .test_mode                      (test_mode         ),
    .reset_n_in_sync                (core_rst_n_in_sync),
    .reset_n_out_qlfy               (core_rst_n_qlfy   ),
    .reset_n_out                    (core_rst_n_o      ),
    .reset_n_status                 (core_rst_n_status )
);
 
assign core_rst_n_in_sync   = sys_rst_n_in & hart_rst_n_i & core_reset_n & cpu_rst_n_sync;
 
scr1_data_sync_cell #(
    .STAGES_AMOUNT        (SCR1_SCU_RST_SYNC_STAGES_NUM)
) i_core_rstn_status_sync (
    .rst_n                (pwrup_rst_n_sync      ),
    .clk                  (clk                   ),
    .data_in              (core_rst_n_status     ),
    .data_out             (core_rst_n_status_sync)
);
 
assign core_rst_status_o = ~core_rst_n_status_sync;
 
// Core Reset RDC Qualifiers:
//  - Core-to-ExternalSOC RDC Qlfy
assign core_rdc_qlfy_o = core_rst_n_qlfy;
//  - Core-to-HDU RDC Qlfy
assign core2hdu_rdc_qlfy_o = core_rst_n_qlfy;
//  - Core-to-DebugModule RDC Qlfy
assign core2dm_rdc_qlfy_o  = core_rst_n_qlfy;
 
// Hart Debug Unit Reset: hdu_rst_n_o
//------------------------------------------------------------------------------
 
scr1_reset_qlfy_adapter_cell_sync   i_hdu_rstn_qlfy_adapter_cell_sync (
    .rst_n                          (pwrup_rst_n_sync ),
    .clk                            (clk              ),
    .test_rst_n                     (test_rst_n       ),
    .test_mode                      (test_mode        ),
    .reset_n_in_sync                (hdu_rst_n_in_sync),
    .reset_n_out_qlfy               (hdu_rst_n_qlfy   ),
    .reset_n_out                    (hdu_rst_n_o      ),
    .reset_n_status                 (hdu_rst_n_status )
);
 
assign hdu_rst_n_in_sync = scu_mode_ff.hdu_rst_bhv | core_rst_n_in_sync;
 
scr1_data_sync_cell #(
    .STAGES_AMOUNT       (SCR1_SCU_RST_SYNC_STAGES_NUM)
) i_hdu_rstn_status_sync (
    .rst_n               (pwrup_rst_n_sync     ),
    .clk                 (clk                  ),
    .data_in             (hdu_rst_n_status     ),
    .data_out            (hdu_rst_n_status_sync)
);
 
// Hart Debug Unit Reset RDC Qualifiers:
//  - HDU-to-DebugModule RDC Qlfy
assign hdu2dm_rdc_qlfy_o = hdu_rst_n_qlfy;
 
// Debug Module Reset: dm_rst_n_o
//------------------------------------------------------------------------------
 
scr1_reset_buf_cell i_dm_rstn_buf_cell (
    .rst_n              (pwrup_rst_n_sync),
    .clk                (clk             ),
    .test_mode          (test_mode       ),
    .test_rst_n         (test_rst_n      ),
    .reset_n_in         (dm_rst_n_in     ),
    .reset_n_out        (dm_rst_n_o      ),
    .reset_n_status     (dm_rst_n_status )
);
 
assign dm_rst_n_in  = ~scu_mode_ff.dm_rst_bhv | sys_reset_n;
 
`ifdef SCR1_TRGT_SIMULATION
//--------------------------------------------------------------------
// Assertions
//--------------------------------------------------------------------
 
`ifndef VERILATOR
// Preventing some assertions to be raised at 0 sim time or in the first cycle
initial begin
$assertoff(0, scr1_scu);
repeat (2) @(posedge clk);
$asserton(0, scr1_scu);
end
`endif // VERILATOR
 
// X checks
SCR1_SVA_SCU_RESETS_XCHECK : assert property (
    @(negedge clk)
    !$isunknown({pwrup_rst_n, rst_n, cpu_rst_n, ndm_rst_n_i, hart_rst_n_i})
) else $error("SCU resets error: unknown values of input resets");
 
`ifndef VERILATOR
// Qualifiers checks
SCR1_SVA_SCU_SYS2SOC_QLFY_CHECK : assert property (
    @(negedge clk) disable iff (~pwrup_rst_n)
    $fell(sys_rst_n_o) |-> $fell($past(sys_rdc_qlfy_o))
) else $error("SCU sys2soc qlfy error: qlfy wasn't raised prior to reset");
 
SCR1_SVA_SCU_CORE2SOC_QLFY_CHECK : assert property (
    @(negedge clk) disable iff (~pwrup_rst_n)
    $fell(core_rst_n_o) |-> $fell($past(core_rdc_qlfy_o))
) else $error("SCU core2soc qlfy error: qlfy wasn't raised prior to reset");
 
SCR1_SVA_SCU_CORE2HDU_QLFY_CHECK : assert property (
    @(negedge clk) disable iff (~pwrup_rst_n)
    $fell(core_rst_n_o) |-> $fell($past(core2hdu_rdc_qlfy_o))
) else $error("SCU core2hdu qlfy error: qlfy wasn't raised prior to reset");
 
SCR1_SVA_SCU_CORE2DM_QLFY_CHECK : assert property (
    @(negedge clk) disable iff (~pwrup_rst_n)
    $fell(core_rst_n_o) |-> $fell($past(core2dm_rdc_qlfy_o))
) else $error("SCU core2dm qlfy error: qlfy wasn't raised prior to reset");
 
SCR1_SVA_SCU_HDU2DM_QLFY_CHECK : assert property (
    @(negedge clk) disable iff (~pwrup_rst_n)
    $fell(hdu_rst_n_o) |-> $fell($past(hdu2dm_rdc_qlfy_o))
) else $error("SCU hdu2dm qlfy error: qlfy wasn't raised prior to reset");
`endif // VERILATOR
`endif // SCR1_TRGT_SIMULATION
 
endmodule : scr1_scu
`endif // SCR1_DBG_EN
 

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [scr1_scu.sv] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details`
2			`/// @file`
3			`/// @brief System Control Unit (SCU)`
4			`///`
5
6			`//------------------------------------------------------------------------------`
7			`//`
8			`// Functionality:`
9			`// - Generates System, Core, HDU and DM resets and their qualifier signals`
10			`// - Provides debugger with software System and Core resets generation functionality`
11			`// - Allows to set the behavior of DM and HDU resets`
12			`// - Shows resets Statuses and Sticky Statuses`
13
14			`// Structure:`
15			`// - TAPC scan-chain interface`
16			`// - SCU CSRs write/read interface`
17			`// - SCU CSRS:`
18			`// - CONTROL register`
19			`// - MODE register`
20			`// - STATUS register`
21			`// - STICKY_STATUS register`
22			`// - Reset logic`
23			`// - System Reset`
24			`// - Core Reset`
25			`// - DM Reset`
26			`// - HDU Reset`
27			`//------------------------------------------------------------------------------`
28
29			`include "scr1_arch_description.svh"
30			`include "scr1_scu.svh"
31
32			`ifdef SCR1_DBG_EN
33
34			`module scr1_scu (`
35			`// Global signals`
36			`input logic pwrup_rst_n, // Power-Up Reset`
37			`input logic rst_n, // Regular Reset`
38			`input logic cpu_rst_n, // CPU Reset`
39			`input logic test_mode, // DFT Test Mode`
40			`input logic test_rst_n, // DFT Test Reset`
41			`input logic clk, // SCU clock`
42
43			`// TAPC scan-chains`
44			`input logic tapcsync2scu_ch_sel_i, // TAPC Chain Select`
45			`input logic tapcsync2scu_ch_id_i, // TAPC Chain ID`
46			`input logic tapcsync2scu_ch_capture_i, // TAPC Chain Capture`
47			`input logic tapcsync2scu_ch_shift_i, // TAPC Chain Shift`
48			`input logic tapcsync2scu_ch_update_i, // TAPC Chain Update`
49			`input logic tapcsync2scu_ch_tdi_i, // TAPC Chain TDI`
50			`output logic scu2tapcsync_ch_tdo_o, // TAPC Chain TDO`
51
52			`// Input sync resets:`
53			`input logic ndm_rst_n_i, // Non-DM Reset input from DM`
54			`input logic hart_rst_n_i, // HART Reset from DM`
55
56			`// Generated resets`
57			`output logic sys_rst_n_o, // System/Cluster Reset`
58			`output logic core_rst_n_o, // Core Reset`
59			`output logic dm_rst_n_o, // Debug Module Reset`
60			`output logic hdu_rst_n_o, // HART Debug Unit Reset`
61
62			`// Resets statuses`
63			`output logic sys_rst_status_o, // System Reset Status (sync'ed to POR reset domain)`
64			`output logic core_rst_status_o, // Core Reset Status (sync'ed to POR reset domain)`
65
66			`// Reset Domain Crossing (RDC) qualifiers`
67			`output logic sys_rdc_qlfy_o, // System/Cluster-to-ExternalSOC Reset Domain Crossing Qualifier`
68			`output logic core_rdc_qlfy_o, // Core-to-ExternalSOC Reset Domain Crossing Qualifier`
69			`output logic core2hdu_rdc_qlfy_o, // Core-to-HDU Reset Domain Crossing Qualifier`
70			`output logic core2dm_rdc_qlfy_o, // Core-to-DM Reset Domain Crossing Qualifier`
71			`output logic hdu2dm_rdc_qlfy_o // HDU-to-DM Reset Domain Crossing Qualifier`
72			`);`
73
74			`//------------------------------------------------------------------------------`
75			`// Local Parameters`
76			`//======================================================================================================================`
77			`localparam int unsigned SCR1_SCU_RST_SYNC_STAGES_NUM = 2;`
78
79			`//------------------------------------------------------------------------------`
80			`// Local Signals`
81			`//------------------------------------------------------------------------------`
82
83			`// SCU CSR write/read i/f`
84			`//------------------------------------------------------------------------------`
85
86			`// TAPC scan-chain control logic`
87			`logic scu_csr_req;`
88			`logic tapc_dr_cap_req;`
89			`logic tapc_dr_shft_req;`
90			`logic tapc_dr_upd_req;`
91
92			`// TAPC shift register signals`
93			`logic tapc_shift_upd;`
94			`type_scr1_scu_sysctrl_dr_s tapc_shift_ff;`
95			`type_scr1_scu_sysctrl_dr_s tapc_shift_next;`
96
97			`// TAPC shadow register signals`
98			`type_scr1_scu_sysctrl_dr_s tapc_shadow_ff;`
99
100			`// SCU CSR write/read i/f`
101			`//------------------------------------------------------------------------------`
102
103			`logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] scu_csr_wdata;`
104			`logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] scu_csr_rdata;`
105
106			`// SCU CSRs signals`
107			`//------------------------------------------------------------------------------`
108
109			`// Control register`
110			`type_scr1_scu_sysctrl_control_reg_s scu_control_ff;`
111			`logic scu_control_wr_req;`
112
113			`// Mode register`
114			`type_scr1_scu_sysctrl_mode_reg_s scu_mode_ff;`
115			`logic scu_mode_wr_req;`
116
117			`// Status register`
118			`type_scr1_scu_sysctrl_status_reg_s scu_status_ff;`
119			`type_scr1_scu_sysctrl_status_reg_s scu_status_ff_dly;`
120			`type_scr1_scu_sysctrl_status_reg_s scu_status_ff_posedge;`
121
122			`// Sticky Status register`
123			`type_scr1_scu_sysctrl_status_reg_s scu_sticky_sts_ff;`
124			`logic scu_sticky_sts_wr_req;`
125
126			`// Reset logic signals`
127			`//------------------------------------------------------------------------------`
128
129			`// Input resets synchronization signals`
130			`logic pwrup_rst_n_sync;`
131			`logic rst_n_sync;`
132			`logic cpu_rst_n_sync;`
133
134			`// System Reset signals`
135			`logic sys_rst_n_in;`
136			`logic sys_rst_n_status;`
137			`logic sys_rst_n_status_sync;`
138			`logic sys_rst_n_qlfy;`
139			`logic sys_reset_n;`
140
141			`// Core Reset signals`
142			`logic core_rst_n_in_sync;`
143			`logic core_rst_n_status;`
144			`logic core_rst_n_status_sync;`
145			`logic core_rst_n_qlfy;`
146			`logic core_reset_n;`
147
148			`// HDU Reset signals`
149			`logic hdu_rst_n_in_sync;`
150			`logic hdu_rst_n_status;`
151			`logic hdu_rst_n_status_sync;`
152			`logic hdu_rst_n_qlfy;`
153
154			`// DM Reset signals`
155			`logic dm_rst_n_in;`
156			`logic dm_rst_n_status;`
157
158			`//------------------------------------------------------------------------------`
159			`// TAPC scan-chain i/f`
160			`//------------------------------------------------------------------------------`
161			`//`
162			`// Consists of the following functional units:`
163			`// - TAPC scan-chain control logic`
164			`// - TAPC shift register`
165			`// - TAPC shadow register`
166			`//`
167
168			`// TAPC scan-chain control logic`
169			`//------------------------------------------------------------------------------`
170
171			`assign scu_csr_req = tapcsync2scu_ch_sel_i & (tapcsync2scu_ch_id_i == '0);`
172			`assign tapc_dr_cap_req = scu_csr_req & tapcsync2scu_ch_capture_i;`
173			`assign tapc_dr_shft_req = scu_csr_req & tapcsync2scu_ch_shift_i;`
174			`assign tapc_dr_upd_req = scu_csr_req & tapcsync2scu_ch_update_i;`
175
176			`// TAPC shift register`
177			`//------------------------------------------------------------------------------`
178
179			`assign tapc_shift_upd = tapc_dr_cap_req \| tapc_dr_shft_req;`
180
181			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
182			`if (~pwrup_rst_n_sync) begin`
183			`tapc_shift_ff <= '0;`
184			`end else if (tapc_shift_upd) begin`
185			`tapc_shift_ff <= tapc_shift_next;`
186			`end`
187			`end`
188
189			`assign tapc_shift_next = tapc_dr_cap_req ? tapc_shadow_ff`
190			`: tapc_dr_shft_req ? {tapcsync2scu_ch_tdi_i, tapc_shift_ff[SCR1_SCU_DR_SYSCTRL_WIDTH-1:1]}// cp.5`
191			`: tapc_shift_ff;`
192
193			`// TAPC shadow register`
194			`//------------------------------------------------------------------------------`
195
196			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
197			`if (~pwrup_rst_n_sync) begin`
198			`tapc_shadow_ff <= '0;`
199			`end else if (tapc_dr_upd_req) begin`
200			`tapc_shadow_ff.op <= tapc_shift_ff.op;`
201			`tapc_shadow_ff.addr <= tapc_shift_ff.addr;`
202			`tapc_shadow_ff.data <= scu_csr_wdata;`
203			`end`
204			`end`
205
206			`assign scu2tapcsync_ch_tdo_o = tapc_shift_ff[0];`
207
208			`//------------------------------------------------------------------------------`
209			`// SCU CSRs write/read interface`
210			`//------------------------------------------------------------------------------`
211
212			`// Write interface`
213			`//------------------------------------------------------------------------------`
214
215			`// Register selection logic`
216			`always_comb begin`
217			`scu_control_wr_req = 1'b0;`
218			`scu_mode_wr_req = 1'b0;`
219			`scu_sticky_sts_wr_req = 1'b0;`
220
221			`if (tapc_dr_upd_req && (tapc_shift_ff.op != SCR1_SCU_SYSCTRL_OP_READ)) begin`
222			`case (tapc_shift_ff.addr)`
223			`SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_control_wr_req = 1'b1;`
224			`SCR1_SCU_SYSCTRL_ADDR_MODE : scu_mode_wr_req = 1'b1;`
225			`SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_sticky_sts_wr_req = (tapc_shift_ff.op == SCR1_SCU_SYSCTRL_OP_CLRBITS);`
226			`default : begin end`
227			`endcase`
228			`end`
229			`end`
230
231			`// Write data construction`
232			`always_comb begin`
233			`scu_csr_wdata = '0;`
234
235			`if (tapc_dr_upd_req) begin`
236			`case (tapc_shift_ff.op)`
237			`SCR1_SCU_SYSCTRL_OP_WRITE : scu_csr_wdata = tapc_shift_ff.data;`
238			`SCR1_SCU_SYSCTRL_OP_READ : scu_csr_wdata = scu_csr_rdata;`
239			`SCR1_SCU_SYSCTRL_OP_SETBITS: scu_csr_wdata = scu_csr_rdata \| tapc_shift_ff.data;`
240			`SCR1_SCU_SYSCTRL_OP_CLRBITS: scu_csr_wdata = scu_csr_rdata & (~tapc_shift_ff.data);`
241			`default : begin end`
242			`endcase`
243			`end`
244			`end`
245
246			`// Read interface`
247			`//------------------------------------------------------------------------------`
248
249			`// Read data multiplexer`
250			`always_comb begin`
251			`scu_csr_rdata = '0;`
252
253			`if (tapc_dr_upd_req) begin`
254			`case (tapc_shift_ff.addr)`
255			`SCR1_SCU_SYSCTRL_ADDR_CONTROL: scu_csr_rdata = scu_control_ff;`
256			`SCR1_SCU_SYSCTRL_ADDR_MODE : scu_csr_rdata = scu_mode_ff;`
257			`SCR1_SCU_SYSCTRL_ADDR_STATUS : scu_csr_rdata = scu_status_ff;`
258			`SCR1_SCU_SYSCTRL_ADDR_STICKY : scu_csr_rdata = scu_sticky_sts_ff;`
259			`default : scu_csr_rdata = 'x;`
260			`endcase`
261			`end`
262			`end`
263
264			`//------------------------------------------------------------------------------`
265			`// SCU CSRs`
266			`//------------------------------------------------------------------------------`
267			`//`
268			`// Registers:`
269			`// - CONTROL register`
270			`// - MODE register`
271			`// - STATUS register`
272			`// - STICKY_STATUS register`
273			`//`
274
275			`// CONTROL register`
276			`//------------------------------------------------------------------------------`
277			`// Allows debugger to generate System and Core resets`
278
279			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
280			`if (~pwrup_rst_n_sync) begin`
281			`scu_control_ff <= '0;`
282			`end else if (scu_control_wr_req) begin`
283			`scu_control_ff <= scu_csr_wdata;`
284			`end`
285			`end`
286
287			`// MODE register`
288			`//------------------------------------------------------------------------------`
289			`// Sets reset behavior for DM Reset and HDU Reset signals`
290
291			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
292			`if (~pwrup_rst_n_sync) begin`
293			`scu_mode_ff <= '0;`
294			`end else if (scu_mode_wr_req) begin`
295			`scu_mode_ff <= scu_csr_wdata;`
296			`end`
297			`end`
298
299			`// STATUS register`
300			`//------------------------------------------------------------------------------`
301			`// Holds the status of every output reset signal (System, Core, DM and HDU)`
302
303			`assign scu_status_ff.sys_reset = sys_rst_status_o ;`
304			`assign scu_status_ff.core_reset = core_rst_status_o;`
305			`assign scu_status_ff.dm_reset = ~dm_rst_n_status;`
306			`assign scu_status_ff.hdu_reset = ~hdu_rst_n_status_sync;`
307
308			`// Status Register positive edge detection logic`
309			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
310			`if (~pwrup_rst_n_sync) begin`
311			`scu_status_ff_dly <= '0;`
312			`end else begin`
313			`scu_status_ff_dly <= scu_status_ff;`
314			`end`
315			`end`
316
317			`assign scu_status_ff_posedge = scu_status_ff & ~scu_status_ff_dly;`
318
319			`// STICKY_STATUS register`
320			`//------------------------------------------------------------------------------`
321			`// For every output reset signal shows if it was asserted since the last bit clearing`
322			`integer i;`
323			`always_ff @(posedge clk, negedge pwrup_rst_n_sync) begin`
324			`if (~pwrup_rst_n_sync) begin`
325			`scu_sticky_sts_ff <= '0;`
326			`end else begin`
327			`for (i = 0; i < SCR1_SCU_SYSCTRL_STATUS_REG_WIDTH ; i=i+1) begin // cp.4`
328			`if (scu_status_ff_posedge[i]) begin`
329			`scu_sticky_sts_ff[i] <= 1'b1;`
330			`end else if (scu_sticky_sts_wr_req) begin`
331			`scu_sticky_sts_ff[i] <= scu_csr_wdata[i];`
332			`end`
333			`end`
334			`end`
335			`end`
336
337			`//------------------------------------------------------------------------------`
338			`// Reset logic`
339			`//------------------------------------------------------------------------------`
340			`//`
341			`// Consists of the following functional units:`
342			`// - System Reset logic`
343			`// - Core Reset logic`
344			`// - Hart Debug Unit Reset logic`
345			`// - Debug Module Reset logic`
346			`//`
347
348			`// Reset inputs are assumed synchronous`
349			`assign pwrup_rst_n_sync = pwrup_rst_n;`
350			`assign rst_n_sync = rst_n;`
351			`assign cpu_rst_n_sync = cpu_rst_n;`
352
353			`// Intermediate resets:`
354			`assign sys_reset_n = ~scu_control_ff.sys_reset;`
355			`assign core_reset_n = ~scu_control_ff.core_reset;`
356
357			`// System/Cluster Reset: sys_rst_n_o`
358			`//------------------------------------------------------------------------------`
359
360			`scr1_reset_qlfy_adapter_cell_sync i_sys_rstn_qlfy_adapter_cell_sync (`
361			`.rst_n (pwrup_rst_n_sync),`
362			`.clk (clk ),`
363			`.test_rst_n (test_rst_n ),`
364			`.test_mode (test_mode ),`
365			`.reset_n_in_sync (sys_rst_n_in ),`
366			`.reset_n_out_qlfy (sys_rst_n_qlfy ),`
367			`.reset_n_out (sys_rst_n_o ),`
368			`.reset_n_status (sys_rst_n_status)`
369			`);`
370
371			`assign sys_rst_n_in = sys_reset_n & ndm_rst_n_i & rst_n_sync;`
372
373			`scr1_data_sync_cell #(`
374			`.STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)`
375			`) i_sys_rstn_status_sync (`
376			`.rst_n (pwrup_rst_n_sync ),`
377			`.clk (clk ),`
378			`.data_in (sys_rst_n_status ),`
379			`.data_out (sys_rst_n_status_sync)`
380			`);`
381
382			`assign sys_rst_status_o = ~sys_rst_n_status_sync;`
383
384			`// System/Cluster-to-ExternalSOC RDC qualifier`
385			`assign sys_rdc_qlfy_o = sys_rst_n_qlfy;`
386
387			`// Core Reset: core_rst_n_o`
388			`//------------------------------------------------------------------------------`
389
390			`scr1_reset_qlfy_adapter_cell_sync i_core_rstn_qlfy_adapter_cell_sync (`
391			`.rst_n (pwrup_rst_n_sync ),`
392			`.clk (clk ),`
393			`.test_rst_n (test_rst_n ),`
394			`.test_mode (test_mode ),`
395			`.reset_n_in_sync (core_rst_n_in_sync),`
396			`.reset_n_out_qlfy (core_rst_n_qlfy ),`
397			`.reset_n_out (core_rst_n_o ),`
398			`.reset_n_status (core_rst_n_status )`
399			`);`
400
401			`assign core_rst_n_in_sync = sys_rst_n_in & hart_rst_n_i & core_reset_n & cpu_rst_n_sync;`
402
403			`scr1_data_sync_cell #(`
404			`.STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)`
405			`) i_core_rstn_status_sync (`
406			`.rst_n (pwrup_rst_n_sync ),`
407			`.clk (clk ),`
408			`.data_in (core_rst_n_status ),`
409			`.data_out (core_rst_n_status_sync)`
410			`);`
411
412			`assign core_rst_status_o = ~core_rst_n_status_sync;`
413
414			`// Core Reset RDC Qualifiers:`
415			`// - Core-to-ExternalSOC RDC Qlfy`
416			`assign core_rdc_qlfy_o = core_rst_n_qlfy;`
417			`// - Core-to-HDU RDC Qlfy`
418			`assign core2hdu_rdc_qlfy_o = core_rst_n_qlfy;`
419			`// - Core-to-DebugModule RDC Qlfy`
420			`assign core2dm_rdc_qlfy_o = core_rst_n_qlfy;`
421
422			`// Hart Debug Unit Reset: hdu_rst_n_o`
423			`//------------------------------------------------------------------------------`
424
425			`scr1_reset_qlfy_adapter_cell_sync i_hdu_rstn_qlfy_adapter_cell_sync (`
426			`.rst_n (pwrup_rst_n_sync ),`
427			`.clk (clk ),`
428			`.test_rst_n (test_rst_n ),`
429			`.test_mode (test_mode ),`
430			`.reset_n_in_sync (hdu_rst_n_in_sync),`
431			`.reset_n_out_qlfy (hdu_rst_n_qlfy ),`
432			`.reset_n_out (hdu_rst_n_o ),`
433			`.reset_n_status (hdu_rst_n_status )`
434			`);`
435
436			`assign hdu_rst_n_in_sync = scu_mode_ff.hdu_rst_bhv \| core_rst_n_in_sync;`
437
438			`scr1_data_sync_cell #(`
439			`.STAGES_AMOUNT (SCR1_SCU_RST_SYNC_STAGES_NUM)`
440			`) i_hdu_rstn_status_sync (`
441			`.rst_n (pwrup_rst_n_sync ),`
442			`.clk (clk ),`
443			`.data_in (hdu_rst_n_status ),`
444			`.data_out (hdu_rst_n_status_sync)`
445			`);`
446
447			`// Hart Debug Unit Reset RDC Qualifiers:`
448			`// - HDU-to-DebugModule RDC Qlfy`
449			`assign hdu2dm_rdc_qlfy_o = hdu_rst_n_qlfy;`
450
451			`// Debug Module Reset: dm_rst_n_o`
452			`//------------------------------------------------------------------------------`
453
454			`scr1_reset_buf_cell i_dm_rstn_buf_cell (`
455			`.rst_n (pwrup_rst_n_sync),`
456			`.clk (clk ),`
457			`.test_mode (test_mode ),`
458			`.test_rst_n (test_rst_n ),`
459			`.reset_n_in (dm_rst_n_in ),`
460			`.reset_n_out (dm_rst_n_o ),`
461			`.reset_n_status (dm_rst_n_status )`
462			`);`
463
464			`assign dm_rst_n_in = ~scu_mode_ff.dm_rst_bhv \| sys_reset_n;`
465
466			`ifdef SCR1_TRGT_SIMULATION
467			`//--------------------------------------------------------------------`
468			`// Assertions`
469			`//--------------------------------------------------------------------`
470
471			`ifndef VERILATOR
472			`// Preventing some assertions to be raised at 0 sim time or in the first cycle`
473			`initial begin`
474			`$assertoff(0, scr1_scu);`
475			`repeat (2) @(posedge clk);`
476			`$asserton(0, scr1_scu);`
477			`end`
478			`endif // VERILATOR
479
480			`// X checks`
481			`SCR1_SVA_SCU_RESETS_XCHECK : assert property (`
482			`@(negedge clk)`
483			`!$isunknown({pwrup_rst_n, rst_n, cpu_rst_n, ndm_rst_n_i, hart_rst_n_i})`
484			`) else $error("SCU resets error: unknown values of input resets");`
485
486			`ifndef VERILATOR
487			`// Qualifiers checks`
488			`SCR1_SVA_SCU_SYS2SOC_QLFY_CHECK : assert property (`
489			`@(negedge clk) disable iff (~pwrup_rst_n)`
490			`$fell(sys_rst_n_o) \|-> $fell($past(sys_rdc_qlfy_o))`
491			`) else $error("SCU sys2soc qlfy error: qlfy wasn't raised prior to reset");`
492
493			`SCR1_SVA_SCU_CORE2SOC_QLFY_CHECK : assert property (`
494			`@(negedge clk) disable iff (~pwrup_rst_n)`
495			`$fell(core_rst_n_o) \|-> $fell($past(core_rdc_qlfy_o))`
496			`) else $error("SCU core2soc qlfy error: qlfy wasn't raised prior to reset");`
497
498			`SCR1_SVA_SCU_CORE2HDU_QLFY_CHECK : assert property (`
499			`@(negedge clk) disable iff (~pwrup_rst_n)`
500			`$fell(core_rst_n_o) \|-> $fell($past(core2hdu_rdc_qlfy_o))`
501			`) else $error("SCU core2hdu qlfy error: qlfy wasn't raised prior to reset");`
502
503			`SCR1_SVA_SCU_CORE2DM_QLFY_CHECK : assert property (`
504			`@(negedge clk) disable iff (~pwrup_rst_n)`
505			`$fell(core_rst_n_o) \|-> $fell($past(core2dm_rdc_qlfy_o))`
506			`) else $error("SCU core2dm qlfy error: qlfy wasn't raised prior to reset");`
507
508			`SCR1_SVA_SCU_HDU2DM_QLFY_CHECK : assert property (`
509			`@(negedge clk) disable iff (~pwrup_rst_n)`
510			`$fell(hdu_rst_n_o) \|-> $fell($past(hdu2dm_rdc_qlfy_o))`
511			`) else $error("SCU hdu2dm qlfy error: qlfy wasn't raised prior to reset");`
512			`endif // VERILATOR
513			`endif // SCR1_TRGT_SIMULATION
514
515			`endmodule : scr1_scu`
516			`endif // SCR1_DBG_EN
517