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/// Copyright by Syntacore LLC � 2016-2021. See LICENSE for details
/// @file       
/// @brief      TAP Controller (TAPC)
///
 
//------------------------------------------------------------------------------
 //
 // Functionality:
 // - Controls TAP operation
 // - Allows debugger to access TAP Data registers and DMI/SCU scan-chains via
 //   command written in Instruction register
 //
 // Structure:
 // - Synchronous reset generation
 // - TAPC FSM
 // - TAPC Instruction Registers
 // - TAPC DRs/DMI/SCU scan-chains
 // - TAPC TDO enable and output Registers
 // - TAPC Data Registers
 //   - BYPASS
 //   - IDCODE
 //   - BUILD ID
 //
//------------------------------------------------------------------------------
 
`include "scr1_arch_description.svh"
 
`ifdef SCR1_DBG_EN
`include "scr1_tapc.svh"
`include "scr1_dm.svh"
 
module scr1_tapc (
    // JTAG signals
    input   logic                                   tapc_trst_n,                    // Test Reset (TRSTn)
    input   logic                                   tapc_tck,                       // Test Clock (TCK)
    input   logic                                   tapc_tms,                       // Test Mode Select (TMS)
    input   logic                                   tapc_tdi,                       // Test Data Input (TDI)
    output  logic                                   tapc_tdo,                       // Test Data Output (TDO)
    output  logic                                   tapc_tdo_en,                    // TDO Enable, signal for TDO buffer control
 
    // Fuses:
    input   logic [31:0]                            soc2tapc_fuse_idcode_i,         // IDCODE value from fuses
 
    // DMI/SCU scan-chains
    output  logic                                   tapc2tapcsync_scu_ch_sel_o,     // SCU Chain Select
    output  logic                                   tapc2tapcsync_dmi_ch_sel_o,     // DMI Chain Select
    output  logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]    tapc2tapcsync_ch_id_o,          // DMI/SCU Chain Identifier
    output  logic                                   tapc2tapcsync_ch_capture_o,     // DMI/SCU Chain Capture
    output  logic                                   tapc2tapcsync_ch_shift_o,       // DMI/SCU Chain Shift
    output  logic                                   tapc2tapcsync_ch_update_o,      // DMI/SCU Chain Update
    output  logic                                   tapc2tapcsync_ch_tdi_o,         // DMI/SCU Chain TDI
    input   logic                                   tapcsync2tapc_ch_tdo_i          // DMI/SCU Chain TDO
);
 
//------------------------------------------------------------------------------
// Local Signals
//------------------------------------------------------------------------------
 
logic                                       trst_n_int;       // Sync reset signal
 
// TAPC FSM signals
//------------------------------------------------------------------------------
 
type_scr1_tap_state_e                       tap_fsm_ff;       // TAP's current state
type_scr1_tap_state_e                       tap_fsm_next;     // TAP's next state
 
// Control signals
logic                                       tap_fsm_reset;
logic                                       tap_fsm_ir_upd;
logic                                       tap_fsm_ir_cap;
logic                                       tap_fsm_ir_shft;
 
// Registered control signals
logic                                       tap_fsm_ir_shift_ff;
logic                                       tap_fsm_ir_shift_next;
logic                                       tap_fsm_dr_capture_ff;
logic                                       tap_fsm_dr_capture_next;
logic                                       tap_fsm_dr_shift_ff;
logic                                       tap_fsm_dr_shift_next;
logic                                       tap_fsm_dr_update_ff;
logic                                       tap_fsm_dr_update_next;
 
// TAPC Instruction Registers signals
//------------------------------------------------------------------------------
 
logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_shift_ff;   // Instruction Shift Register
logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_shift_next; // Instruction Shift Register next value
logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_ff;         // Instruction Register
logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0]      tap_ir_next;       // Instruction Register next value
 
// TAPC Data Registers signals
//------------------------------------------------------------------------------
 
// BYPASS register
logic                                       dr_bypass_sel;
logic                                       dr_bypass_tdo;
 
// IDCODE register
logic                                       dr_idcode_sel;
logic                                       dr_idcode_tdo;
 
// BUILD ID register
logic                                       dr_bld_id_sel;
logic                                       dr_bld_id_tdo;
 
logic                                       dr_out;
 
// TDO registers
//------------------------------------------------------------------------------
 
// TDO enable register
logic                                       tdo_en_ff;
logic                                       tdo_en_next;
 
// TDO output register
logic                                       tdo_out_ff;
logic                                       tdo_out_next;
 
//------------------------------------------------------------------------------
// TAPC Synchronous Reset logic
//------------------------------------------------------------------------------
 
always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        trst_n_int <= 1'b0;
    end else begin
        trst_n_int <= ~tap_fsm_reset;
    end
end
 
//------------------------------------------------------------------------------
// TAP's FSM
//------------------------------------------------------------------------------
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_fsm_ff <= SCR1_TAP_STATE_RESET;
    end else begin
        tap_fsm_ff <= tap_fsm_next;
    end
end
 
always_comb begin
    case (tap_fsm_ff)
        SCR1_TAP_STATE_RESET      : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET        : SCR1_TAP_STATE_IDLE;
        SCR1_TAP_STATE_IDLE       : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
        SCR1_TAP_STATE_DR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_SEL_SCAN  : SCR1_TAP_STATE_DR_CAPTURE;
        SCR1_TAP_STATE_DR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1     : SCR1_TAP_STATE_DR_SHIFT;
        SCR1_TAP_STATE_DR_SHIFT   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1     : SCR1_TAP_STATE_DR_SHIFT;
        SCR1_TAP_STATE_DR_EXIT1   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE    : SCR1_TAP_STATE_DR_PAUSE;
        SCR1_TAP_STATE_DR_PAUSE   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT2     : SCR1_TAP_STATE_DR_PAUSE;
        SCR1_TAP_STATE_DR_EXIT2   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE    : SCR1_TAP_STATE_DR_SHIFT;
        SCR1_TAP_STATE_DR_UPDATE  : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
        SCR1_TAP_STATE_IR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET        : SCR1_TAP_STATE_IR_CAPTURE;
        SCR1_TAP_STATE_IR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1     : SCR1_TAP_STATE_IR_SHIFT;
        SCR1_TAP_STATE_IR_SHIFT   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1     : SCR1_TAP_STATE_IR_SHIFT;
        SCR1_TAP_STATE_IR_EXIT1   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE    : SCR1_TAP_STATE_IR_PAUSE;
        SCR1_TAP_STATE_IR_PAUSE   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT2     : SCR1_TAP_STATE_IR_PAUSE;
        SCR1_TAP_STATE_IR_EXIT2   : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE    : SCR1_TAP_STATE_IR_SHIFT;
        SCR1_TAP_STATE_IR_UPDATE  : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN  : SCR1_TAP_STATE_IDLE;
`ifdef SCR1_XPROP_EN
        default                   : tap_fsm_next = SCR1_TAP_STATE_XXX;
`else // SCR1_XPROP_EN
        default                   : tap_fsm_next = tap_fsm_ff;
`endif // SCR1_XPROP_EN
    endcase
end
 
assign tap_fsm_reset   = (tap_fsm_ff == SCR1_TAP_STATE_RESET);
assign tap_fsm_ir_upd  = (tap_fsm_ff == SCR1_TAP_STATE_IR_UPDATE);
assign tap_fsm_ir_cap  = (tap_fsm_ff == SCR1_TAP_STATE_IR_CAPTURE);
assign tap_fsm_ir_shft = (tap_fsm_ff == SCR1_TAP_STATE_IR_SHIFT);
 
//------------------------------------------------------------------------------
// TAPC Instruction Registers
//------------------------------------------------------------------------------
 
// TAPC Instruction Shift register
//------------------------------------------------------------------------------
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_ir_shift_ff <= '0;
    end else if (~trst_n_int) begin
        tap_ir_shift_ff <= '0;
    end else begin
        tap_ir_shift_ff <= tap_ir_shift_next;
    end
end
 
assign tap_ir_shift_next = tap_fsm_ir_cap  ? {{($bits(tap_ir_shift_ff)-1){1'b0}}, 1'b1}
                         : tap_fsm_ir_shft ? {tapc_tdi, tap_ir_shift_ff[$left(tap_ir_shift_ff):1]}
                                           : tap_ir_shift_ff;
 
// TAPC Instruction register
//------------------------------------------------------------------------------
 
always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;
    end else if (~trst_n_int) begin
        tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;
    end else begin
        tap_ir_ff <= tap_ir_next;
    end
end
 
assign tap_ir_next = tap_fsm_ir_upd ? tap_ir_shift_ff : tap_ir_ff;
 
//------------------------------------------------------------------------------
// Control signals
//------------------------------------------------------------------------------
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_fsm_ir_shift_ff <= 1'b0;
    end else if (~trst_n_int) begin
        tap_fsm_ir_shift_ff <= 1'b0;
    end else begin
        tap_fsm_ir_shift_ff <= tap_fsm_ir_shift_next;
    end
end
 
assign tap_fsm_ir_shift_next = (tap_fsm_next == SCR1_TAP_STATE_IR_SHIFT);
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_fsm_dr_capture_ff <= 1'b0;
    end else if (~trst_n_int) begin
        tap_fsm_dr_capture_ff <= 1'b0;
    end else begin
        tap_fsm_dr_capture_ff <= tap_fsm_dr_capture_next;
    end
end
 
assign tap_fsm_dr_capture_next = (tap_fsm_next == SCR1_TAP_STATE_DR_CAPTURE);
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_fsm_dr_shift_ff <= 1'b0;
    end else if (~trst_n_int) begin
        tap_fsm_dr_shift_ff <= 1'b0;
    end else begin
        tap_fsm_dr_shift_ff <= tap_fsm_dr_shift_next;
    end
end
 
assign tap_fsm_dr_shift_next = (tap_fsm_next == SCR1_TAP_STATE_DR_SHIFT);
 
always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tap_fsm_dr_update_ff <= 1'b0;
    end else if (~trst_n_int) begin
        tap_fsm_dr_update_ff <= 1'b0;
    end else begin
        tap_fsm_dr_update_ff <= tap_fsm_dr_update_next;
    end
end
 
assign tap_fsm_dr_update_next = (tap_fsm_next == SCR1_TAP_STATE_DR_UPDATE);
 
//------------------------------------------------------------------------------
// TAPC DRs/DMI/SCU scan-chains
//------------------------------------------------------------------------------
//
 // Consists of the following functional units:
 // - Data source/destination decoder
 // - DMI channel ID decoder
 
// - Read data multiplexer
// Data source/destination decoder
//------------------------------------------------------------------------------
 
always_comb begin
    dr_bypass_sel               = 1'b0;
    dr_idcode_sel               = 1'b0;
    dr_bld_id_sel               = 1'b0;
    tapc2tapcsync_scu_ch_sel_o  = 1'b0;
    tapc2tapcsync_dmi_ch_sel_o  = 1'b0;
    case (tap_ir_ff)
        SCR1_TAP_INSTR_DTMCS     : tapc2tapcsync_dmi_ch_sel_o = 1'b1;
        SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_dmi_ch_sel_o = 1'b1;
        SCR1_TAP_INSTR_IDCODE    : dr_idcode_sel              = 1'b1;
        SCR1_TAP_INSTR_BYPASS    : dr_bypass_sel              = 1'b1;
        SCR1_TAP_INSTR_BLD_ID    : dr_bld_id_sel              = 1'b1;
        SCR1_TAP_INSTR_SCU_ACCESS: tapc2tapcsync_scu_ch_sel_o = 1'b1;
        default                  : dr_bypass_sel              = 1'b1;
    endcase
end
 
// DMI channel ID decoder
//------------------------------------------------------------------------------
 
always_comb begin
    tapc2tapcsync_ch_id_o = '0;
    case (tap_ir_ff)
        SCR1_TAP_INSTR_DTMCS     : tapc2tapcsync_ch_id_o = 'd1;
        SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_ch_id_o = 'd2;
        default                  : tapc2tapcsync_ch_id_o = '0;
    endcase
end
 
// Read data multiplexer
//------------------------------------------------------------------------------
 
always_comb begin
    dr_out = 1'b0;
    case (tap_ir_ff)
        SCR1_TAP_INSTR_DTMCS     : dr_out = tapcsync2tapc_ch_tdo_i;
        SCR1_TAP_INSTR_DMI_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;
        SCR1_TAP_INSTR_IDCODE    : dr_out = dr_idcode_tdo;
        SCR1_TAP_INSTR_BYPASS    : dr_out = dr_bypass_tdo;
        SCR1_TAP_INSTR_BLD_ID    : dr_out = dr_bld_id_tdo;
        SCR1_TAP_INSTR_SCU_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;
        default                  : dr_out = dr_bypass_tdo;
    endcase
end
 
//------------------------------------------------------------------------------
// TDO enable and output registers
//------------------------------------------------------------------------------
 
// TDO enable register
//------------------------------------------------------------------------------
 
always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tdo_en_ff  <= 1'b0;
    end else if (~trst_n_int) begin
        tdo_en_ff  <= 1'b0;
    end else begin
        tdo_en_ff  <= tdo_en_next;
    end
end
 
assign tdo_en_next = tap_fsm_dr_shift_ff | tap_fsm_ir_shift_ff;
 
// TDO output register
//------------------------------------------------------------------------------
 
always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
    if (~tapc_trst_n) begin
        tdo_out_ff <= 1'b0;
    end else if (~trst_n_int) begin
        tdo_out_ff <= 1'b0;
    end else begin
        tdo_out_ff <= tdo_out_next;
    end
end
 
assign tdo_out_next = tap_fsm_dr_shift_ff ? dr_out
                    : tap_fsm_ir_shift_ff ? tap_ir_shift_ff[0]
                                          : 1'b0;
 
// TAPC TDO signals
assign tapc_tdo_en = tdo_en_ff;
assign tapc_tdo    = tdo_out_ff;
 
//------------------------------------------------------------------------------
// TAPC Data Registers
//------------------------------------------------------------------------------
//
 // Registers:
 // - BYPASS register
 // - IDCODE register
 // - BUILD ID register
 
// BYPASS register
//------------------------------------------------------------------------------
// 1-bit mandatory IEEE 1149.1 compliant register
 
scr1_tapc_shift_reg  #(
    .SCR1_WIDTH       (SCR1_TAP_DR_BYPASS_WIDTH),
    .SCR1_RESET_VALUE (SCR1_TAP_DR_BYPASS_WIDTH'(0))
) i_bypass_reg        (
    .clk              (tapc_tck             ),
    .rst_n            (tapc_trst_n          ),
    .rst_n_sync       (trst_n_int           ),
    .fsm_dr_select    (dr_bypass_sel        ),
    .fsm_dr_capture   (tap_fsm_dr_capture_ff),
    .fsm_dr_shift     (tap_fsm_dr_shift_ff  ),
    .din_serial       (tapc_tdi             ),
    .din_parallel     (1'b0                 ),
    .dout_serial      (dr_bypass_tdo        ),
    .dout_parallel    (                     )
);
 
// IDCODE register
//------------------------------------------------------------------------------
// Holds the Device ID value (mandatory IEEE 1149.1 compliant register)
 
scr1_tapc_shift_reg  #(
    .SCR1_WIDTH       (SCR1_TAP_DR_IDCODE_WIDTH),
    .SCR1_RESET_VALUE (SCR1_TAP_DR_IDCODE_WIDTH'(0))
) i_tap_idcode_reg    (
    .clk              (tapc_tck              ),
    .rst_n            (tapc_trst_n           ),
    .rst_n_sync       (trst_n_int            ),
    .fsm_dr_select    (dr_idcode_sel         ),
    .fsm_dr_capture   (tap_fsm_dr_capture_ff ),
    .fsm_dr_shift     (tap_fsm_dr_shift_ff   ),
    .din_serial       (tapc_tdi              ),
    .din_parallel     (soc2tapc_fuse_idcode_i),
    .dout_serial      (dr_idcode_tdo         ),
    .dout_parallel    (                      )
);
 
// BUILD ID register
//------------------------------------------------------------------------------
// Holds the BUILD ID value
 
scr1_tapc_shift_reg  #(
    .SCR1_WIDTH       (SCR1_TAP_DR_BLD_ID_WIDTH),
    .SCR1_RESET_VALUE (SCR1_TAP_DR_BLD_ID_WIDTH'(0))
) i_tap_dr_bld_id_reg (
    .clk              (tapc_tck             ),
    .rst_n            (tapc_trst_n          ),
    .rst_n_sync       (trst_n_int           ),
    .fsm_dr_select    (dr_bld_id_sel        ),
    .fsm_dr_capture   (tap_fsm_dr_capture_ff),
    .fsm_dr_shift     (tap_fsm_dr_shift_ff  ),
    .din_serial       (tapc_tdi             ),
    .din_parallel     (SCR1_TAP_BLD_ID_VALUE),
    .dout_serial      (dr_bld_id_tdo        ),
    .dout_parallel    (                     )
);
 
//------------------------------------------------------------------------------
// DMI/SCU scan-chains signals
//------------------------------------------------------------------------------
 
assign tapc2tapcsync_ch_tdi_o     = tapc_tdi;
assign tapc2tapcsync_ch_capture_o = tap_fsm_dr_capture_ff;
assign tapc2tapcsync_ch_shift_o   = tap_fsm_dr_shift_ff;
assign tapc2tapcsync_ch_update_o  = tap_fsm_dr_update_ff;
 
`ifdef SCR1_TRGT_SIMULATION
//-------------------------------------------------------------------------------
// Assertion
//-------------------------------------------------------------------------------
 
// X checks
SCR1_SVA_TAPC_XCHECK : assert property (
    @(posedge tapc_tck) disable iff (~tapc_trst_n)
    !$isunknown({tapc_tms, tapc_tdi})
) else $error("TAPC error: unknown values");
 
SCR1_SVA_TAPC_XCHECK_NEGCLK : assert property (
    @(negedge tapc_tck) disable iff (tap_fsm_ff != SCR1_TAP_STATE_DR_SHIFT)
    !$isunknown({tapcsync2tapc_ch_tdo_i})
) else $error("TAPC @negedge error: unknown values");
 
`endif // SCR1_TRGT_SIMULATION
 
endmodule : scr1_tapc
 
`endif // SCR1_DBG_EN

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [scr1_tapc.sv] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC � 2016-2021. See LICENSE for details`
2			`/// @file`
3			`/// @brief TAP Controller (TAPC)`
4			`///`
5
6			`//------------------------------------------------------------------------------`
7			`//`
8			`// Functionality:`
9			`// - Controls TAP operation`
10			`// - Allows debugger to access TAP Data registers and DMI/SCU scan-chains via`
11			`// command written in Instruction register`
12			`//`
13			`// Structure:`
14			`// - Synchronous reset generation`
15			`// - TAPC FSM`
16			`// - TAPC Instruction Registers`
17			`// - TAPC DRs/DMI/SCU scan-chains`
18			`// - TAPC TDO enable and output Registers`
19			`// - TAPC Data Registers`
20			`// - BYPASS`
21			`// - IDCODE`
22			`// - BUILD ID`
23			`//`
24			`//------------------------------------------------------------------------------`
25
26			`include "scr1_arch_description.svh"
27
28			`ifdef SCR1_DBG_EN
29			`include "scr1_tapc.svh"
30			`include "scr1_dm.svh"
31
32			`module scr1_tapc (`
33			`// JTAG signals`
34			`input logic tapc_trst_n, // Test Reset (TRSTn)`
35			`input logic tapc_tck, // Test Clock (TCK)`
36			`input logic tapc_tms, // Test Mode Select (TMS)`
37			`input logic tapc_tdi, // Test Data Input (TDI)`
38			`output logic tapc_tdo, // Test Data Output (TDO)`
39			`output logic tapc_tdo_en, // TDO Enable, signal for TDO buffer control`
40
41			`// Fuses:`
42			`input logic [31:0] soc2tapc_fuse_idcode_i, // IDCODE value from fuses`
43
44			`// DMI/SCU scan-chains`
45			`output logic tapc2tapcsync_scu_ch_sel_o, // SCU Chain Select`
46			`output logic tapc2tapcsync_dmi_ch_sel_o, // DMI Chain Select`
47			`output logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0] tapc2tapcsync_ch_id_o, // DMI/SCU Chain Identifier`
48			`output logic tapc2tapcsync_ch_capture_o, // DMI/SCU Chain Capture`
49			`output logic tapc2tapcsync_ch_shift_o, // DMI/SCU Chain Shift`
50			`output logic tapc2tapcsync_ch_update_o, // DMI/SCU Chain Update`
51			`output logic tapc2tapcsync_ch_tdi_o, // DMI/SCU Chain TDI`
52			`input logic tapcsync2tapc_ch_tdo_i // DMI/SCU Chain TDO`
53			`);`
54
55			`//------------------------------------------------------------------------------`
56			`// Local Signals`
57			`//------------------------------------------------------------------------------`
58
59			`logic trst_n_int; // Sync reset signal`
60
61			`// TAPC FSM signals`
62			`//------------------------------------------------------------------------------`
63
64			`type_scr1_tap_state_e tap_fsm_ff; // TAP's current state`
65			`type_scr1_tap_state_e tap_fsm_next; // TAP's next state`
66
67			`// Control signals`
68			`logic tap_fsm_reset;`
69			`logic tap_fsm_ir_upd;`
70			`logic tap_fsm_ir_cap;`
71			`logic tap_fsm_ir_shft;`
72
73			`// Registered control signals`
74			`logic tap_fsm_ir_shift_ff;`
75			`logic tap_fsm_ir_shift_next;`
76			`logic tap_fsm_dr_capture_ff;`
77			`logic tap_fsm_dr_capture_next;`
78			`logic tap_fsm_dr_shift_ff;`
79			`logic tap_fsm_dr_shift_next;`
80			`logic tap_fsm_dr_update_ff;`
81			`logic tap_fsm_dr_update_next;`
82
83			`// TAPC Instruction Registers signals`
84			`//------------------------------------------------------------------------------`
85
86			`logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_shift_ff; // Instruction Shift Register`
87			`logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_shift_next; // Instruction Shift Register next value`
88			`logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_ff; // Instruction Register`
89			`logic [SCR1_TAP_INSTRUCTION_WIDTH-1:0] tap_ir_next; // Instruction Register next value`
90
91			`// TAPC Data Registers signals`
92			`//------------------------------------------------------------------------------`
93
94			`// BYPASS register`
95			`logic dr_bypass_sel;`
96			`logic dr_bypass_tdo;`
97
98			`// IDCODE register`
99			`logic dr_idcode_sel;`
100			`logic dr_idcode_tdo;`
101
102			`// BUILD ID register`
103			`logic dr_bld_id_sel;`
104			`logic dr_bld_id_tdo;`
105
106			`logic dr_out;`
107
108			`// TDO registers`
109			`//------------------------------------------------------------------------------`
110
111			`// TDO enable register`
112			`logic tdo_en_ff;`
113			`logic tdo_en_next;`
114
115			`// TDO output register`
116			`logic tdo_out_ff;`
117			`logic tdo_out_next;`
118
119			`//------------------------------------------------------------------------------`
120			`// TAPC Synchronous Reset logic`
121			`//------------------------------------------------------------------------------`
122
123			`always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin`
124			`if (~tapc_trst_n) begin`
125			`trst_n_int <= 1'b0;`
126			`end else begin`
127			`trst_n_int <= ~tap_fsm_reset;`
128			`end`
129			`end`
130
131			`//------------------------------------------------------------------------------`
132			`// TAP's FSM`
133			`//------------------------------------------------------------------------------`
134
135			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
136			`if (~tapc_trst_n) begin`
137			`tap_fsm_ff <= SCR1_TAP_STATE_RESET;`
138			`end else begin`
139			`tap_fsm_ff <= tap_fsm_next;`
140			`end`
141			`end`
142
143			`always_comb begin`
144			`case (tap_fsm_ff)`
145			`SCR1_TAP_STATE_RESET : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET : SCR1_TAP_STATE_IDLE;`
146			`SCR1_TAP_STATE_IDLE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;`
147			`SCR1_TAP_STATE_DR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_SEL_SCAN : SCR1_TAP_STATE_DR_CAPTURE;`
148			`SCR1_TAP_STATE_DR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1 : SCR1_TAP_STATE_DR_SHIFT;`
149			`SCR1_TAP_STATE_DR_SHIFT : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT1 : SCR1_TAP_STATE_DR_SHIFT;`
150			`SCR1_TAP_STATE_DR_EXIT1 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE : SCR1_TAP_STATE_DR_PAUSE;`
151			`SCR1_TAP_STATE_DR_PAUSE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_EXIT2 : SCR1_TAP_STATE_DR_PAUSE;`
152			`SCR1_TAP_STATE_DR_EXIT2 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_UPDATE : SCR1_TAP_STATE_DR_SHIFT;`
153			`SCR1_TAP_STATE_DR_UPDATE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;`
154			`SCR1_TAP_STATE_IR_SEL_SCAN: tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_RESET : SCR1_TAP_STATE_IR_CAPTURE;`
155			`SCR1_TAP_STATE_IR_CAPTURE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1 : SCR1_TAP_STATE_IR_SHIFT;`
156			`SCR1_TAP_STATE_IR_SHIFT : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT1 : SCR1_TAP_STATE_IR_SHIFT;`
157			`SCR1_TAP_STATE_IR_EXIT1 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE : SCR1_TAP_STATE_IR_PAUSE;`
158			`SCR1_TAP_STATE_IR_PAUSE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_EXIT2 : SCR1_TAP_STATE_IR_PAUSE;`
159			`SCR1_TAP_STATE_IR_EXIT2 : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_IR_UPDATE : SCR1_TAP_STATE_IR_SHIFT;`
160			`SCR1_TAP_STATE_IR_UPDATE : tap_fsm_next = tapc_tms ? SCR1_TAP_STATE_DR_SEL_SCAN : SCR1_TAP_STATE_IDLE;`
161			`ifdef SCR1_XPROP_EN
162			`default : tap_fsm_next = SCR1_TAP_STATE_XXX;`
163			`else // SCR1_XPROP_EN
164			`default : tap_fsm_next = tap_fsm_ff;`
165			`endif // SCR1_XPROP_EN
166			`endcase`
167			`end`
168
169			`assign tap_fsm_reset = (tap_fsm_ff == SCR1_TAP_STATE_RESET);`
170			`assign tap_fsm_ir_upd = (tap_fsm_ff == SCR1_TAP_STATE_IR_UPDATE);`
171			`assign tap_fsm_ir_cap = (tap_fsm_ff == SCR1_TAP_STATE_IR_CAPTURE);`
172			`assign tap_fsm_ir_shft = (tap_fsm_ff == SCR1_TAP_STATE_IR_SHIFT);`
173
174			`//------------------------------------------------------------------------------`
175			`// TAPC Instruction Registers`
176			`//------------------------------------------------------------------------------`
177
178			`// TAPC Instruction Shift register`
179			`//------------------------------------------------------------------------------`
180
181			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
182			`if (~tapc_trst_n) begin`
183			`tap_ir_shift_ff <= '0;`
184			`end else if (~trst_n_int) begin`
185			`tap_ir_shift_ff <= '0;`
186			`end else begin`
187			`tap_ir_shift_ff <= tap_ir_shift_next;`
188			`end`
189			`end`
190
191			`assign tap_ir_shift_next = tap_fsm_ir_cap ? {{($bits(tap_ir_shift_ff)-1){1'b0}}, 1'b1}`
192			`: tap_fsm_ir_shft ? {tapc_tdi, tap_ir_shift_ff[$left(tap_ir_shift_ff):1]}`
193			`: tap_ir_shift_ff;`
194
195			`// TAPC Instruction register`
196			`//------------------------------------------------------------------------------`
197
198			`always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin`
199			`if (~tapc_trst_n) begin`
200			`tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;`
201			`end else if (~trst_n_int) begin`
202			`tap_ir_ff <= SCR1_TAP_INSTR_IDCODE;`
203			`end else begin`
204			`tap_ir_ff <= tap_ir_next;`
205			`end`
206			`end`
207
208			`assign tap_ir_next = tap_fsm_ir_upd ? tap_ir_shift_ff : tap_ir_ff;`
209
210			`//------------------------------------------------------------------------------`
211			`// Control signals`
212			`//------------------------------------------------------------------------------`
213
214			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
215			`if (~tapc_trst_n) begin`
216			`tap_fsm_ir_shift_ff <= 1'b0;`
217			`end else if (~trst_n_int) begin`
218			`tap_fsm_ir_shift_ff <= 1'b0;`
219			`end else begin`
220			`tap_fsm_ir_shift_ff <= tap_fsm_ir_shift_next;`
221			`end`
222			`end`
223
224			`assign tap_fsm_ir_shift_next = (tap_fsm_next == SCR1_TAP_STATE_IR_SHIFT);`
225
226			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
227			`if (~tapc_trst_n) begin`
228			`tap_fsm_dr_capture_ff <= 1'b0;`
229			`end else if (~trst_n_int) begin`
230			`tap_fsm_dr_capture_ff <= 1'b0;`
231			`end else begin`
232			`tap_fsm_dr_capture_ff <= tap_fsm_dr_capture_next;`
233			`end`
234			`end`
235
236			`assign tap_fsm_dr_capture_next = (tap_fsm_next == SCR1_TAP_STATE_DR_CAPTURE);`
237
238			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
239			`if (~tapc_trst_n) begin`
240			`tap_fsm_dr_shift_ff <= 1'b0;`
241			`end else if (~trst_n_int) begin`
242			`tap_fsm_dr_shift_ff <= 1'b0;`
243			`end else begin`
244			`tap_fsm_dr_shift_ff <= tap_fsm_dr_shift_next;`
245			`end`
246			`end`
247
248			`assign tap_fsm_dr_shift_next = (tap_fsm_next == SCR1_TAP_STATE_DR_SHIFT);`
249
250			`always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin`
251			`if (~tapc_trst_n) begin`
252			`tap_fsm_dr_update_ff <= 1'b0;`
253			`end else if (~trst_n_int) begin`
254			`tap_fsm_dr_update_ff <= 1'b0;`
255			`end else begin`
256			`tap_fsm_dr_update_ff <= tap_fsm_dr_update_next;`
257			`end`
258			`end`
259
260			`assign tap_fsm_dr_update_next = (tap_fsm_next == SCR1_TAP_STATE_DR_UPDATE);`
261
262			`//------------------------------------------------------------------------------`
263			`// TAPC DRs/DMI/SCU scan-chains`
264			`//------------------------------------------------------------------------------`
265			`//`
266			`// Consists of the following functional units:`
267			`// - Data source/destination decoder`
268			`// - DMI channel ID decoder`
269
270			`// - Read data multiplexer`
271			`// Data source/destination decoder`
272			`//------------------------------------------------------------------------------`
273
274			`always_comb begin`
275			`dr_bypass_sel = 1'b0;`
276			`dr_idcode_sel = 1'b0;`
277			`dr_bld_id_sel = 1'b0;`
278			`tapc2tapcsync_scu_ch_sel_o = 1'b0;`
279			`tapc2tapcsync_dmi_ch_sel_o = 1'b0;`
280			`case (tap_ir_ff)`
281			`SCR1_TAP_INSTR_DTMCS : tapc2tapcsync_dmi_ch_sel_o = 1'b1;`
282			`SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_dmi_ch_sel_o = 1'b1;`
283			`SCR1_TAP_INSTR_IDCODE : dr_idcode_sel = 1'b1;`
284			`SCR1_TAP_INSTR_BYPASS : dr_bypass_sel = 1'b1;`
285			`SCR1_TAP_INSTR_BLD_ID : dr_bld_id_sel = 1'b1;`
286			`SCR1_TAP_INSTR_SCU_ACCESS: tapc2tapcsync_scu_ch_sel_o = 1'b1;`
287			`default : dr_bypass_sel = 1'b1;`
288			`endcase`
289			`end`
290
291			`// DMI channel ID decoder`
292			`//------------------------------------------------------------------------------`
293
294			`always_comb begin`
295			`tapc2tapcsync_ch_id_o = '0;`
296			`case (tap_ir_ff)`
297			`SCR1_TAP_INSTR_DTMCS : tapc2tapcsync_ch_id_o = 'd1;`
298			`SCR1_TAP_INSTR_DMI_ACCESS: tapc2tapcsync_ch_id_o = 'd2;`
299			`default : tapc2tapcsync_ch_id_o = '0;`
300			`endcase`
301			`end`
302
303			`// Read data multiplexer`
304			`//------------------------------------------------------------------------------`
305
306			`always_comb begin`
307			`dr_out = 1'b0;`
308			`case (tap_ir_ff)`
309			`SCR1_TAP_INSTR_DTMCS : dr_out = tapcsync2tapc_ch_tdo_i;`
310			`SCR1_TAP_INSTR_DMI_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;`
311			`SCR1_TAP_INSTR_IDCODE : dr_out = dr_idcode_tdo;`
312			`SCR1_TAP_INSTR_BYPASS : dr_out = dr_bypass_tdo;`
313			`SCR1_TAP_INSTR_BLD_ID : dr_out = dr_bld_id_tdo;`
314			`SCR1_TAP_INSTR_SCU_ACCESS: dr_out = tapcsync2tapc_ch_tdo_i;`
315			`default : dr_out = dr_bypass_tdo;`
316			`endcase`
317			`end`
318
319			`//------------------------------------------------------------------------------`
320			`// TDO enable and output registers`
321			`//------------------------------------------------------------------------------`
322
323			`// TDO enable register`
324			`//------------------------------------------------------------------------------`
325
326			`always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin`
327			`if (~tapc_trst_n) begin`
328			`tdo_en_ff <= 1'b0;`
329			`end else if (~trst_n_int) begin`
330			`tdo_en_ff <= 1'b0;`
331			`end else begin`
332			`tdo_en_ff <= tdo_en_next;`
333			`end`
334			`end`
335
336			`assign tdo_en_next = tap_fsm_dr_shift_ff \| tap_fsm_ir_shift_ff;`
337
338			`// TDO output register`
339			`//------------------------------------------------------------------------------`
340
341			`always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin`
342			`if (~tapc_trst_n) begin`
343			`tdo_out_ff <= 1'b0;`
344			`end else if (~trst_n_int) begin`
345			`tdo_out_ff <= 1'b0;`
346			`end else begin`
347			`tdo_out_ff <= tdo_out_next;`
348			`end`
349			`end`
350
351			`assign tdo_out_next = tap_fsm_dr_shift_ff ? dr_out`
352			`: tap_fsm_ir_shift_ff ? tap_ir_shift_ff[0]`
353			`: 1'b0;`
354
355			`// TAPC TDO signals`
356			`assign tapc_tdo_en = tdo_en_ff;`
357			`assign tapc_tdo = tdo_out_ff;`
358
359			`//------------------------------------------------------------------------------`
360			`// TAPC Data Registers`
361			`//------------------------------------------------------------------------------`
362			`//`
363			`// Registers:`
364			`// - BYPASS register`
365			`// - IDCODE register`
366			`// - BUILD ID register`
367
368			`// BYPASS register`
369			`//------------------------------------------------------------------------------`
370			`// 1-bit mandatory IEEE 1149.1 compliant register`
371
372			`scr1_tapc_shift_reg #(`
373			`.SCR1_WIDTH (SCR1_TAP_DR_BYPASS_WIDTH),`
374			`.SCR1_RESET_VALUE (SCR1_TAP_DR_BYPASS_WIDTH'(0))`
375			`) i_bypass_reg (`
376			`.clk (tapc_tck ),`
377			`.rst_n (tapc_trst_n ),`
378			`.rst_n_sync (trst_n_int ),`
379			`.fsm_dr_select (dr_bypass_sel ),`
380			`.fsm_dr_capture (tap_fsm_dr_capture_ff),`
381			`.fsm_dr_shift (tap_fsm_dr_shift_ff ),`
382			`.din_serial (tapc_tdi ),`
383			`.din_parallel (1'b0 ),`
384			`.dout_serial (dr_bypass_tdo ),`
385			`.dout_parallel ( )`
386			`);`
387
388			`// IDCODE register`
389			`//------------------------------------------------------------------------------`
390			`// Holds the Device ID value (mandatory IEEE 1149.1 compliant register)`
391
392			`scr1_tapc_shift_reg #(`
393			`.SCR1_WIDTH (SCR1_TAP_DR_IDCODE_WIDTH),`
394			`.SCR1_RESET_VALUE (SCR1_TAP_DR_IDCODE_WIDTH'(0))`
395			`) i_tap_idcode_reg (`
396			`.clk (tapc_tck ),`
397			`.rst_n (tapc_trst_n ),`
398			`.rst_n_sync (trst_n_int ),`
399			`.fsm_dr_select (dr_idcode_sel ),`
400			`.fsm_dr_capture (tap_fsm_dr_capture_ff ),`
401			`.fsm_dr_shift (tap_fsm_dr_shift_ff ),`
402			`.din_serial (tapc_tdi ),`
403			`.din_parallel (soc2tapc_fuse_idcode_i),`
404			`.dout_serial (dr_idcode_tdo ),`
405			`.dout_parallel ( )`
406			`);`
407
408			`// BUILD ID register`
409			`//------------------------------------------------------------------------------`
410			`// Holds the BUILD ID value`
411
412			`scr1_tapc_shift_reg #(`
413			`.SCR1_WIDTH (SCR1_TAP_DR_BLD_ID_WIDTH),`
414			`.SCR1_RESET_VALUE (SCR1_TAP_DR_BLD_ID_WIDTH'(0))`
415			`) i_tap_dr_bld_id_reg (`
416			`.clk (tapc_tck ),`
417			`.rst_n (tapc_trst_n ),`
418			`.rst_n_sync (trst_n_int ),`
419			`.fsm_dr_select (dr_bld_id_sel ),`
420			`.fsm_dr_capture (tap_fsm_dr_capture_ff),`
421			`.fsm_dr_shift (tap_fsm_dr_shift_ff ),`
422			`.din_serial (tapc_tdi ),`
423			`.din_parallel (SCR1_TAP_BLD_ID_VALUE),`
424			`.dout_serial (dr_bld_id_tdo ),`
425			`.dout_parallel ( )`
426			`);`
427
428			`//------------------------------------------------------------------------------`
429			`// DMI/SCU scan-chains signals`
430			`//------------------------------------------------------------------------------`
431
432			`assign tapc2tapcsync_ch_tdi_o = tapc_tdi;`
433			`assign tapc2tapcsync_ch_capture_o = tap_fsm_dr_capture_ff;`
434			`assign tapc2tapcsync_ch_shift_o = tap_fsm_dr_shift_ff;`
435			`assign tapc2tapcsync_ch_update_o = tap_fsm_dr_update_ff;`
436
437			`ifdef SCR1_TRGT_SIMULATION
438			`//-------------------------------------------------------------------------------`
439			`// Assertion`
440			`//-------------------------------------------------------------------------------`
441
442			`// X checks`
443			`SCR1_SVA_TAPC_XCHECK : assert property (`
444			`@(posedge tapc_tck) disable iff (~tapc_trst_n)`
445			`!$isunknown({tapc_tms, tapc_tdi})`
446			`) else $error("TAPC error: unknown values");`
447
448			`SCR1_SVA_TAPC_XCHECK_NEGCLK : assert property (`
449			`@(negedge tapc_tck) disable iff (tap_fsm_ff != SCR1_TAP_STATE_DR_SHIFT)`
450			`!$isunknown({tapcsync2tapc_ch_tdo_i})`
451			`) else $error("TAPC @negedge error: unknown values");`
452
453			`endif // SCR1_TRGT_SIMULATION
454
455			`endmodule : scr1_tapc`
456
457			`endif // SCR1_DBG_EN