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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief TAPC shift register. Parameterized implementation of JTAG TAPC's Shift Register.
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///
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`include "scr1_arch_description.svh"
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`ifdef SCR1_DBG_EN
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module scr1_tapc_shift_reg #(
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parameter int unsigned SCR1_WIDTH = 8, // Register width, bits
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parameter logic [SCR1_WIDTH-1:0] SCR1_RESET_VALUE = '0 // Register's value after reset
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) (
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input logic clk, // Clock
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input logic rst_n, // Async reset
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input logic rst_n_sync, // Sync reset
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// TAP FSM's control signals:
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input logic fsm_dr_select, // - for this DR selection (operation enabling);
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input logic fsm_dr_capture, // - to capture parallel input's data into shift register;
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input logic fsm_dr_shift, // - to enable data shifting;
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// Inputs:
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input logic din_serial, // - serial (shift_reg[msb/SCR1_WIDTH]);
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input logic [SCR1_WIDTH-1:0] din_parallel, // - parallel (shift register's input).
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// Outputs:
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output logic dout_serial, // - serial (shift_reg[0]);
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output logic [SCR1_WIDTH-1:0] dout_parallel // - parallel (shift register's output).
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);
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//-------------------------------------------------------------------------------
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// Local signals declaration
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//-------------------------------------------------------------------------------
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logic [SCR1_WIDTH-1:0] shift_reg;
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//-------------------------------------------------------------------------------
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// Shift register
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//-------------------------------------------------------------------------------
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generate
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if (SCR1_WIDTH > 1)
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begin : dr_shift_reg
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (~rst_n) begin
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shift_reg <= SCR1_RESET_VALUE;
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end
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else if (~rst_n_sync) begin
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shift_reg <= SCR1_RESET_VALUE;
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end
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else if (fsm_dr_select & fsm_dr_capture) begin
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shift_reg <= din_parallel;
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end
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else if (fsm_dr_select & fsm_dr_shift) begin
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shift_reg <= {din_serial, shift_reg[SCR1_WIDTH-1:1]};
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end
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end
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end
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else begin : dr_shift_reg
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (~rst_n) begin
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shift_reg <= SCR1_RESET_VALUE;
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end
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else if (~rst_n_sync) begin
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shift_reg <= SCR1_RESET_VALUE;
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end
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else if (fsm_dr_select & fsm_dr_capture) begin
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shift_reg <= din_parallel;
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end
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else if (fsm_dr_select & fsm_dr_shift) begin
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shift_reg <= din_serial;
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end
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end
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end
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endgenerate
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//-------------------------------------------------------------------------------
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// Parallel output
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//-------------------------------------------------------------------------------
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assign dout_parallel = shift_reg;
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//-------------------------------------------------------------------------------
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// Serial output
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//-------------------------------------------------------------------------------
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assign dout_serial = shift_reg[0];
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`ifdef SCR1_TRGT_SIMULATION
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//-------------------------------------------------------------------------------
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// Assertion
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//-------------------------------------------------------------------------------
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// X checks
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SCR1_SVA_TAPC_SHIFTREG_XCHECK : assert property (
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@(negedge clk) disable iff (~rst_n)
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!$isunknown({
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rst_n_sync,
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fsm_dr_select,
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fsm_dr_capture,
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fsm_dr_shift,
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din_serial,
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din_parallel
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})
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) else begin
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$error("TAPC Shift Reg error: unknown values");
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end
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`endif // SCR1_TRGT_SIMULATION
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endmodule : scr1_tapc_shift_reg
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`endif // SCR1_DBG_EN
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