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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [core/] [scr1_tapc_synchronizer.sv] - Blame information for rev 11

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1 11 dinesha 
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief      TAPC clock domain crossing synchronizer
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///
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`include "scr1_arch_description.svh"
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`ifdef SCR1_DBG_EN
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`include "scr1_tapc.svh"
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`include "scr1_dm.svh"
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module scr1_tapc_synchronizer (
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    // System common signals
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    input   logic                                   pwrup_rst_n,                // Power-Up Reset
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    input   logic                                   dm_rst_n,                   // Debug Module Reset
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    input   logic                                   clk,                        // System Clock (SysCLK)
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    // JTAG common signals
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    input   logic                                   tapc_trst_n,                // JTAG Test Reset (TRSTn)
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    input   logic                                   tapc_tck,                   // JTAG Test Clock (TCK)
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    // DMI/SCU scan-chains
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    input  logic                                    tapc2tapcsync_scu_ch_sel_i, // SCU Chain Select input  (TCK domain)
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    output logic                                    tapcsync2scu_ch_sel_o,      // SCU Chain Select output (SysCLK domain)
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    input  logic                                    tapc2tapcsync_dmi_ch_sel_i, // DMI Chain Select input  (TCK domain)
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    output logic                                    tapcsync2dmi_ch_sel_o,      // DMI Chain Select output (SysCLK domain)
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    input  logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]     tapc2tapcsync_ch_id_i,      // DMI/SCU Chain Identifier input  (TCK domain)
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    output logic [SCR1_DBG_DMI_CH_ID_WIDTH-1:0]     tapcsync2core_ch_id_o,      // DMI/SCU Chain Identifier output (SysCLK domain)
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    input  logic                                    tapc2tapcsync_ch_capture_i, // DMI/SCU Chain Capture input  (TCK domain)
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    output logic                                    tapcsync2core_ch_capture_o, // DMI/SCU Chain Capture output (SysCLK domain)
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    input  logic                                    tapc2tapcsync_ch_shift_i,   // DMI/SCU Chain Shift input  (TCK domain)
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    output logic                                    tapcsync2core_ch_shift_o,   // DMI/SCU Chain Shift output (SysCLK domain)
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    input  logic                                    tapc2tapcsync_ch_update_i,  // DMI/SCU Chain Update input  (TCK domain)
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    output logic                                    tapcsync2core_ch_update_o,  // DMI/SCU Chain Update output (SysCLK domain)
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    input  logic                                    tapc2tapcsync_ch_tdi_i,     // DMI/SCU Chain TDI input  (TCK domain)
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    output logic                                    tapcsync2core_ch_tdi_o,     // DMI/SCU Chain TDI output (SysCLK domain)
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    output logic                                    tapc2tapcsync_ch_tdo_i,     // DMI/SCU Chain TDO output (TCK domain)
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    input  logic                                    tapcsync2core_ch_tdo_o      // DMI/SCU Chain TDO input  (SysCLK domain)
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);
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//-------------------------------------------------------------------------------
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// Local signals declaration
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//-------------------------------------------------------------------------------
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logic           tck_divpos;
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logic           tck_divneg;
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logic           tck_rise_load;
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logic           tck_rise_reset;
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logic           tck_fall_load;
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logic           tck_fall_reset;
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logic [3:0]     tck_divpos_sync;
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logic [3:0]     tck_divneg_sync;
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logic [2:0]     dmi_ch_capture_sync;
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logic [2:0]     dmi_ch_shift_sync;
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logic [2:0]     dmi_ch_tdi_sync;
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//-------------------------------------------------------------------------------
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// Logic
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//-------------------------------------------------------------------------------
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always_ff @(posedge tapc_tck, negedge tapc_trst_n) begin
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    if (~tapc_trst_n) begin
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        tck_divpos      <= 1'b0;
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    end else begin
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        tck_divpos      <= ~tck_divpos;
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    end
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end
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always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
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    if (~tapc_trst_n) begin
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        tck_divneg      <= 1'b0;
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    end else begin
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        tck_divneg      <= ~tck_divneg;
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    end
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end
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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        tck_divpos_sync <= 4'd0;
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        tck_divneg_sync <= 4'd0;
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    end else begin
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        tck_divpos_sync <= {tck_divpos_sync[2:0], tck_divpos};
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        tck_divneg_sync <= {tck_divneg_sync[2:0], tck_divneg};
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    end
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end
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assign tck_rise_load  = tck_divpos_sync[2] ^ tck_divpos_sync[1];
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assign tck_rise_reset = tck_divpos_sync[3] ^ tck_divpos_sync[2];
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assign tck_fall_load  = tck_divneg_sync[2] ^ tck_divneg_sync[1];
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assign tck_fall_reset = tck_divneg_sync[3] ^ tck_divneg_sync[2];
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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            tapcsync2core_ch_update_o   <= '0;
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    end else begin
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        if  (tck_fall_load) begin
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            tapcsync2core_ch_update_o   <= tapc2tapcsync_ch_update_i;
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        end else if (tck_fall_reset) begin
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            tapcsync2core_ch_update_o   <= '0;
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        end
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    end
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end
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always_ff @(negedge tapc_tck, negedge tapc_trst_n) begin
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    if (~tapc_trst_n) begin
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        dmi_ch_capture_sync[0] <= '0;
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        dmi_ch_shift_sync[0]   <= '0;
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    end else begin
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        dmi_ch_capture_sync[0] <= tapc2tapcsync_ch_capture_i;
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        dmi_ch_shift_sync[0]   <= tapc2tapcsync_ch_shift_i;
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    end
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end
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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        dmi_ch_capture_sync[2:1] <= '0;
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        dmi_ch_shift_sync[2:1]   <= '0;
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    end else begin
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        dmi_ch_capture_sync[2:1] <= {dmi_ch_capture_sync[1], dmi_ch_capture_sync[0]};
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        dmi_ch_shift_sync[2:1]   <= {dmi_ch_shift_sync[1], dmi_ch_shift_sync[0]};
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    end
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end
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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        dmi_ch_tdi_sync     <= '0;
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    end else begin
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        dmi_ch_tdi_sync     <= {dmi_ch_tdi_sync[1:0], tapc2tapcsync_ch_tdi_i};
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    end
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end
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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            tapcsync2core_ch_capture_o <= '0;
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            tapcsync2core_ch_shift_o   <= '0;
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            tapcsync2core_ch_tdi_o     <= '0;
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    end else begin
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        if (tck_rise_load) begin
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            tapcsync2core_ch_capture_o <= dmi_ch_capture_sync[2];
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            tapcsync2core_ch_shift_o   <= dmi_ch_shift_sync[2];
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            tapcsync2core_ch_tdi_o     <= dmi_ch_tdi_sync[2];
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        end else if (tck_rise_reset) begin
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            tapcsync2core_ch_capture_o <= '0;
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            tapcsync2core_ch_shift_o   <= '0;
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            tapcsync2core_ch_tdi_o     <= '0;
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        end
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    end
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end
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always_ff @(posedge clk, negedge dm_rst_n) begin
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    if (~dm_rst_n) begin
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            tapcsync2dmi_ch_sel_o     <= '0;
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            tapcsync2core_ch_id_o      <= '0;
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    end else begin
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        if (tck_rise_load) begin
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            tapcsync2dmi_ch_sel_o     <= tapc2tapcsync_dmi_ch_sel_i;
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            tapcsync2core_ch_id_o      <= tapc2tapcsync_ch_id_i;
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        end
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    end
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end
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always_ff @(posedge clk, negedge pwrup_rst_n) begin
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    if (~pwrup_rst_n) begin
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            tapcsync2scu_ch_sel_o     <= '0;
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    end else begin
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        if (tck_rise_load) begin
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            tapcsync2scu_ch_sel_o     <= tapc2tapcsync_scu_ch_sel_i;
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        end
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    end
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end
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assign tapc2tapcsync_ch_tdo_i = tapcsync2core_ch_tdo_o;
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endmodule : scr1_tapc_synchronizer
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`endif // SCR1_DBG_EN

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