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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_csr.svh] - Blame information for rev 11

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1 11 dinesha 
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @brief      CSR mapping/description file
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///
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`ifndef SCR1_CSR_SVH
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`define SCR1_CSR_SVH
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`include "scr1_arch_description.svh"
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`include "scr1_arch_types.svh"
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`include "scr1_ipic.svh"
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`ifdef SCR1_RVE_EXT
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`define SCR1_CSR_REDUCED_CNT
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`endif // SCR1_RVE_EXT
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`ifdef SCR1_CSR_REDUCED_CNT
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`undef SCR1_MCOUNTEN_EN
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`endif // SCR1_CSR_REDUCED_CNT
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//-------------------------------------------------------------------------------
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// CSR addresses (standard)
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//-------------------------------------------------------------------------------
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// Machine Information Registers (read-only)
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MVENDORID     = 'hF11;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MARCHID       = 'hF12;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIMPID        = 'hF13;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MHARTID       = 'hF14;
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// Machine Trap Setup (read-write)
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSTATUS       = 'h300;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MISA          = 'h301;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIE           = 'h304;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVEC         = 'h305;
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// Machine Trap Handling (read-write)
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MSCRATCH      = 'h340;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MEPC          = 'h341;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCAUSE        = 'h342;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MTVAL         = 'h343;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MIP           = 'h344;
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// Machine Counters/Timers (read-write)
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`ifndef SCR1_CSR_REDUCED_CNT
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLE        = 'hB00;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRET      = 'hB02;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCYCLEH       = 'hB80;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MINSTRETH     = 'hB82;
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`endif // SCR1_CSR_REDUCED_CNT
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// Shadow Counters/Timers (read-only)
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIME          = 'hC01;
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`ifndef SCR1_CSR_REDUCED_CNT
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLE         = 'hC00;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRET       = 'hC02;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TIMEH         = 'hC81;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_CYCLEH        = 'hC80;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_INSTRETH      = 'hC82;
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`endif // SCR1_CSR_REDUCED_CNT
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`ifdef SCR1_DBG_EN
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//parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_DBGC_SCRATCH  = 'h7C8;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MBASE    = 'h7B0;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_HDU_MSPAN    = 'h004;    // must be power of 2
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`endif // SCR1_DBG_EN
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//-------------------------------------------------------------------------------
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// CSR addresses (non-standard)
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//-------------------------------------------------------------------------------
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`ifdef SCR1_MCOUNTEN_EN
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_MCOUNTEN      = 'h7E0;
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`endif // SCR1_MCOUNTEN_EN
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`ifdef SCR1_TDU_EN
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MBASE    = 'h7A0;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_MSPAN    = 'h008;    // must be power of 2
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`endif // SCR1_TDU_EN
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`ifdef SCR1_IPIC_EN
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_BASE     = 'hBF0;
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CISV     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CISV );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CICSR    = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CICSR);
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IPR      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IPR  );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ISVR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ISVR );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_EOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_EOI  );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_SOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_SOI  );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IDX      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IDX  );
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parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ICSR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ICSR );
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`endif // SCR1_IPIC_EN
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//-------------------------------------------------------------------------------
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// CSR definitions
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//-------------------------------------------------------------------------------
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// General
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parameter bit [`SCR1_XLEN-1:0] SCR1_RST_VECTOR      = SCR1_ARCH_RST_VECTOR;
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// Reset values TBD
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parameter bit SCR1_CSR_MIE_MSIE_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MIE_MTIE_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MIE_MEIE_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MIP_MSIP_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MIP_MTIP_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MIP_MEIP_RST_VAL             = 1'b0;
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parameter bit SCR1_CSR_MSTATUS_MIE_RST_VAL          = 1'b0;
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parameter bit SCR1_CSR_MSTATUS_MPIE_RST_VAL         = 1'b1;
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// MISA
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`define SCR1_RVC_ENC                                `SCR1_XLEN'h0004
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`define SCR1_RVE_ENC                                `SCR1_XLEN'h0010
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`define SCR1_RVI_ENC                                `SCR1_XLEN'h0100
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`define SCR1_RVM_ENC                                `SCR1_XLEN'h1000
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parameter bit [1:0]             SCR1_MISA_MXL_32    = 2'd1;
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parameter bit [`SCR1_XLEN-1:0]  SCR1_CSR_MISA       = (SCR1_MISA_MXL_32 << (`SCR1_XLEN-2))
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`ifndef SCR1_RVE_EXT
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                                                    | `SCR1_RVI_ENC
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`else // SCR1_RVE_EXT
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                                                    | `SCR1_RVE_ENC
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`endif // SCR1_RVE_EXT
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`ifdef SCR1_RVC_EXT
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                                                    | `SCR1_RVC_ENC
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`endif // SCR1_RVC_EXT
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`ifdef SCR1_RVM_EXT
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                                                    | `SCR1_RVM_ENC
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`endif // SCR1_RVM_EXT
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                                                    ;
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// MVENDORID
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parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MVENDORID   = `SCR1_MVENDORID;
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// MARCHID
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parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MARCHID     = `SCR1_XLEN'd8;
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// MIMPID
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parameter bit [`SCR1_XLEN-1:0] SCR1_CSR_MIMPID      = `SCR1_MIMPID;
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// MSTATUS
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parameter bit [1:0] SCR1_CSR_MSTATUS_MPP            = 2'b11;
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parameter int unsigned SCR1_CSR_MSTATUS_MIE_OFFSET  = 3;
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parameter int unsigned SCR1_CSR_MSTATUS_MPIE_OFFSET = 7;
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parameter int unsigned SCR1_CSR_MSTATUS_MPP_OFFSET  = 11;
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// MTVEC
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// bits [5:0] are always zero
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parameter bit [`SCR1_XLEN-1:SCR1_CSR_MTVEC_BASE_ZERO_BITS] SCR1_CSR_MTVEC_BASE_RST_VAL  = SCR1_CSR_MTVEC_BASE_WR_RST_VAL;
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parameter bit SCR1_CSR_MTVEC_MODE_DIRECT            = 1'b0;
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`ifdef SCR1_MTVEC_MODE_EN
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parameter bit SCR1_CSR_MTVEC_MODE_VECTORED          = 1'b1;
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`endif // SCR1_MTVEC_MODE_EN
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// MIE, MIP
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parameter int unsigned SCR1_CSR_MIE_MSIE_OFFSET     = 3;
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parameter int unsigned SCR1_CSR_MIE_MTIE_OFFSET     = 7;
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parameter int unsigned SCR1_CSR_MIE_MEIE_OFFSET     = 11;
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`ifdef SCR1_MCOUNTEN_EN
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// MCOUNTEN
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parameter int unsigned SCR1_CSR_MCOUNTEN_CY_OFFSET  = 0;
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parameter int unsigned SCR1_CSR_MCOUNTEN_IR_OFFSET  = 2;
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`endif // SCR1_MCOUNTEN_EN
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// MCAUSE
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typedef logic [`SCR1_XLEN-2:0]      type_scr1_csr_mcause_ec_v;
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// MCYCLE, MINSTRET
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`ifdef SCR1_CSR_REDUCED_CNT
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parameter int unsigned SCR1_CSR_COUNTERS_WIDTH      = 32;
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`else // ~SCR1_CSR_REDUCED_CNT
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parameter int unsigned SCR1_CSR_COUNTERS_WIDTH      = 64;
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`endif // ~SCR1_CSR_REDUCED_CNT
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// HPM
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parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTER_MASK   = 7'b1100000;
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parameter bit [6:0] SCR1_CSR_ADDR_HPMCOUNTERH_MASK  = 7'b1100100;
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parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTER_MASK  = 7'b1011000;
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parameter bit [6:0] SCR1_CSR_ADDR_MHPMCOUNTERH_MASK = 7'b1011100;
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parameter bit [6:0] SCR1_CSR_ADDR_MHPMEVENT_MASK    = 7'b0011001;
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//-------------------------------------------------------------------------------
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// Types declaration
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//-------------------------------------------------------------------------------
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typedef enum logic {
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    SCR1_CSR_RESP_OK,
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    SCR1_CSR_RESP_ER
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`ifdef SCR1_XPROP_EN
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    ,
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    SCR1_CSR_RESP_ERROR = 'x
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`endif // SCR1_XPROP_EN
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} type_scr1_csr_resp_e;
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`endif // SCR1_CSR_SVH

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