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dinesha |
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @brief IPIC header file
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///
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`ifndef SCR1_IPIC_SVH
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`define SCR1_IPIC_SVH
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`include "scr1_arch_description.svh"
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`ifdef SCR1_IPIC_EN
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//-------------------------------------------------------------------------------
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// Parameters declaration
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//-------------------------------------------------------------------------------
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parameter SCR1_IRQ_VECT_NUM = 16; // must be power of 2 in the current implementation
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parameter SCR1_IRQ_VECT_WIDTH = $clog2(SCR1_IRQ_VECT_NUM+1);
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parameter SCR1_IRQ_LINES_NUM = SCR1_IRQ_VECT_NUM;
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parameter SCR1_IRQ_LINES_WIDTH = $clog2(SCR1_IRQ_LINES_NUM);
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parameter logic [SCR1_IRQ_VECT_WIDTH-1:0] SCR1_IRQ_VOID_VECT_NUM = SCR1_IRQ_VECT_WIDTH'(SCR1_IRQ_VECT_NUM);
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parameter SCR1_IRQ_IDX_WIDTH = $clog2(SCR1_IRQ_VECT_NUM);
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// Address decoding parameters
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parameter logic [2:0] SCR1_IPIC_CISV = 3'h0; // RO
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parameter logic [2:0] SCR1_IPIC_CICSR = 3'h1; // {IP, IE}
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parameter logic [2:0] SCR1_IPIC_IPR = 3'h2; // RW1C
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parameter logic [2:0] SCR1_IPIC_ISVR = 3'h3; // RO
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parameter logic [2:0] SCR1_IPIC_EOI = 3'h4; // RZW
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parameter logic [2:0] SCR1_IPIC_SOI = 3'h5; // RZW
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parameter logic [2:0] SCR1_IPIC_IDX = 3'h6; // RW
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parameter logic [2:0] SCR1_IPIC_ICSR = 3'h7; // RW
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parameter SCR1_IPIC_ICSR_IP = 0;
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parameter SCR1_IPIC_ICSR_IE = 1;
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parameter SCR1_IPIC_ICSR_IM = 2;
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parameter SCR1_IPIC_ICSR_INV = 3;
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parameter SCR1_IPIC_ICSR_IS = 4;
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parameter SCR1_IPIC_ICSR_PRV_LSB = 8;
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parameter SCR1_IPIC_ICSR_PRV_MSB = 9;
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parameter SCR1_IPIC_ICSR_LN_LSB = 12;
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parameter SCR1_IPIC_ICSR_LN_MSB = SCR1_IPIC_ICSR_LN_LSB
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+ SCR1_IRQ_LINES_WIDTH;
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parameter logic [1:0] SCR1_IPIC_PRV_M = 2'b11;
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//-------------------------------------------------------------------------------
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// Types declaration
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//-------------------------------------------------------------------------------
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typedef enum logic {
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SCR1_CSR2IPIC_RD,
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SCR1_CSR2IPIC_WR
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`ifdef SCR1_XPROP_EN
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,
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SCR1_CSR2IPIC_ERROR = 'x
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`endif // SCR1_XPROP_EN
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} type_scr1_csr2ipic_wr_e;
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`endif // SCR1_IPIC_EN
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`endif // SCR1_IPIC_SVH
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