URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_memif.svh] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log


/// Copyright by Syntacore LLC � 2016-2021. See LICENSE for details
/// @file       
/// @brief      Memory interface definitions file
///
 
`ifndef SCR1_MEMIF_SVH
`define SCR1_MEMIF_SVH
 
`include "scr1_arch_description.svh"
 
//-------------------------------------------------------------------------------
// Memory command enum
//-------------------------------------------------------------------------------
typedef enum logic {
    SCR1_MEM_CMD_RD     = 1'b0,
    SCR1_MEM_CMD_WR     = 1'b1
`ifdef SCR1_XPROP_EN
    ,
    SCR1_MEM_CMD_ERROR  = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_cmd_e;
 
//-------------------------------------------------------------------------------
// Memory data width enum
//-------------------------------------------------------------------------------
typedef enum logic[1:0] {
    SCR1_MEM_WIDTH_BYTE     = 2'b00,
    SCR1_MEM_WIDTH_HWORD    = 2'b01,
    SCR1_MEM_WIDTH_WORD     = 2'b10
`ifdef SCR1_XPROP_EN
    ,
    SCR1_MEM_WIDTH_ERROR    = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_width_e;
 
//-------------------------------------------------------------------------------
// Memory response enum
//-------------------------------------------------------------------------------
typedef enum logic[1:0] {
    SCR1_MEM_RESP_NOTRDY    = 2'b00,
    SCR1_MEM_RESP_RDY_OK    = 2'b01,
    SCR1_MEM_RESP_RDY_ER    = 2'b10
`ifdef SCR1_XPROP_EN
    ,
    SCR1_MEM_RESP_ERROR     = 'x
`endif // SCR1_XPROP_EN
} type_scr1_mem_resp_e;
 
`endif // SCR1_MEMIF_SVH

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC � 2016-2021. See LICENSE for details`
2			`/// @file`
3			`/// @brief Memory interface definitions file`
4			`///`
5
6			`ifndef SCR1_MEMIF_SVH
7			`define SCR1_MEMIF_SVH
8
9			`include "scr1_arch_description.svh"
10
11			`//-------------------------------------------------------------------------------`
12			`// Memory command enum`
13			`//-------------------------------------------------------------------------------`
14			`typedef enum logic {`
15			`SCR1_MEM_CMD_RD = 1'b0,`
16			`SCR1_MEM_CMD_WR = 1'b1`
17			`ifdef SCR1_XPROP_EN
18			`,`
19			`SCR1_MEM_CMD_ERROR = 'x`
20			`endif // SCR1_XPROP_EN
21			`} type_scr1_mem_cmd_e;`
22
23			`//-------------------------------------------------------------------------------`
24			`// Memory data width enum`
25			`//-------------------------------------------------------------------------------`
26			`typedef enum logic[1:0] {`
27			`SCR1_MEM_WIDTH_BYTE = 2'b00,`
28			`SCR1_MEM_WIDTH_HWORD = 2'b01,`
29			`SCR1_MEM_WIDTH_WORD = 2'b10`
30			`ifdef SCR1_XPROP_EN
31			`,`
32			`SCR1_MEM_WIDTH_ERROR = 'x`
33			`endif // SCR1_XPROP_EN
34			`} type_scr1_mem_width_e;`
35
36			`//-------------------------------------------------------------------------------`
37			`// Memory response enum`
38			`//-------------------------------------------------------------------------------`
39			`typedef enum logic[1:0] {`
40			`SCR1_MEM_RESP_NOTRDY = 2'b00,`
41			`SCR1_MEM_RESP_RDY_OK = 2'b01,`
42			`SCR1_MEM_RESP_RDY_ER = 2'b10`
43			`ifdef SCR1_XPROP_EN
44			`,`
45			`SCR1_MEM_RESP_ERROR = 'x`
46			`endif // SCR1_XPROP_EN
47			`} type_scr1_mem_resp_e;`
48
49			`endif // SCR1_MEMIF_SVH

Browse

Tools

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_memif.svh] - Blame information for rev 11