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dinesha |
/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details
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/// @file
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/// @brief SCU header file
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///
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`ifndef SCR1_INCLUDE_SCU_DEFS
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`define SCR1_INCLUDE_SCU_DEFS
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//`include "scr1_arch_description.svh"
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`ifdef SCR1_DBG_EN
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//==============================================================================
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// Parameters
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//==============================================================================
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localparam int unsigned SCR1_SCU_DR_SYSCTRL_OP_WIDTH = 2;
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localparam int unsigned SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH = 2;
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localparam int unsigned SCR1_SCU_DR_SYSCTRL_DATA_WIDTH = 4;
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//==============================================================================
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// Types
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//==============================================================================
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typedef enum logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] {
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SCR1_SCU_SYSCTRL_OP_WRITE = 2'h0,
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SCR1_SCU_SYSCTRL_OP_READ = 2'h1,
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SCR1_SCU_SYSCTRL_OP_SETBITS = 2'h2,
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SCR1_SCU_SYSCTRL_OP_CLRBITS = 2'h3
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`ifdef SCR1_XPROP_EN
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,
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SCR1_SCU_SYSCTRL_OP_XXX = 'X
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`endif // SCR1_XPROP_EN
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} type_scr1_scu_sysctrl_op_e;
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typedef enum logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] {
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SCR1_SCU_SYSCTRL_ADDR_CONTROL = 2'h0,
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SCR1_SCU_SYSCTRL_ADDR_MODE = 2'h1,
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SCR1_SCU_SYSCTRL_ADDR_STATUS = 2'h2,
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SCR1_SCU_SYSCTRL_ADDR_STICKY = 2'h3
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`ifdef SCR1_XPROP_EN
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,
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SCR1_SCU_SYSCTRL_ADDR_XXX = 'X
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`endif // SCR1_XPROP_EN
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} type_scr1_scu_sysctrl_addr_e;
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typedef struct packed {
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logic [SCR1_SCU_DR_SYSCTRL_DATA_WIDTH-1:0] data;
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logic [SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH-1:0] addr;
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logic [SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1:0] op;
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} type_scr1_scu_sysctrl_dr_s;
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typedef enum int unsigned {
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SCR1_SCU_DR_SYSCTRL_OP_BIT_R = 'h0,
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SCR1_SCU_DR_SYSCTRL_OP_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH-1,
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SCR1_SCU_DR_SYSCTRL_ADDR_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH,
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SCR1_SCU_DR_SYSCTRL_ADDR_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
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SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH - 1,
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SCR1_SCU_DR_SYSCTRL_DATA_BIT_R = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
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SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH,
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SCR1_SCU_DR_SYSCTRL_DATA_BIT_L = SCR1_SCU_DR_SYSCTRL_OP_WIDTH +
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SCR1_SCU_DR_SYSCTRL_ADDR_WIDTH +
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SCR1_SCU_DR_SYSCTRL_DATA_WIDTH - 1
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} type_scr1_scu_sysctrl_dr_bits_e;
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typedef struct packed {
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logic [1:0] rsrv;
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logic core_reset;
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logic sys_reset;
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} type_scr1_scu_sysctrl_control_reg_s;
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typedef struct packed {
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logic [1:0] rsrv;
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logic hdu_rst_bhv;
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logic dm_rst_bhv;
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} type_scr1_scu_sysctrl_mode_reg_s;
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typedef struct packed {
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logic hdu_reset;
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logic dm_reset;
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logic core_reset;
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logic sys_reset;
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} type_scr1_scu_sysctrl_status_reg_s;
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`endif // SCR1_DBG_EN
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`endif // SCR1_INCLUDE_SCU_DEFS
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