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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [includes/] [scr1_search_ms1.svh] - Blame information for rev 11

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1 11 dinesha
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file       
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/// @brief      Most significant one search function
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///
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`ifndef SCR1_SEARCH_MS1_SVH
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`define SCR1_SEARCH_MS1_SVH
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//-------------------------------------------------------------------------------
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// Local types declaration
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//-------------------------------------------------------------------------------
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typedef struct packed {
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    logic       vd;
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    logic       idx;
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} type_scr1_search_one_2_s;
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typedef struct packed {
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    logic           vd;
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    logic [4:0]     idx;
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} type_scr1_search_one_32_s;
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//-------------------------------------------------------------------------------
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// Leading Zeros Count Function
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//-------------------------------------------------------------------------------
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function automatic type_scr1_search_one_2_s scr1_lead_zeros_cnt_2(
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    input   logic [1:0]     din
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);
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    type_scr1_search_one_2_s tmp;
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begin
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    tmp.vd  = |din;
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    tmp.idx = ~din[1];
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    scr1_lead_zeros_cnt_2 =  tmp;
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end
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endfunction
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function automatic logic [4:0] scr1_lead_zeros_cnt_32(
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    input   logic [31:0]    din
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);
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begin
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    logic [15:0]    stage1_vd;
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    logic [7:0]     stage2_vd;
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    logic [3:0]     stage3_vd;
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    logic [1:0]     stage4_vd;
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    logic           stage1_idx [15:0];
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    logic [1:0]     stage2_idx [7:0];
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    logic [2:0]     stage3_idx [3:0];
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    logic [3:0]     stage4_idx [1:0];
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    type_scr1_search_one_32_s tmp;
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    logic [4:0]     res;
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    integer         i;
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    // Stage 1
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    for (i=0; i<16; i=i+1) begin // cp.4
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        type_scr1_search_one_2_s tmp;
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        tmp = scr1_lead_zeros_cnt_2(din[(i+1)*2-1-:2]);
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        stage1_vd[i]  = tmp.vd;
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        stage1_idx[i] = tmp.idx;
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    end
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    // Stage 2
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    for (i=0; i<8;i=i+1) begin // cp.4
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        type_scr1_search_one_2_s tmp;
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        tmp = scr1_lead_zeros_cnt_2(stage1_vd[(i+1)*2-1-:2]);
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        stage2_vd[i]  = tmp.vd;
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        stage2_idx[i] = (tmp.idx) ? {tmp.idx, stage1_idx[2*i]} : {tmp.idx, stage1_idx[2*i+1]};
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    end
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    // Stage 3
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    for (i=0; i<4; i=i+1) begin // cp.4
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        type_scr1_search_one_2_s tmp;
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        tmp = scr1_lead_zeros_cnt_2(stage2_vd[(i+1)*2-1-:2]);
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        stage3_vd[i]  = tmp.vd;
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        stage3_idx[i] = (tmp.idx) ? {tmp.idx, stage2_idx[2*i]} : {tmp.idx, stage2_idx[2*i+1]};
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    end
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    // Stage 4
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    for (i=0; i<2; i=i+1) begin // cp.4
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        type_scr1_search_one_2_s tmp;
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        tmp = scr1_lead_zeros_cnt_2(stage3_vd[(i+1)*2-1-:2]);
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        stage4_vd[i]  = tmp.vd;
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        stage4_idx[i] = (tmp.idx) ? {tmp.idx, stage3_idx[2*i]} : {tmp.idx, stage3_idx[2*i+1]};
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    end
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    // Stage 5
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    tmp.vd = |stage4_vd;
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    tmp.idx = (stage4_vd[1]) ? {1'b0, stage4_idx[1]} : {1'b1, stage4_idx[0]};
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    res = tmp.idx;
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    scr1_lead_zeros_cnt_32 = res;
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end
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endfunction
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`endif // SCR1_SEARCH_MS1_SVH

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