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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
/// @file       
/// @brief      Dual-port synchronous memory with byte enable inputs
///
 
`include "scr1_arch_description.svh"
 
`ifdef SCR1_TCM_EN
module scr1_dp_memory
#(
    parameter SCR1_WIDTH    = 32,
    parameter SCR1_SIZE     = `SCR1_IMEM_AWIDTH'h00010000,
    parameter SCR1_NBYTES   = SCR1_WIDTH / 8
)
(
    input   logic                           clk,
    // Port A
    input   logic                           rena,
    input   logic [$clog2(SCR1_SIZE)-1:2]   addra,
    output  logic [SCR1_WIDTH-1:0]          qa,
    // Port B
    input   logic                           renb,
    input   logic                           wenb,
    input   logic [SCR1_NBYTES-1:0]         webb,
    input   logic [$clog2(SCR1_SIZE)-1:2]   addrb,
    input   logic [SCR1_WIDTH-1:0]          datab,
    output  logic [SCR1_WIDTH-1:0]          qb
);
 
`ifdef SCR1_TRGT_FPGA_INTEL
//-------------------------------------------------------------------------------
// Local signal declaration
//-------------------------------------------------------------------------------
 `ifdef SCR1_TRGT_FPGA_INTEL_MAX10
(* ramstyle = "M9K" *)    logic [SCR1_NBYTES-1:0][7:0]  memory_array  [0:(SCR1_SIZE/SCR1_NBYTES)-1];
 `elsif SCR1_TRGT_FPGA_INTEL_ARRIAV
(* ramstyle = "M10K" *)   logic [SCR1_NBYTES-1:0][7:0]  memory_array  [0:(SCR1_SIZE/SCR1_NBYTES)-1];
 `endif
logic [3:0] wenbb;
//-------------------------------------------------------------------------------
// Port B memory behavioral description
//-------------------------------------------------------------------------------
assign wenbb = {4{wenb}} & webb;
always_ff @(posedge clk) begin
    if (wenb) begin
        if (wenbb[0]) begin
            memory_array[addrb][0] <= datab[0+:8];
        end
        if (wenbb[1]) begin
            memory_array[addrb][1] <= datab[8+:8];
        end
        if (wenbb[2]) begin
            memory_array[addrb][2] <= datab[16+:8];
        end
        if (wenbb[3]) begin
            memory_array[addrb][3] <= datab[24+:8];
        end
    end
    qb <= memory_array[addrb];
end
//-------------------------------------------------------------------------------
// Port A memory behavioral description
//-------------------------------------------------------------------------------
always_ff @(posedge clk) begin
    qa <= memory_array[addra];
end
 
`else // SCR1_TRGT_FPGA_INTEL
 
// CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc
 
localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;
 
//-------------------------------------------------------------------------------
// Local signal declaration
//-------------------------------------------------------------------------------
 `ifdef SCR1_TRGT_FPGA_XILINX
(* ram_style = "block" *)  logic  [SCR1_WIDTH-1:0]  ram_block  [RAM_SIZE_WORDS-1:0];
 `else  // ASIC or SIMULATION
logic  [SCR1_WIDTH-1:0]  ram_block  [RAM_SIZE_WORDS-1:0];
 `endif
//-------------------------------------------------------------------------------
// Port A memory behavioral description
//-------------------------------------------------------------------------------
always_ff @(posedge clk) begin
    if (rena) begin
        qa <= ram_block[addra];
    end
end
 
//-------------------------------------------------------------------------------
// Port B memory behavioral description
//-------------------------------------------------------------------------------
always_ff @(posedge clk) begin
    if (wenb) begin
        for (int i=0; i
            if (webb[i]) begin
                ram_block[addrb][i*8 +: 8] <= datab[i*8 +: 8];
            end
        end
    end
    if (renb) begin
        qb <= ram_block[addrb];
    end
end
 
`endif // SCR1_TRGT_FPGA_INTEL
 
endmodule : scr1_dp_memory
 
`endif // SCR1_TCM_EN

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details`
2			`/// @file`
3			`/// @brief Dual-port synchronous memory with byte enable inputs`
4			`///`
5
6			`include "scr1_arch_description.svh"
7
8			`ifdef SCR1_TCM_EN
9			`module scr1_dp_memory`
10			`#(`
11			`parameter SCR1_WIDTH = 32,`
12			parameter SCR1_SIZE = `SCR1_IMEM_AWIDTH'h00010000,
13			`parameter SCR1_NBYTES = SCR1_WIDTH / 8`
14			`)`
15			`(`
16			`input logic clk,`
17			`// Port A`
18			`input logic rena,`
19			`input logic [$clog2(SCR1_SIZE)-1:2] addra,`
20			`output logic [SCR1_WIDTH-1:0] qa,`
21			`// Port B`
22			`input logic renb,`
23			`input logic wenb,`
24			`input logic [SCR1_NBYTES-1:0] webb,`
25			`input logic [$clog2(SCR1_SIZE)-1:2] addrb,`
26			`input logic [SCR1_WIDTH-1:0] datab,`
27			`output logic [SCR1_WIDTH-1:0] qb`
28			`);`
29
30			`ifdef SCR1_TRGT_FPGA_INTEL
31			`//-------------------------------------------------------------------------------`
32			`// Local signal declaration`
33			`//-------------------------------------------------------------------------------`
34			`ifdef SCR1_TRGT_FPGA_INTEL_MAX10
35			`(* ramstyle = "M9K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];`
36			`elsif SCR1_TRGT_FPGA_INTEL_ARRIAV
37			`(* ramstyle = "M10K" *) logic [SCR1_NBYTES-1:0][7:0] memory_array [0:(SCR1_SIZE/SCR1_NBYTES)-1];`
38			`endif
39			`logic [3:0] wenbb;`
40			`//-------------------------------------------------------------------------------`
41			`// Port B memory behavioral description`
42			`//-------------------------------------------------------------------------------`
43			`assign wenbb = {4{wenb}} & webb;`
44			`always_ff @(posedge clk) begin`
45			`if (wenb) begin`
46			`if (wenbb[0]) begin`
47			`memory_array[addrb][0] <= datab[0+:8];`
48			`end`
49			`if (wenbb[1]) begin`
50			`memory_array[addrb][1] <= datab[8+:8];`
51			`end`
52			`if (wenbb[2]) begin`
53			`memory_array[addrb][2] <= datab[16+:8];`
54			`end`
55			`if (wenbb[3]) begin`
56			`memory_array[addrb][3] <= datab[24+:8];`
57			`end`
58			`end`
59			`qb <= memory_array[addrb];`
60			`end`
61			`//-------------------------------------------------------------------------------`
62			`// Port A memory behavioral description`
63			`//-------------------------------------------------------------------------------`
64			`always_ff @(posedge clk) begin`
65			`qa <= memory_array[addra];`
66			`end`
67
68			`else // SCR1_TRGT_FPGA_INTEL
69
70			`// CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc`
71
72			`localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES;`
73
74			`//-------------------------------------------------------------------------------`
75			`// Local signal declaration`
76			`//-------------------------------------------------------------------------------`
77			`ifdef SCR1_TRGT_FPGA_XILINX
78			`(* ram_style = "block" *) logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];`
79			`else // ASIC or SIMULATION
80			`logic [SCR1_WIDTH-1:0] ram_block [RAM_SIZE_WORDS-1:0];`
81			`endif
82			`//-------------------------------------------------------------------------------`
83			`// Port A memory behavioral description`
84			`//-------------------------------------------------------------------------------`
85			`always_ff @(posedge clk) begin`
86			`if (rena) begin`
87			`qa <= ram_block[addra];`
88			`end`
89			`end`
90
91			`//-------------------------------------------------------------------------------`
92			`// Port B memory behavioral description`
93			`//-------------------------------------------------------------------------------`
94			`always_ff @(posedge clk) begin`
95			`if (wenb) begin`
96			`for (int i=0; i`
97			`if (webb[i]) begin`
98			`ram_block[addrb][i8 +: 8] <= datab[i8 +: 8];`
99			`end`
100			`end`
101			`end`
102			`if (renb) begin`
103			`qb <= ram_block[addrb];`
104			`end`
105			`end`
106
107			`endif // SCR1_TRGT_FPGA_INTEL
108
109			`endmodule : scr1_dp_memory`
110
111			`endif // SCR1_TCM_EN

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_dp_memory.sv] - Blame information for rev 11