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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
/// @file       
/// @brief      SCR1 AHB top
///
 
`include "scr1_arch_description.svh"
`include "scr1_memif.svh"
`include "scr1_ahb.svh"
`ifdef SCR1_IPIC_EN
`include "scr1_ipic.svh"
`endif // SCR1_IPIC_EN
 
`ifdef SCR1_TCM_EN
 `define SCR1_IMEM_ROUTER_EN
`endif // SCR1_TCM_EN
 
module scr1_top_ahb (
    // Control
    input   logic                                   pwrup_rst_n,            // Power-Up Reset
    input   logic                                   rst_n,                  // Regular Reset signal
    input   logic                                   cpu_rst_n,              // CPU Reset (Core Reset)
    input   logic                                   test_mode,              // Test mode
    input   logic                                   test_rst_n,             // Test mode's reset
    input   logic                                   clk,                    // System clock
    input   logic                                   rtc_clk,                // Real-time clock
`ifdef SCR1_DBG_EN
    output  logic                                   sys_rst_n_o,            // External System Reset output
                                                                            //   (for the processor cluster's components or
                                                                            //    external SOC (could be useful in small
                                                                            //    SCR-core-centric SOCs))
    output  logic                                   sys_rdc_qlfy_o,         // System-to-External SOC Reset Domain Crossing Qualifier
`endif // SCR1_DBG_EN
 
    // Fuses
    input   logic [`SCR1_XLEN-1:0]                  fuse_mhartid,           // Hart ID
`ifdef SCR1_DBG_EN
    input   logic [31:0]                            fuse_idcode,            // TAPC IDCODE
`endif // SCR1_DBG_EN
 
    // IRQ
`ifdef SCR1_IPIC_EN
    input   logic [SCR1_IRQ_LINES_NUM-1:0]          irq_lines,              // IRQ lines to IPIC
`else // SCR1_IPIC_EN
    input   logic                                   ext_irq,                // External IRQ input
`endif // SCR1_IPIC_EN
    input   logic                                   soft_irq,               // Software IRQ input
 
`ifdef SCR1_DBG_EN
    // -- JTAG I/F
    input   logic                                   trst_n,
    input   logic                                   tck,
    input   logic                                   tms,
    input   logic                                   tdi,
    output  logic                                   tdo,
    output  logic                                   tdo_en,
`endif // SCR1_DBG_EN
 
    // Instruction Memory Interface
    output  logic [3:0]                             imem_hprot,
    output  logic [2:0]                             imem_hburst,
    output  logic [2:0]                             imem_hsize,
    output  logic [1:0]                             imem_htrans,
    output  logic                                   imem_hmastlock,
    output  logic [SCR1_AHB_WIDTH-1:0]              imem_haddr,
    input   logic                                   imem_hready,
    input   logic [SCR1_AHB_WIDTH-1:0]              imem_hrdata,
    input   logic                                   imem_hresp,
 
    // Data Memory Interface
    output  logic [3:0]                             dmem_hprot,
    output  logic [2:0]                             dmem_hburst,
    output  logic [2:0]                             dmem_hsize,
    output  logic [1:0]                             dmem_htrans,
    output  logic                                   dmem_hmastlock,
    output  logic [SCR1_AHB_WIDTH-1:0]              dmem_haddr,
    output  logic                                   dmem_hwrite,
    output  logic [SCR1_AHB_WIDTH-1:0]              dmem_hwdata,
    input   logic                                   dmem_hready,
    input   logic [SCR1_AHB_WIDTH-1:0]              dmem_hrdata,
    input   logic                                   dmem_hresp
);
 
//-------------------------------------------------------------------------------
// Local parameters
//-------------------------------------------------------------------------------
localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM            = 2;
 
//-------------------------------------------------------------------------------
// Local signal declaration
//-------------------------------------------------------------------------------
// Reset logic
logic                                               pwrup_rst_n_sync;
logic                                               rst_n_sync;
logic                                               cpu_rst_n_sync;
logic                                               core_rst_n_local;
`ifdef SCR1_DBG_EN
logic                                               tapc_trst_n;
`endif // SCR1_DBG_EN
 
// Instruction memory interface from core to router
logic                                               core_imem_req_ack;
logic                                               core_imem_req;
logic                                               core_imem_cmd;
logic [`SCR1_IMEM_AWIDTH-1:0]                       core_imem_addr;
logic [`SCR1_IMEM_DWIDTH-1:0]                       core_imem_rdata;
logic [1:0]                                         core_imem_resp;
 
// Data memory interface from core to router
logic                                               core_dmem_req_ack;
logic                                               core_dmem_req;
logic                                               core_dmem_cmd;
logic [1:0]                                         core_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0]                       core_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0]                       core_dmem_rdata;
logic [1:0]                                         core_dmem_resp;
 
// Instruction memory interface from router to AHB bridge
logic                                               ahb_imem_req_ack;
logic                                               ahb_imem_req;
logic                                               ahb_imem_cmd;
logic [`SCR1_IMEM_AWIDTH-1:0]                       ahb_imem_addr;
logic [`SCR1_IMEM_DWIDTH-1:0]                       ahb_imem_rdata;
logic [1:0]                                         ahb_imem_resp;
 
// Data memory interface from router to AHB bridge
logic                                               ahb_dmem_req_ack;
logic                                               ahb_dmem_req;
logic                                               ahb_dmem_cmd;
logic [1:0]                                         ahb_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0]                       ahb_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0]                       ahb_dmem_rdata;
logic [1:0]                                         ahb_dmem_resp;
 
`ifdef SCR1_TCM_EN
// Instruction memory interface from router to TCM
logic                                               tcm_imem_req_ack;
logic                                               tcm_imem_req;
logic                                               tcm_imem_cmd;
logic [`SCR1_IMEM_AWIDTH-1:0]                       tcm_imem_addr;
logic [`SCR1_IMEM_DWIDTH-1:0]                       tcm_imem_rdata;
logic [1:0]                                         tcm_imem_resp;
 
// Data memory interface from router to TCM
logic                                               tcm_dmem_req_ack;
logic                                               tcm_dmem_req;
logic                                               tcm_dmem_cmd;
logic [1:0]                                         tcm_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0]                       tcm_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0]                       tcm_dmem_rdata;
logic [1:0]                                         tcm_dmem_resp;
`endif // SCR1_TCM_EN
 
// Data memory interface from router to memory-mapped timer
logic                                               timer_dmem_req_ack;
logic                                               timer_dmem_req;
logic                                               timer_dmem_cmd;
logic [1:0]                                         timer_dmem_width;
logic [`SCR1_DMEM_AWIDTH-1:0]                       timer_dmem_addr;
logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_wdata;
logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
logic [1:0]                                         timer_dmem_resp;
 
logic                                               timer_irq;
logic [63:0]                                        timer_val;
 
 
//-------------------------------------------------------------------------------
// Reset logic
//-------------------------------------------------------------------------------
// Power-Up Reset synchronizer
scr1_reset_sync_cell #(
    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
) i_pwrup_rstn_reset_sync (
    .rst_n          (pwrup_rst_n     ),
    .clk            (clk             ),
    .test_rst_n     (test_rst_n      ),
    .test_mode      (test_mode       ),
    .rst_n_in       (1'b1            ),
    .rst_n_out      (pwrup_rst_n_sync)
);
 
// Regular Reset synchronizer
scr1_reset_sync_cell #(
    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
) i_rstn_reset_sync (
    .rst_n          (pwrup_rst_n     ),
    .clk            (clk             ),
    .test_rst_n     (test_rst_n      ),
    .test_mode      (test_mode       ),
    .rst_n_in       (rst_n           ),
    .rst_n_out      (rst_n_sync      )
);
 
// CPU Reset synchronizer
scr1_reset_sync_cell #(
    .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
) i_cpu_rstn_reset_sync (
    .rst_n          (pwrup_rst_n     ),
    .clk            (clk             ),
    .test_rst_n     (test_rst_n      ),
    .test_mode      (test_mode       ),
    .rst_n_in       (cpu_rst_n       ),
    .rst_n_out      (cpu_rst_n_sync  )
);
 
`ifdef SCR1_DBG_EN
// TAPC Reset
scr1_reset_and2_cell i_tapc_rstn_and2_cell (
    .rst_n_in       ({trst_n, pwrup_rst_n}),
    .test_rst_n     (test_rst_n      ),
    .test_mode      (test_mode       ),
    .rst_n_out      (tapc_trst_n     )
);
`endif // SCR1_DBG_EN
 
//-------------------------------------------------------------------------------
// SCR1 core instance
//-------------------------------------------------------------------------------
scr1_core_top i_core_top (
    // Common
    .pwrup_rst_n                (pwrup_rst_n_sync ),
    .rst_n                      (rst_n_sync       ),
    .cpu_rst_n                  (cpu_rst_n_sync   ),
    .test_mode                  (test_mode        ),
    .test_rst_n                 (test_rst_n       ),
    .clk                        (clk              ),
    .core_rst_n_o               (core_rst_n_local ),
    .core_rdc_qlfy_o            (                 ),
`ifdef SCR1_DBG_EN
    .sys_rst_n_o                (sys_rst_n_o      ),
    .sys_rdc_qlfy_o             (sys_rdc_qlfy_o   ),
`endif // SCR1_DBG_EN
 
    // Fuses
    .core_fuse_mhartid_i        (fuse_mhartid     ),
`ifdef SCR1_DBG_EN
    .tapc_fuse_idcode_i         (fuse_idcode      ),
`endif // SCR1_DBG_EN
 
    // IRQ
`ifdef SCR1_IPIC_EN
    .core_irq_lines_i           (irq_lines        ),
`else // SCR1_IPIC_EN
    .core_irq_ext_i             (ext_irq          ),
`endif // SCR1_IPIC_EN
    .core_irq_soft_i            (soft_irq         ),
    .core_irq_mtimer_i          (timer_irq        ),
 
    // Memory-mapped external timer
    .core_mtimer_val_i          (timer_val        ),
 
`ifdef SCR1_DBG_EN
    // Debug interface
    .tapc_trst_n                (tapc_trst_n      ),
    .tapc_tck                   (tck              ),
    .tapc_tms                   (tms              ),
    .tapc_tdi                   (tdi              ),
    .tapc_tdo                   (tdo              ),
    .tapc_tdo_en                (tdo_en           ),
`endif // SCR1_DBG_EN
 
    // Instruction memory interface
    .imem2core_req_ack_i        (core_imem_req_ack),
    .core2imem_req_o            (core_imem_req    ),
    .core2imem_cmd_o            (core_imem_cmd    ),
    .core2imem_addr_o           (core_imem_addr   ),
    .imem2core_rdata_i          (core_imem_rdata  ),
    .imem2core_resp_i           (core_imem_resp   ),
 
    // Data memory interface
    .dmem2core_req_ack_i        (core_dmem_req_ack),
    .core2dmem_req_o            (core_dmem_req    ),
    .core2dmem_cmd_o            (core_dmem_cmd    ),
    .core2dmem_width_o          (core_dmem_width  ),
    .core2dmem_addr_o           (core_dmem_addr   ),
    .core2dmem_wdata_o          (core_dmem_wdata  ),
    .dmem2core_rdata_i          (core_dmem_rdata  ),
    .dmem2core_resp_i           (core_dmem_resp   )
);
 
 
`ifdef SCR1_TCM_EN
//-------------------------------------------------------------------------------
// TCM instance
//-------------------------------------------------------------------------------
scr1_tcm #(
    .SCR1_TCM_SIZE  (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
) i_tcm (
    .clk            (clk             ),
    .rst_n          (core_rst_n_local),
 
    // Instruction interface to TCM
    .imem_req_ack   (tcm_imem_req_ack),
    .imem_req       (tcm_imem_req    ),
    .imem_addr      (tcm_imem_addr   ),
    .imem_rdata     (tcm_imem_rdata  ),
    .imem_resp      (tcm_imem_resp   ),
 
    // Data interface to TCM
    .dmem_req_ack   (tcm_dmem_req_ack),
    .dmem_req       (tcm_dmem_req    ),
    .dmem_cmd       (tcm_dmem_cmd    ),
    .dmem_width     (tcm_dmem_width  ),
    .dmem_addr      (tcm_dmem_addr   ),
    .dmem_wdata     (tcm_dmem_wdata  ),
    .dmem_rdata     (tcm_dmem_rdata  ),
    .dmem_resp      (tcm_dmem_resp   )
);
`endif // SCR1_TCM_EN
 
 
//-------------------------------------------------------------------------------
// Memory-mapped timer instance
//-------------------------------------------------------------------------------
scr1_timer i_timer (
    // Common
    .rst_n          (core_rst_n_local  ),
    .clk            (clk               ),
    .rtc_clk        (rtc_clk           ),
 
    // Memory interface
    .dmem_req       (timer_dmem_req    ),
    .dmem_cmd       (timer_dmem_cmd    ),
    .dmem_width     (timer_dmem_width  ),
    .dmem_addr      (timer_dmem_addr   ),
    .dmem_wdata     (timer_dmem_wdata  ),
    .dmem_req_ack   (timer_dmem_req_ack),
    .dmem_rdata     (timer_dmem_rdata  ),
    .dmem_resp      (timer_dmem_resp   ),
 
    // Timer interface
    .timer_val      (timer_val         ),
    .timer_irq      (timer_irq         )
);
 
 
`ifdef SCR1_IMEM_ROUTER_EN
//-------------------------------------------------------------------------------
// Instruction memory router
//-------------------------------------------------------------------------------
scr1_imem_router #(
 `ifdef SCR1_TCM_EN
    .SCR1_ADDR_MASK     (SCR1_TCM_ADDR_MASK),
    .SCR1_ADDR_PATTERN  (SCR1_TCM_ADDR_PATTERN)
 `endif // SCR1_TCM_EN
) i_imem_router (
    .rst_n          (core_rst_n_local ),
    .clk            (clk              ),
    // Interface to core
    .imem_req_ack   (core_imem_req_ack),
    .imem_req       (core_imem_req    ),
    .imem_cmd       (core_imem_cmd    ),
    .imem_addr      (core_imem_addr   ),
    .imem_rdata     (core_imem_rdata  ),
    .imem_resp      (core_imem_resp   ),
    // Interface to AHB bridge
    .port0_req_ack  (ahb_imem_req_ack ),
    .port0_req      (ahb_imem_req     ),
    .port0_cmd      (ahb_imem_cmd     ),
    .port0_addr     (ahb_imem_addr    ),
    .port0_rdata    (ahb_imem_rdata   ),
    .port0_resp     (ahb_imem_resp    ),
 `ifdef SCR1_TCM_EN
    // Interface to TCM
    .port1_req_ack  (tcm_imem_req_ack ),
    .port1_req      (tcm_imem_req     ),
    .port1_cmd      (tcm_imem_cmd     ),
    .port1_addr     (tcm_imem_addr    ),
    .port1_rdata    (tcm_imem_rdata   ),
    .port1_resp     (tcm_imem_resp    )
 `endif // SCR1_TCM_EN
);
 
`else // SCR1_IMEM_ROUTER_EN
 
assign ahb_imem_req         = core_imem_req;
assign ahb_imem_cmd         = core_imem_cmd;
assign ahb_imem_addr        = core_imem_addr;
assign core_imem_req_ack    = ahb_imem_req_ack;
assign core_imem_resp       = ahb_imem_resp;
assign core_imem_rdata      = ahb_imem_rdata;
 
`endif // SCR1_IMEM_ROUTER_EN
 
//-------------------------------------------------------------------------------
// Data memory router
//-------------------------------------------------------------------------------
scr1_dmem_router #(
 
`ifdef SCR1_TCM_EN
    .SCR1_PORT1_ADDR_MASK       (SCR1_TCM_ADDR_MASK),
    .SCR1_PORT1_ADDR_PATTERN    (SCR1_TCM_ADDR_PATTERN),
`else // SCR1_TCM_EN
    .SCR1_PORT1_ADDR_MASK       (32'h00000000),
    .SCR1_PORT1_ADDR_PATTERN    (32'hFFFFFFFF),
`endif // SCR1_TCM_EN
 
    .SCR1_PORT2_ADDR_MASK       (SCR1_TIMER_ADDR_MASK),
    .SCR1_PORT2_ADDR_PATTERN    (SCR1_TIMER_ADDR_PATTERN)
 
) i_dmem_router (
    .rst_n          (core_rst_n_local    ),
    .clk            (clk                 ),
    // Interface to core
    .dmem_req_ack   (core_dmem_req_ack   ),
    .dmem_req       (core_dmem_req       ),
    .dmem_cmd       (core_dmem_cmd       ),
    .dmem_width     (core_dmem_width     ),
    .dmem_addr      (core_dmem_addr      ),
    .dmem_wdata     (core_dmem_wdata     ),
    .dmem_rdata     (core_dmem_rdata     ),
    .dmem_resp      (core_dmem_resp      ),
`ifdef SCR1_TCM_EN
    // Interface to TCM
    .port1_req_ack  (tcm_dmem_req_ack    ),
    .port1_req      (tcm_dmem_req        ),
    .port1_cmd      (tcm_dmem_cmd        ),
    .port1_width    (tcm_dmem_width      ),
    .port1_addr     (tcm_dmem_addr       ),
    .port1_wdata    (tcm_dmem_wdata      ),
    .port1_rdata    (tcm_dmem_rdata      ),
    .port1_resp     (tcm_dmem_resp       ),
`else // SCR1_TCM_EN
    .port1_req_ack  (1'b0),
    .port1_req      (                    ),
    .port1_cmd      (                    ),
    .port1_width    (                    ),
    .port1_addr     (                    ),
    .port1_wdata    (                    ),
    .port1_rdata    ('0                  ),
    .port1_resp     (SCR1_MEM_RESP_RDY_ER),
`endif // SCR1_TCM_EN
    // Interface to memory-mapped timer
    .port2_req_ack  (timer_dmem_req_ack  ),
    .port2_req      (timer_dmem_req      ),
    .port2_cmd      (timer_dmem_cmd      ),
    .port2_width    (timer_dmem_width    ),
    .port2_addr     (timer_dmem_addr     ),
    .port2_wdata    (timer_dmem_wdata    ),
    .port2_rdata    (timer_dmem_rdata    ),
    .port2_resp     (timer_dmem_resp     ),
    // Interface to AHB bridge
    .port0_req_ack  (ahb_dmem_req_ack    ),
    .port0_req      (ahb_dmem_req        ),
    .port0_cmd      (ahb_dmem_cmd        ),
    .port0_width    (ahb_dmem_width      ),
    .port0_addr     (ahb_dmem_addr       ),
    .port0_wdata    (ahb_dmem_wdata      ),
    .port0_rdata    (ahb_dmem_rdata      ),
    .port0_resp     (ahb_dmem_resp       )
);
 
 
//-------------------------------------------------------------------------------
// Instruction memory AHB bridge
//-------------------------------------------------------------------------------
scr1_imem_ahb i_imem_ahb (
    .rst_n          (core_rst_n_local   ),
    .clk            (clk                ),
    // Interface to imem router
    .imem_req_ack   (ahb_imem_req_ack   ),
    .imem_req       (ahb_imem_req       ),
    .imem_addr      (ahb_imem_addr      ),
    .imem_rdata     (ahb_imem_rdata     ),
    .imem_resp      (ahb_imem_resp      ),
    // AHB interface
    .hprot          (imem_hprot         ),
    .hburst         (imem_hburst        ),
    .hsize          (imem_hsize         ),
    .htrans         (imem_htrans        ),
    .hmastlock      (imem_hmastlock     ),
    .haddr          (imem_haddr         ),
    .hready         (imem_hready        ),
    .hrdata         (imem_hrdata        ),
    .hresp          (imem_hresp         )
);
 
 
//-------------------------------------------------------------------------------
// Data memory AHB bridge
//-------------------------------------------------------------------------------
scr1_dmem_ahb i_dmem_ahb (
    .rst_n          (core_rst_n_local   ),
    .clk            (clk                ),
    // Interface to dmem router
    .dmem_req_ack   (ahb_dmem_req_ack   ),
    .dmem_req       (ahb_dmem_req       ),
    .dmem_cmd       (ahb_dmem_cmd       ),
    .dmem_width     (ahb_dmem_width     ),
    .dmem_addr      (ahb_dmem_addr      ),
    .dmem_wdata     (ahb_dmem_wdata     ),
    .dmem_rdata     (ahb_dmem_rdata     ),
    .dmem_resp      (ahb_dmem_resp      ),
    // AHB interface
    .hprot          (dmem_hprot         ),
    .hburst         (dmem_hburst        ),
    .hsize          (dmem_hsize         ),
    .htrans         (dmem_htrans        ),
    .hmastlock      (dmem_hmastlock     ),
    .haddr          (dmem_haddr         ),
    .hwrite         (dmem_hwrite        ),
    .hwdata         (dmem_hwdata        ),
    .hready         (dmem_hready        ),
    .hrdata         (dmem_hrdata        ),
    .hresp          (dmem_hresp         )
);
 
endmodule : scr1_top_ahb
 
 

Line No.	Rev	Author	Line
1	11	dinesha	`/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details`
2			`/// @file`
3			`/// @brief SCR1 AHB top`
4			`///`
5
6			`include "scr1_arch_description.svh"
7			`include "scr1_memif.svh"
8			`include "scr1_ahb.svh"
9			`ifdef SCR1_IPIC_EN
10			`include "scr1_ipic.svh"
11			`endif // SCR1_IPIC_EN
12
13			`ifdef SCR1_TCM_EN
14			`define SCR1_IMEM_ROUTER_EN
15			`endif // SCR1_TCM_EN
16
17			`module scr1_top_ahb (`
18			`// Control`
19			`input logic pwrup_rst_n, // Power-Up Reset`
20			`input logic rst_n, // Regular Reset signal`
21			`input logic cpu_rst_n, // CPU Reset (Core Reset)`
22			`input logic test_mode, // Test mode`
23			`input logic test_rst_n, // Test mode's reset`
24			`input logic clk, // System clock`
25			`input logic rtc_clk, // Real-time clock`
26			`ifdef SCR1_DBG_EN
27			`output logic sys_rst_n_o, // External System Reset output`
28			`// (for the processor cluster's components or`
29			`// external SOC (could be useful in small`
30			`// SCR-core-centric SOCs))`
31			`output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier`
32			`endif // SCR1_DBG_EN
33
34			`// Fuses`
35			input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
36			`ifdef SCR1_DBG_EN
37			`input logic [31:0] fuse_idcode, // TAPC IDCODE`
38			`endif // SCR1_DBG_EN
39
40			`// IRQ`
41			`ifdef SCR1_IPIC_EN
42			`input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC`
43			`else // SCR1_IPIC_EN
44			`input logic ext_irq, // External IRQ input`
45			`endif // SCR1_IPIC_EN
46			`input logic soft_irq, // Software IRQ input`
47
48			`ifdef SCR1_DBG_EN
49			`// -- JTAG I/F`
50			`input logic trst_n,`
51			`input logic tck,`
52			`input logic tms,`
53			`input logic tdi,`
54			`output logic tdo,`
55			`output logic tdo_en,`
56			`endif // SCR1_DBG_EN
57
58			`// Instruction Memory Interface`
59			`output logic [3:0] imem_hprot,`
60			`output logic [2:0] imem_hburst,`
61			`output logic [2:0] imem_hsize,`
62			`output logic [1:0] imem_htrans,`
63			`output logic imem_hmastlock,`
64			`output logic [SCR1_AHB_WIDTH-1:0] imem_haddr,`
65			`input logic imem_hready,`
66			`input logic [SCR1_AHB_WIDTH-1:0] imem_hrdata,`
67			`input logic imem_hresp,`
68
69			`// Data Memory Interface`
70			`output logic [3:0] dmem_hprot,`
71			`output logic [2:0] dmem_hburst,`
72			`output logic [2:0] dmem_hsize,`
73			`output logic [1:0] dmem_htrans,`
74			`output logic dmem_hmastlock,`
75			`output logic [SCR1_AHB_WIDTH-1:0] dmem_haddr,`
76			`output logic dmem_hwrite,`
77			`output logic [SCR1_AHB_WIDTH-1:0] dmem_hwdata,`
78			`input logic dmem_hready,`
79			`input logic [SCR1_AHB_WIDTH-1:0] dmem_hrdata,`
80			`input logic dmem_hresp`
81			`);`
82
83			`//-------------------------------------------------------------------------------`
84			`// Local parameters`
85			`//-------------------------------------------------------------------------------`
86			`localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;`
87
88			`//-------------------------------------------------------------------------------`
89			`// Local signal declaration`
90			`//-------------------------------------------------------------------------------`
91			`// Reset logic`
92			`logic pwrup_rst_n_sync;`
93			`logic rst_n_sync;`
94			`logic cpu_rst_n_sync;`
95			`logic core_rst_n_local;`
96			`ifdef SCR1_DBG_EN
97			`logic tapc_trst_n;`
98			`endif // SCR1_DBG_EN
99
100			`// Instruction memory interface from core to router`
101			`logic core_imem_req_ack;`
102			`logic core_imem_req;`
103	21	dinesha	`logic core_imem_cmd;`
104	11	dinesha	logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
105			logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
106	21	dinesha	`logic [1:0] core_imem_resp;`
107	11	dinesha
108			`// Data memory interface from core to router`
109			`logic core_dmem_req_ack;`
110			`logic core_dmem_req;`
111	21	dinesha	`logic core_dmem_cmd;`
112			`logic [1:0] core_dmem_width;`
113	11	dinesha	logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
114			logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
115			logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
116	21	dinesha	`logic [1:0] core_dmem_resp;`
117	11	dinesha
118			`// Instruction memory interface from router to AHB bridge`
119			`logic ahb_imem_req_ack;`
120			`logic ahb_imem_req;`
121	21	dinesha	`logic ahb_imem_cmd;`
122	11	dinesha	logic [`SCR1_IMEM_AWIDTH-1:0] ahb_imem_addr;
123			logic [`SCR1_IMEM_DWIDTH-1:0] ahb_imem_rdata;
124	21	dinesha	`logic [1:0] ahb_imem_resp;`
125	11	dinesha
126			`// Data memory interface from router to AHB bridge`
127			`logic ahb_dmem_req_ack;`
128			`logic ahb_dmem_req;`
129	21	dinesha	`logic ahb_dmem_cmd;`
130			`logic [1:0] ahb_dmem_width;`
131	11	dinesha	logic [`SCR1_DMEM_AWIDTH-1:0] ahb_dmem_addr;
132			logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_wdata;
133			logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_rdata;
134	21	dinesha	`logic [1:0] ahb_dmem_resp;`
135	11	dinesha
136			`ifdef SCR1_TCM_EN
137			`// Instruction memory interface from router to TCM`
138			`logic tcm_imem_req_ack;`
139			`logic tcm_imem_req;`
140	21	dinesha	`logic tcm_imem_cmd;`
141	11	dinesha	logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
142			logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
143	21	dinesha	`logic [1:0] tcm_imem_resp;`
144	11	dinesha
145			`// Data memory interface from router to TCM`
146			`logic tcm_dmem_req_ack;`
147			`logic tcm_dmem_req;`
148	21	dinesha	`logic tcm_dmem_cmd;`
149			`logic [1:0] tcm_dmem_width;`
150	11	dinesha	logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
151			logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
152			logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
153	21	dinesha	`logic [1:0] tcm_dmem_resp;`
154	11	dinesha	`endif // SCR1_TCM_EN
155
156			`// Data memory interface from router to memory-mapped timer`
157			`logic timer_dmem_req_ack;`
158			`logic timer_dmem_req;`
159	21	dinesha	`logic timer_dmem_cmd;`
160			`logic [1:0] timer_dmem_width;`
161	11	dinesha	logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
162			logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
163			logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
164	21	dinesha	`logic [1:0] timer_dmem_resp;`
165	11	dinesha
166			`logic timer_irq;`
167			`logic [63:0] timer_val;`
168
169
170			`//-------------------------------------------------------------------------------`
171			`// Reset logic`
172			`//-------------------------------------------------------------------------------`
173			`// Power-Up Reset synchronizer`
174			`scr1_reset_sync_cell #(`
175			`.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)`
176			`) i_pwrup_rstn_reset_sync (`
177			`.rst_n (pwrup_rst_n ),`
178			`.clk (clk ),`
179			`.test_rst_n (test_rst_n ),`
180			`.test_mode (test_mode ),`
181			`.rst_n_in (1'b1 ),`
182			`.rst_n_out (pwrup_rst_n_sync)`
183			`);`
184
185			`// Regular Reset synchronizer`
186			`scr1_reset_sync_cell #(`
187			`.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)`
188			`) i_rstn_reset_sync (`
189			`.rst_n (pwrup_rst_n ),`
190			`.clk (clk ),`
191			`.test_rst_n (test_rst_n ),`
192			`.test_mode (test_mode ),`
193			`.rst_n_in (rst_n ),`
194			`.rst_n_out (rst_n_sync )`
195			`);`
196
197			`// CPU Reset synchronizer`
198			`scr1_reset_sync_cell #(`
199			`.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)`
200			`) i_cpu_rstn_reset_sync (`
201			`.rst_n (pwrup_rst_n ),`
202			`.clk (clk ),`
203			`.test_rst_n (test_rst_n ),`
204			`.test_mode (test_mode ),`
205			`.rst_n_in (cpu_rst_n ),`
206			`.rst_n_out (cpu_rst_n_sync )`
207			`);`
208
209			`ifdef SCR1_DBG_EN
210			`// TAPC Reset`
211			`scr1_reset_and2_cell i_tapc_rstn_and2_cell (`
212			`.rst_n_in ({trst_n, pwrup_rst_n}),`
213			`.test_rst_n (test_rst_n ),`
214			`.test_mode (test_mode ),`
215			`.rst_n_out (tapc_trst_n )`
216			`);`
217			`endif // SCR1_DBG_EN
218
219			`//-------------------------------------------------------------------------------`
220			`// SCR1 core instance`
221			`//-------------------------------------------------------------------------------`
222			`scr1_core_top i_core_top (`
223			`// Common`
224			`.pwrup_rst_n (pwrup_rst_n_sync ),`
225			`.rst_n (rst_n_sync ),`
226			`.cpu_rst_n (cpu_rst_n_sync ),`
227			`.test_mode (test_mode ),`
228			`.test_rst_n (test_rst_n ),`
229			`.clk (clk ),`
230			`.core_rst_n_o (core_rst_n_local ),`
231			`.core_rdc_qlfy_o ( ),`
232			`ifdef SCR1_DBG_EN
233			`.sys_rst_n_o (sys_rst_n_o ),`
234			`.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),`
235			`endif // SCR1_DBG_EN
236
237			`// Fuses`
238			`.core_fuse_mhartid_i (fuse_mhartid ),`
239			`ifdef SCR1_DBG_EN
240			`.tapc_fuse_idcode_i (fuse_idcode ),`
241			`endif // SCR1_DBG_EN
242
243			`// IRQ`
244			`ifdef SCR1_IPIC_EN
245			`.core_irq_lines_i (irq_lines ),`
246			`else // SCR1_IPIC_EN
247			`.core_irq_ext_i (ext_irq ),`
248			`endif // SCR1_IPIC_EN
249			`.core_irq_soft_i (soft_irq ),`
250			`.core_irq_mtimer_i (timer_irq ),`
251
252			`// Memory-mapped external timer`
253			`.core_mtimer_val_i (timer_val ),`
254
255			`ifdef SCR1_DBG_EN
256			`// Debug interface`
257			`.tapc_trst_n (tapc_trst_n ),`
258			`.tapc_tck (tck ),`
259			`.tapc_tms (tms ),`
260			`.tapc_tdi (tdi ),`
261			`.tapc_tdo (tdo ),`
262			`.tapc_tdo_en (tdo_en ),`
263			`endif // SCR1_DBG_EN
264
265			`// Instruction memory interface`
266			`.imem2core_req_ack_i (core_imem_req_ack),`
267			`.core2imem_req_o (core_imem_req ),`
268			`.core2imem_cmd_o (core_imem_cmd ),`
269			`.core2imem_addr_o (core_imem_addr ),`
270			`.imem2core_rdata_i (core_imem_rdata ),`
271			`.imem2core_resp_i (core_imem_resp ),`
272
273			`// Data memory interface`
274			`.dmem2core_req_ack_i (core_dmem_req_ack),`
275			`.core2dmem_req_o (core_dmem_req ),`
276			`.core2dmem_cmd_o (core_dmem_cmd ),`
277			`.core2dmem_width_o (core_dmem_width ),`
278			`.core2dmem_addr_o (core_dmem_addr ),`
279			`.core2dmem_wdata_o (core_dmem_wdata ),`
280			`.dmem2core_rdata_i (core_dmem_rdata ),`
281			`.dmem2core_resp_i (core_dmem_resp )`
282			`);`
283
284
285			`ifdef SCR1_TCM_EN
286			`//-------------------------------------------------------------------------------`
287			`// TCM instance`
288			`//-------------------------------------------------------------------------------`
289			`scr1_tcm #(`
290			.SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
291			`) i_tcm (`
292			`.clk (clk ),`
293			`.rst_n (core_rst_n_local),`
294
295			`// Instruction interface to TCM`
296			`.imem_req_ack (tcm_imem_req_ack),`
297			`.imem_req (tcm_imem_req ),`
298			`.imem_addr (tcm_imem_addr ),`
299			`.imem_rdata (tcm_imem_rdata ),`
300			`.imem_resp (tcm_imem_resp ),`
301
302			`// Data interface to TCM`
303			`.dmem_req_ack (tcm_dmem_req_ack),`
304			`.dmem_req (tcm_dmem_req ),`
305			`.dmem_cmd (tcm_dmem_cmd ),`
306			`.dmem_width (tcm_dmem_width ),`
307			`.dmem_addr (tcm_dmem_addr ),`
308			`.dmem_wdata (tcm_dmem_wdata ),`
309			`.dmem_rdata (tcm_dmem_rdata ),`
310			`.dmem_resp (tcm_dmem_resp )`
311			`);`
312			`endif // SCR1_TCM_EN
313
314
315			`//-------------------------------------------------------------------------------`
316			`// Memory-mapped timer instance`
317			`//-------------------------------------------------------------------------------`
318			`scr1_timer i_timer (`
319			`// Common`
320			`.rst_n (core_rst_n_local ),`
321			`.clk (clk ),`
322			`.rtc_clk (rtc_clk ),`
323
324			`// Memory interface`
325			`.dmem_req (timer_dmem_req ),`
326			`.dmem_cmd (timer_dmem_cmd ),`
327			`.dmem_width (timer_dmem_width ),`
328			`.dmem_addr (timer_dmem_addr ),`
329			`.dmem_wdata (timer_dmem_wdata ),`
330			`.dmem_req_ack (timer_dmem_req_ack),`
331			`.dmem_rdata (timer_dmem_rdata ),`
332			`.dmem_resp (timer_dmem_resp ),`
333
334			`// Timer interface`
335			`.timer_val (timer_val ),`
336			`.timer_irq (timer_irq )`
337			`);`
338
339
340			`ifdef SCR1_IMEM_ROUTER_EN
341			`//-------------------------------------------------------------------------------`
342			`// Instruction memory router`
343			`//-------------------------------------------------------------------------------`
344			`scr1_imem_router #(`
345			`ifdef SCR1_TCM_EN
346			`.SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),`
347			`.SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)`
348			`endif // SCR1_TCM_EN
349			`) i_imem_router (`
350			`.rst_n (core_rst_n_local ),`
351			`.clk (clk ),`
352			`// Interface to core`
353			`.imem_req_ack (core_imem_req_ack),`
354			`.imem_req (core_imem_req ),`
355			`.imem_cmd (core_imem_cmd ),`
356			`.imem_addr (core_imem_addr ),`
357			`.imem_rdata (core_imem_rdata ),`
358			`.imem_resp (core_imem_resp ),`
359			`// Interface to AHB bridge`
360			`.port0_req_ack (ahb_imem_req_ack ),`
361			`.port0_req (ahb_imem_req ),`
362			`.port0_cmd (ahb_imem_cmd ),`
363			`.port0_addr (ahb_imem_addr ),`
364			`.port0_rdata (ahb_imem_rdata ),`
365			`.port0_resp (ahb_imem_resp ),`
366			`ifdef SCR1_TCM_EN
367			`// Interface to TCM`
368			`.port1_req_ack (tcm_imem_req_ack ),`
369			`.port1_req (tcm_imem_req ),`
370			`.port1_cmd (tcm_imem_cmd ),`
371			`.port1_addr (tcm_imem_addr ),`
372			`.port1_rdata (tcm_imem_rdata ),`
373			`.port1_resp (tcm_imem_resp )`
374			`endif // SCR1_TCM_EN
375			`);`
376
377			`else // SCR1_IMEM_ROUTER_EN
378
379			`assign ahb_imem_req = core_imem_req;`
380			`assign ahb_imem_cmd = core_imem_cmd;`
381			`assign ahb_imem_addr = core_imem_addr;`
382			`assign core_imem_req_ack = ahb_imem_req_ack;`
383			`assign core_imem_resp = ahb_imem_resp;`
384			`assign core_imem_rdata = ahb_imem_rdata;`
385
386			`endif // SCR1_IMEM_ROUTER_EN
387
388			`//-------------------------------------------------------------------------------`
389			`// Data memory router`
390			`//-------------------------------------------------------------------------------`
391			`scr1_dmem_router #(`
392
393			`ifdef SCR1_TCM_EN
394			`.SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),`
395			`.SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),`
396			`else // SCR1_TCM_EN
397			`.SCR1_PORT1_ADDR_MASK (32'h00000000),`
398			`.SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),`
399			`endif // SCR1_TCM_EN
400
401			`.SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),`
402			`.SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)`
403
404			`) i_dmem_router (`
405			`.rst_n (core_rst_n_local ),`
406			`.clk (clk ),`
407			`// Interface to core`
408			`.dmem_req_ack (core_dmem_req_ack ),`
409			`.dmem_req (core_dmem_req ),`
410			`.dmem_cmd (core_dmem_cmd ),`
411			`.dmem_width (core_dmem_width ),`
412			`.dmem_addr (core_dmem_addr ),`
413			`.dmem_wdata (core_dmem_wdata ),`
414			`.dmem_rdata (core_dmem_rdata ),`
415			`.dmem_resp (core_dmem_resp ),`
416			`ifdef SCR1_TCM_EN
417			`// Interface to TCM`
418			`.port1_req_ack (tcm_dmem_req_ack ),`
419			`.port1_req (tcm_dmem_req ),`
420			`.port1_cmd (tcm_dmem_cmd ),`
421			`.port1_width (tcm_dmem_width ),`
422			`.port1_addr (tcm_dmem_addr ),`
423			`.port1_wdata (tcm_dmem_wdata ),`
424			`.port1_rdata (tcm_dmem_rdata ),`
425			`.port1_resp (tcm_dmem_resp ),`
426			`else // SCR1_TCM_EN
427			`.port1_req_ack (1'b0),`
428			`.port1_req ( ),`
429			`.port1_cmd ( ),`
430			`.port1_width ( ),`
431			`.port1_addr ( ),`
432			`.port1_wdata ( ),`
433			`.port1_rdata ('0 ),`
434			`.port1_resp (SCR1_MEM_RESP_RDY_ER),`
435			`endif // SCR1_TCM_EN
436			`// Interface to memory-mapped timer`
437			`.port2_req_ack (timer_dmem_req_ack ),`
438			`.port2_req (timer_dmem_req ),`
439			`.port2_cmd (timer_dmem_cmd ),`
440			`.port2_width (timer_dmem_width ),`
441			`.port2_addr (timer_dmem_addr ),`
442			`.port2_wdata (timer_dmem_wdata ),`
443			`.port2_rdata (timer_dmem_rdata ),`
444			`.port2_resp (timer_dmem_resp ),`
445			`// Interface to AHB bridge`
446			`.port0_req_ack (ahb_dmem_req_ack ),`
447			`.port0_req (ahb_dmem_req ),`
448			`.port0_cmd (ahb_dmem_cmd ),`
449			`.port0_width (ahb_dmem_width ),`
450			`.port0_addr (ahb_dmem_addr ),`
451			`.port0_wdata (ahb_dmem_wdata ),`
452			`.port0_rdata (ahb_dmem_rdata ),`
453			`.port0_resp (ahb_dmem_resp )`
454			`);`
455
456
457			`//-------------------------------------------------------------------------------`
458			`// Instruction memory AHB bridge`
459			`//-------------------------------------------------------------------------------`
460			`scr1_imem_ahb i_imem_ahb (`
461			`.rst_n (core_rst_n_local ),`
462			`.clk (clk ),`
463			`// Interface to imem router`
464			`.imem_req_ack (ahb_imem_req_ack ),`
465			`.imem_req (ahb_imem_req ),`
466			`.imem_addr (ahb_imem_addr ),`
467			`.imem_rdata (ahb_imem_rdata ),`
468			`.imem_resp (ahb_imem_resp ),`
469			`// AHB interface`
470			`.hprot (imem_hprot ),`
471			`.hburst (imem_hburst ),`
472			`.hsize (imem_hsize ),`
473			`.htrans (imem_htrans ),`
474			`.hmastlock (imem_hmastlock ),`
475			`.haddr (imem_haddr ),`
476			`.hready (imem_hready ),`
477			`.hrdata (imem_hrdata ),`
478			`.hresp (imem_hresp )`
479			`);`
480
481
482			`//-------------------------------------------------------------------------------`
483			`// Data memory AHB bridge`
484			`//-------------------------------------------------------------------------------`
485			`scr1_dmem_ahb i_dmem_ahb (`
486			`.rst_n (core_rst_n_local ),`
487			`.clk (clk ),`
488			`// Interface to dmem router`
489			`.dmem_req_ack (ahb_dmem_req_ack ),`
490			`.dmem_req (ahb_dmem_req ),`
491			`.dmem_cmd (ahb_dmem_cmd ),`
492			`.dmem_width (ahb_dmem_width ),`
493			`.dmem_addr (ahb_dmem_addr ),`
494			`.dmem_wdata (ahb_dmem_wdata ),`
495			`.dmem_rdata (ahb_dmem_rdata ),`
496			`.dmem_resp (ahb_dmem_resp ),`
497			`// AHB interface`
498			`.hprot (dmem_hprot ),`
499			`.hburst (dmem_hburst ),`
500			`.hsize (dmem_hsize ),`

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