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dinesha |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// yifive Wishbone interface for syntacore ////
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//// ////
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//// This file is part of the yifive cores project ////
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//// http://www.opencores.org/cores/yifive/ ////
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//// ////
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//// Description: ////
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//// integrated wishbone i/f to instruction/data memory ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// Revision : ////
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//// v0: June 7, 2021, Dinesh A ////
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//// wishbone integration ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Orginal owner Details ////
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//////////////////////////////////////////////////////////////////////
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/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details///
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/// @file ///
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/// @brief SCR1 AHB top ///
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//////////////////////////////////////////////////////////////////////
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`include "scr1_wb.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TCM_EN
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`define SCR1_IMEM_ROUTER_EN
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`endif // SCR1_TCM_EN
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module scr1_top_wb (
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// Control
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input logic pwrup_rst_n, // Power-Up Reset
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input logic rst_n, // Regular Reset signal
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input logic cpu_rst_n, // CPU Reset (Core Reset)
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input logic test_mode, // Test mode
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input logic test_rst_n, // Test mode's reset
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input logic clk, // System clock
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input logic rtc_clk, // Real-time clock
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`ifdef SCR1_DBG_EN
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output logic sys_rst_n_o, // External System Reset output
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// (for the processor cluster's components or
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// external SOC (could be useful in small
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// SCR-core-centric SOCs))
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output logic sys_rdc_qlfy_o, // System-to-External SOC Reset Domain Crossing Qualifier
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`endif // SCR1_DBG_EN
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// Fuses
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input logic [`SCR1_XLEN-1:0] fuse_mhartid, // Hart ID
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`ifdef SCR1_DBG_EN
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input logic [31:0] fuse_idcode, // TAPC IDCODE
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] irq_lines, // IRQ lines to IPIC
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`else // SCR1_IPIC_EN
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input logic ext_irq, // External IRQ input
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`endif // SCR1_IPIC_EN
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input logic soft_irq, // Software IRQ input
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`ifdef SCR1_DBG_EN
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// -- JTAG I/F
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input logic trst_n,
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input logic tck,
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input logic tms,
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input logic tdi,
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output logic tdo,
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output logic tdo_en,
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`endif // SCR1_DBG_EN
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// Instruction Memory Interface
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output logic wbd_imem_stb_o, // strobe/request
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output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
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output logic wbd_imem_we_o, // write
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output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
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output logic [3:0] wbd_imem_sel_o, // byte enable
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input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
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input logic wbd_imem_ack_i, // acknowlegement
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input logic wbd_imem_err_i, // error
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// Data Memory Interface
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output logic wbd_dmem_stb_o, // strobe/request
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output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
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output logic wbd_dmem_we_o, // write
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output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
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output logic [3:0] wbd_dmem_sel_o, // byte enable
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input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
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input logic wbd_dmem_ack_i, // acknowlegement
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input logic wbd_dmem_err_i // error
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);
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//-------------------------------------------------------------------------------
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// Local parameters
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//-------------------------------------------------------------------------------
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localparam int unsigned SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM = 2;
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//-------------------------------------------------------------------------------
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// Local signal declaration
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//-------------------------------------------------------------------------------
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// Reset logic
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logic pwrup_rst_n_sync;
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logic rst_n_sync;
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logic cpu_rst_n_sync;
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logic core_rst_n_local;
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`ifdef SCR1_DBG_EN
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logic tapc_trst_n;
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`endif // SCR1_DBG_EN
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// Instruction memory interface from core to router
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logic core_imem_req_ack;
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logic core_imem_req;
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dinesha |
logic core_imem_cmd;
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dinesha |
logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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logic [1:0] core_imem_resp;
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dinesha |
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// Data memory interface from core to router
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logic core_dmem_req_ack;
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logic core_dmem_req;
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dinesha |
logic core_dmem_cmd;
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logic [1:0] core_dmem_width;
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dinesha |
logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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dinesha |
logic [1:0] core_dmem_resp;
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dinesha |
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// Instruction memory interface from router to WB bridge
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logic wb_imem_req_ack;
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logic wb_imem_req;
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logic wb_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
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logic [1:0] wb_imem_resp;
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// Data memory interface from router to WB bridge
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logic wb_dmem_req_ack;
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logic wb_dmem_req;
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logic wb_dmem_cmd;
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logic [1:0] wb_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
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logic [1:0] wb_dmem_resp;
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dinesha |
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`ifdef SCR1_TCM_EN
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// Instruction memory interface from router to TCM
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logic tcm_imem_req_ack;
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logic tcm_imem_req;
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dinesha |
logic tcm_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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dinesha |
logic [1:0] tcm_imem_resp;
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dinesha |
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// Data memory interface from router to TCM
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req;
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dinesha |
logic tcm_dmem_cmd;
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logic [1:0] tcm_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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logic [1:0] tcm_dmem_resp;
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`endif // SCR1_TCM_EN
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// Data memory interface from router to memory-mapped timer
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logic timer_dmem_req_ack;
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logic timer_dmem_req;
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logic timer_dmem_cmd;
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logic [1:0] timer_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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dinesha |
logic [1:0] timer_dmem_resp;
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logic timer_irq;
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logic [63:0] timer_val;
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//-------------------------------------------------------------------------------
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// Reset logic
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//-------------------------------------------------------------------------------
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// Power-Up Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_pwrup_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (1'b1 ),
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.rst_n_out (pwrup_rst_n_sync)
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);
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// Regular Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (rst_n ),
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.rst_n_out (rst_n_sync )
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);
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// CPU Reset synchronizer
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scr1_reset_sync_cell #(
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.STAGES_AMOUNT (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
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) i_cpu_rstn_reset_sync (
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.rst_n (pwrup_rst_n ),
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.clk (clk ),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_in (cpu_rst_n ),
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.rst_n_out (cpu_rst_n_sync )
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);
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`ifdef SCR1_DBG_EN
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// TAPC Reset
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scr1_reset_and2_cell i_tapc_rstn_and2_cell (
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.rst_n_in ({trst_n, pwrup_rst_n}),
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.test_rst_n (test_rst_n ),
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.test_mode (test_mode ),
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.rst_n_out (tapc_trst_n )
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);
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`endif // SCR1_DBG_EN
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//-------------------------------------------------------------------------------
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// SCR1 core instance
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//-------------------------------------------------------------------------------
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scr1_core_top i_core_top (
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// Common
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.pwrup_rst_n (pwrup_rst_n_sync ),
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.rst_n (rst_n_sync ),
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.cpu_rst_n (cpu_rst_n_sync ),
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.test_mode (test_mode ),
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.test_rst_n (test_rst_n ),
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.clk (clk ),
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.core_rst_n_o (core_rst_n_local ),
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.core_rdc_qlfy_o ( ),
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`ifdef SCR1_DBG_EN
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.sys_rst_n_o (sys_rst_n_o ),
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.sys_rdc_qlfy_o (sys_rdc_qlfy_o ),
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`endif // SCR1_DBG_EN
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| 280 |
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// Fuses
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.core_fuse_mhartid_i (fuse_mhartid ),
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`ifdef SCR1_DBG_EN
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.tapc_fuse_idcode_i (fuse_idcode ),
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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.core_irq_lines_i (irq_lines ),
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`else // SCR1_IPIC_EN
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.core_irq_ext_i (ext_irq ),
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`endif // SCR1_IPIC_EN
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.core_irq_soft_i (soft_irq ),
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.core_irq_mtimer_i (timer_irq ),
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// Memory-mapped external timer
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.core_mtimer_val_i (timer_val ),
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`ifdef SCR1_DBG_EN
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// Debug interface
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.tapc_trst_n (tapc_trst_n ),
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.tapc_tck (tck ),
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.tapc_tms (tms ),
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.tapc_tdi (tdi ),
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.tapc_tdo (tdo ),
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.tapc_tdo_en (tdo_en ),
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`endif // SCR1_DBG_EN
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|
|
| 309 |
|
|
// Instruction memory interface
|
| 310 |
|
|
.imem2core_req_ack_i (core_imem_req_ack),
|
| 311 |
|
|
.core2imem_req_o (core_imem_req ),
|
| 312 |
|
|
.core2imem_cmd_o (core_imem_cmd ),
|
| 313 |
|
|
.core2imem_addr_o (core_imem_addr ),
|
| 314 |
|
|
.imem2core_rdata_i (core_imem_rdata ),
|
| 315 |
|
|
.imem2core_resp_i (core_imem_resp ),
|
| 316 |
|
|
|
| 317 |
|
|
// Data memory interface
|
| 318 |
|
|
.dmem2core_req_ack_i (core_dmem_req_ack),
|
| 319 |
|
|
.core2dmem_req_o (core_dmem_req ),
|
| 320 |
|
|
.core2dmem_cmd_o (core_dmem_cmd ),
|
| 321 |
|
|
.core2dmem_width_o (core_dmem_width ),
|
| 322 |
|
|
.core2dmem_addr_o (core_dmem_addr ),
|
| 323 |
|
|
.core2dmem_wdata_o (core_dmem_wdata ),
|
| 324 |
|
|
.dmem2core_rdata_i (core_dmem_rdata ),
|
| 325 |
|
|
.dmem2core_resp_i (core_dmem_resp )
|
| 326 |
|
|
);
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
`ifdef SCR1_TCM_EN
|
| 330 |
|
|
//-------------------------------------------------------------------------------
|
| 331 |
|
|
// TCM instance
|
| 332 |
|
|
//-------------------------------------------------------------------------------
|
| 333 |
|
|
scr1_tcm #(
|
| 334 |
|
|
.SCR1_TCM_SIZE (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
|
| 335 |
|
|
) i_tcm (
|
| 336 |
|
|
.clk (clk ),
|
| 337 |
|
|
.rst_n (core_rst_n_local),
|
| 338 |
|
|
|
| 339 |
|
|
// Instruction interface to TCM
|
| 340 |
|
|
.imem_req_ack (tcm_imem_req_ack),
|
| 341 |
|
|
.imem_req (tcm_imem_req ),
|
| 342 |
|
|
.imem_addr (tcm_imem_addr ),
|
| 343 |
|
|
.imem_rdata (tcm_imem_rdata ),
|
| 344 |
|
|
.imem_resp (tcm_imem_resp ),
|
| 345 |
|
|
|
| 346 |
|
|
// Data interface to TCM
|
| 347 |
|
|
.dmem_req_ack (tcm_dmem_req_ack),
|
| 348 |
|
|
.dmem_req (tcm_dmem_req ),
|
| 349 |
|
|
.dmem_cmd (tcm_dmem_cmd ),
|
| 350 |
|
|
.dmem_width (tcm_dmem_width ),
|
| 351 |
|
|
.dmem_addr (tcm_dmem_addr ),
|
| 352 |
|
|
.dmem_wdata (tcm_dmem_wdata ),
|
| 353 |
|
|
.dmem_rdata (tcm_dmem_rdata ),
|
| 354 |
|
|
.dmem_resp (tcm_dmem_resp )
|
| 355 |
|
|
);
|
| 356 |
|
|
`endif // SCR1_TCM_EN
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
//-------------------------------------------------------------------------------
|
| 360 |
|
|
// Memory-mapped timer instance
|
| 361 |
|
|
//-------------------------------------------------------------------------------
|
| 362 |
|
|
scr1_timer i_timer (
|
| 363 |
|
|
// Common
|
| 364 |
|
|
.rst_n (core_rst_n_local ),
|
| 365 |
|
|
.clk (clk ),
|
| 366 |
|
|
.rtc_clk (rtc_clk ),
|
| 367 |
|
|
|
| 368 |
|
|
// Memory interface
|
| 369 |
|
|
.dmem_req (timer_dmem_req ),
|
| 370 |
|
|
.dmem_cmd (timer_dmem_cmd ),
|
| 371 |
|
|
.dmem_width (timer_dmem_width ),
|
| 372 |
|
|
.dmem_addr (timer_dmem_addr ),
|
| 373 |
|
|
.dmem_wdata (timer_dmem_wdata ),
|
| 374 |
|
|
.dmem_req_ack (timer_dmem_req_ack),
|
| 375 |
|
|
.dmem_rdata (timer_dmem_rdata ),
|
| 376 |
|
|
.dmem_resp (timer_dmem_resp ),
|
| 377 |
|
|
|
| 378 |
|
|
// Timer interface
|
| 379 |
|
|
.timer_val (timer_val ),
|
| 380 |
|
|
.timer_irq (timer_irq )
|
| 381 |
|
|
);
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
`ifdef SCR1_IMEM_ROUTER_EN
|
| 385 |
|
|
//-------------------------------------------------------------------------------
|
| 386 |
|
|
// Instruction memory router
|
| 387 |
|
|
//-------------------------------------------------------------------------------
|
| 388 |
|
|
scr1_imem_router #(
|
| 389 |
|
|
`ifdef SCR1_TCM_EN
|
| 390 |
|
|
.SCR1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
| 391 |
|
|
.SCR1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN)
|
| 392 |
|
|
`endif // SCR1_TCM_EN
|
| 393 |
|
|
) i_imem_router (
|
| 394 |
|
|
.rst_n (core_rst_n_local ),
|
| 395 |
|
|
.clk (clk ),
|
| 396 |
|
|
// Interface to core
|
| 397 |
|
|
.imem_req_ack (core_imem_req_ack),
|
| 398 |
|
|
.imem_req (core_imem_req ),
|
| 399 |
|
|
.imem_cmd (core_imem_cmd ),
|
| 400 |
|
|
.imem_addr (core_imem_addr ),
|
| 401 |
|
|
.imem_rdata (core_imem_rdata ),
|
| 402 |
|
|
.imem_resp (core_imem_resp ),
|
| 403 |
|
|
// Interface to WB bridge
|
| 404 |
|
|
.port0_req_ack (wb_imem_req_ack ),
|
| 405 |
|
|
.port0_req (wb_imem_req ),
|
| 406 |
|
|
.port0_cmd (wb_imem_cmd ),
|
| 407 |
|
|
.port0_addr (wb_imem_addr ),
|
| 408 |
|
|
.port0_rdata (wb_imem_rdata ),
|
| 409 |
|
|
.port0_resp (wb_imem_resp ),
|
| 410 |
|
|
`ifdef SCR1_TCM_EN
|
| 411 |
|
|
// Interface to TCM
|
| 412 |
|
|
.port1_req_ack (tcm_imem_req_ack ),
|
| 413 |
|
|
.port1_req (tcm_imem_req ),
|
| 414 |
|
|
.port1_cmd (tcm_imem_cmd ),
|
| 415 |
|
|
.port1_addr (tcm_imem_addr ),
|
| 416 |
|
|
.port1_rdata (tcm_imem_rdata ),
|
| 417 |
|
|
.port1_resp (tcm_imem_resp )
|
| 418 |
|
|
`endif // SCR1_TCM_EN
|
| 419 |
|
|
);
|
| 420 |
|
|
|
| 421 |
|
|
`else // SCR1_IMEM_ROUTER_EN
|
| 422 |
|
|
|
| 423 |
|
|
assign wb_imem_req = core_imem_req;
|
| 424 |
|
|
assign wb_imem_cmd = core_imem_cmd;
|
| 425 |
|
|
assign wb_imem_addr = core_imem_addr;
|
| 426 |
|
|
assign core_imem_req_ack = wb_imem_req_ack;
|
| 427 |
|
|
assign core_imem_resp = wb_imem_resp;
|
| 428 |
|
|
assign core_imem_rdata = wb_imem_rdata;
|
| 429 |
|
|
|
| 430 |
|
|
`endif // SCR1_IMEM_ROUTER_EN
|
| 431 |
|
|
|
| 432 |
|
|
//-------------------------------------------------------------------------------
|
| 433 |
|
|
// Data memory router
|
| 434 |
|
|
//-------------------------------------------------------------------------------
|
| 435 |
|
|
scr1_dmem_router #(
|
| 436 |
|
|
|
| 437 |
|
|
`ifdef SCR1_TCM_EN
|
| 438 |
|
|
.SCR1_PORT1_ADDR_MASK (SCR1_TCM_ADDR_MASK),
|
| 439 |
|
|
.SCR1_PORT1_ADDR_PATTERN (SCR1_TCM_ADDR_PATTERN),
|
| 440 |
|
|
`else // SCR1_TCM_EN
|
| 441 |
|
|
.SCR1_PORT1_ADDR_MASK (32'h00000000),
|
| 442 |
|
|
.SCR1_PORT1_ADDR_PATTERN (32'hFFFFFFFF),
|
| 443 |
|
|
`endif // SCR1_TCM_EN
|
| 444 |
|
|
|
| 445 |
|
|
.SCR1_PORT2_ADDR_MASK (SCR1_TIMER_ADDR_MASK),
|
| 446 |
|
|
.SCR1_PORT2_ADDR_PATTERN (SCR1_TIMER_ADDR_PATTERN)
|
| 447 |
|
|
|
| 448 |
|
|
) i_dmem_router (
|
| 449 |
|
|
.rst_n (core_rst_n_local ),
|
| 450 |
|
|
.clk (clk ),
|
| 451 |
|
|
// Interface to core
|
| 452 |
|
|
.dmem_req_ack (core_dmem_req_ack ),
|
| 453 |
|
|
.dmem_req (core_dmem_req ),
|
| 454 |
|
|
.dmem_cmd (core_dmem_cmd ),
|
| 455 |
|
|
.dmem_width (core_dmem_width ),
|
| 456 |
|
|
.dmem_addr (core_dmem_addr ),
|
| 457 |
|
|
.dmem_wdata (core_dmem_wdata ),
|
| 458 |
|
|
.dmem_rdata (core_dmem_rdata ),
|
| 459 |
|
|
.dmem_resp (core_dmem_resp ),
|
| 460 |
|
|
`ifdef SCR1_TCM_EN
|
| 461 |
|
|
// Interface to TCM
|
| 462 |
|
|
.port1_req_ack (tcm_dmem_req_ack ),
|
| 463 |
|
|
.port1_req (tcm_dmem_req ),
|
| 464 |
|
|
.port1_cmd (tcm_dmem_cmd ),
|
| 465 |
|
|
.port1_width (tcm_dmem_width ),
|
| 466 |
|
|
.port1_addr (tcm_dmem_addr ),
|
| 467 |
|
|
.port1_wdata (tcm_dmem_wdata ),
|
| 468 |
|
|
.port1_rdata (tcm_dmem_rdata ),
|
| 469 |
|
|
.port1_resp (tcm_dmem_resp ),
|
| 470 |
|
|
`else // SCR1_TCM_EN
|
| 471 |
|
|
.port1_req_ack (1'b0),
|
| 472 |
|
|
.port1_req ( ),
|
| 473 |
|
|
.port1_cmd ( ),
|
| 474 |
|
|
.port1_width ( ),
|
| 475 |
|
|
.port1_addr ( ),
|
| 476 |
|
|
.port1_wdata ( ),
|
| 477 |
21 |
dinesha |
.port1_rdata (32'h0 ),
|
| 478 |
11 |
dinesha |
.port1_resp (SCR1_MEM_RESP_RDY_ER),
|
| 479 |
|
|
`endif // SCR1_TCM_EN
|
| 480 |
|
|
// Interface to memory-mapped timer
|
| 481 |
|
|
.port2_req_ack (timer_dmem_req_ack ),
|
| 482 |
|
|
.port2_req (timer_dmem_req ),
|
| 483 |
|
|
.port2_cmd (timer_dmem_cmd ),
|
| 484 |
|
|
.port2_width (timer_dmem_width ),
|
| 485 |
|
|
.port2_addr (timer_dmem_addr ),
|
| 486 |
|
|
.port2_wdata (timer_dmem_wdata ),
|
| 487 |
|
|
.port2_rdata (timer_dmem_rdata ),
|
| 488 |
|
|
.port2_resp (timer_dmem_resp ),
|
| 489 |
|
|
// Interface to WB bridge
|
| 490 |
|
|
.port0_req_ack (wb_dmem_req_ack ),
|
| 491 |
|
|
.port0_req (wb_dmem_req ),
|
| 492 |
|
|
.port0_cmd (wb_dmem_cmd ),
|
| 493 |
|
|
.port0_width (wb_dmem_width ),
|
| 494 |
|
|
.port0_addr (wb_dmem_addr ),
|
| 495 |
|
|
.port0_wdata (wb_dmem_wdata ),
|
| 496 |
|
|
.port0_rdata (wb_dmem_rdata ),
|
| 497 |
|
|
.port0_resp (wb_dmem_resp )
|
| 498 |
|
|
);
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
//-------------------------------------------------------------------------------
|
| 502 |
|
|
// Instruction memory WB bridge
|
| 503 |
|
|
//-------------------------------------------------------------------------------
|
| 504 |
|
|
scr1_imem_wb i_imem_wb (
|
| 505 |
|
|
.rst_n (core_rst_n_local ),
|
| 506 |
|
|
.clk (clk ),
|
| 507 |
|
|
// Interface to imem router
|
| 508 |
|
|
.imem_req_ack (wb_imem_req_ack ),
|
| 509 |
|
|
.imem_req (wb_imem_req ),
|
| 510 |
|
|
.imem_addr (wb_imem_addr ),
|
| 511 |
|
|
.imem_rdata (wb_imem_rdata ),
|
| 512 |
|
|
.imem_resp (wb_imem_resp ),
|
| 513 |
|
|
// WB interface
|
| 514 |
|
|
.wbd_stb_o (wbd_imem_stb_o ),
|
| 515 |
|
|
.wbd_adr_o (wbd_imem_adr_o ),
|
| 516 |
|
|
.wbd_we_o (wbd_imem_we_o ),
|
| 517 |
|
|
.wbd_dat_o (wbd_imem_dat_o ),
|
| 518 |
|
|
.wbd_sel_o (wbd_imem_sel_o ),
|
| 519 |
|
|
.wbd_dat_i (wbd_imem_dat_i ),
|
| 520 |
|
|
.wbd_ack_i (wbd_imem_ack_i ),
|
| 521 |
|
|
.wbd_err_i (wbd_imem_err_i )
|
| 522 |
|
|
);
|
| 523 |
|
|
|
| 524 |
|
|
|
| 525 |
|
|
//-------------------------------------------------------------------------------
|
| 526 |
|
|
// Data memory WB bridge
|
| 527 |
|
|
//-------------------------------------------------------------------------------
|
| 528 |
|
|
scr1_dmem_wb i_dmem_wb (
|
| 529 |
|
|
.rst_n (core_rst_n_local ),
|
| 530 |
|
|
.clk (clk ),
|
| 531 |
|
|
// Interface to dmem router
|
| 532 |
|
|
.dmem_req_ack (wb_dmem_req_ack ),
|
| 533 |
|
|
.dmem_req (wb_dmem_req ),
|
| 534 |
|
|
.dmem_cmd (wb_dmem_cmd ),
|
| 535 |
|
|
.dmem_width (wb_dmem_width ),
|
| 536 |
|
|
.dmem_addr (wb_dmem_addr ),
|
| 537 |
|
|
.dmem_wdata (wb_dmem_wdata ),
|
| 538 |
|
|
.dmem_rdata (wb_dmem_rdata ),
|
| 539 |
|
|
.dmem_resp (wb_dmem_resp ),
|
| 540 |
|
|
// WB interface
|
| 541 |
|
|
.wbd_stb_o (wbd_dmem_stb_o ),
|
| 542 |
|
|
.wbd_adr_o (wbd_dmem_adr_o ),
|
| 543 |
|
|
.wbd_we_o (wbd_dmem_we_o ),
|
| 544 |
|
|
.wbd_dat_o (wbd_dmem_dat_o ),
|
| 545 |
|
|
.wbd_sel_o (wbd_dmem_sel_o ),
|
| 546 |
|
|
.wbd_dat_i (wbd_dmem_dat_i ),
|
| 547 |
|
|
.wbd_ack_i (wbd_dmem_ack_i ),
|
| 548 |
|
|
.wbd_err_i (wbd_dmem_err_i )
|
| 549 |
|
|
);
|
| 550 |
|
|
|
| 551 |
|
|
endmodule : scr1_top_wb
|
| 552 |
|
|
|
| 553 |
|
|
|
