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dinesha |
#####################################################
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# Clean up old file and freshly create the directory
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####################################################
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\rm -rf pyfive.sv
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\rm -rf ./tmp
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\rm -rf ./reports
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\rm -rf ./netlist
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mkdir -p ./tmp/synthesis
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mkdir -p ./reports
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mkdir -p ./netlist
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################################################
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# yosys has issue in propgating the golbal parameter from one file to other file
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# to fix this issue, we have concatinated all the rtl file into single file before starting synthesis
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# only memory are exclded from this list
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################################################
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cat ../src/core/pipeline/scr1_pipe_top.sv > pyfive.sv
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cat ../src/core/scr1_core_top.sv >> pyfive.sv
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cat ../src/core/scr1_dm.sv >> pyfive.sv
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cat ../src/core/scr1_tapc_synchronizer.sv >> pyfive.sv
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cat ../src/core/scr1_clk_ctrl.sv >> pyfive.sv
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cat ../src/core/scr1_scu.sv >> pyfive.sv
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cat ../src/core/scr1_tapc.sv >> pyfive.sv
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cat ../src/core/scr1_tapc_shift_reg.sv >> pyfive.sv
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cat ../src/core/scr1_dmi.sv >> pyfive.sv
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cat ../src/core/primitives/scr1_reset_cells.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_ifu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_idu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_exu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_mprf.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_csr.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_ialu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_lsu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_hdu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_pipe_tdu.sv >> pyfive.sv
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cat ../src/core/pipeline/scr1_ipic.sv >> pyfive.sv
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cat ../src/top/scr1_dmem_router.sv >> pyfive.sv
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cat ../src/top/scr1_imem_router.sv >> pyfive.sv
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#cat ../src/top/scr1_dp_memory.sv >> pyfive.sv
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cat ../src/top/scr1_tcm.sv >> pyfive.sv
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cat ../src/top/scr1_timer.sv >> pyfive.sv
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cat ../src/top/scr1_dmem_ahb.sv >> pyfive.sv
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cat ../src/top/scr1_imem_ahb.sv >> pyfive.sv
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cat ../src/top/scr1_top_axi.sv >> pyfive.sv
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cat ../src/top/scr1_mem_axi.sv>> pyfive.sv
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| 48 |
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yosys -g -c synth.tcl -l synth.log
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