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40 |
rrred |
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-- Z80_Soc (Z80 System on Chip)
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--
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-- Version history:
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-------------------
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-- version 0.6 for for Altera DE1
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-- Release Date: 2008 / 05 / 21
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--
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-- Version 0.5 Beta for Altera DE1
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-- Developer: Ronivon Candido Costa
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-- Release Date: 2008 / 04 / 16
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--
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-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
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-- This version developed and tested on: Altera DE1 Development Board
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--
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-- Peripherals configured (Using Ports):
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--
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-- 16 KB Internal ROM Read (0x0000h - 0x3FFFh)
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-- 08 KB INTERNAL VRAM Write (0x4000h - 0x5FFFh)
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-- 32 KB External SRAM Read/Write (0x8000h - 0xFFFFh)
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-- 08 Green Leds Out (Port 0x01h)
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-- 08 Red Leds Out (Port 0x02h)
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-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
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-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
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-- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
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-- 08 Switches In (Port 0x20h)
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-- 04 Push buttons In (Port 0x30h)
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-- 01 PS/2 keyboard In (Port 0x80h)
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-- 01 Video write port In (Port 0x90h)
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--
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-- Revision history:
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--
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-- 2008/05/23 - Modified RAM layout to support new and future improvements
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-- - Added port 0x90 to write a character to video.
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-- - Cursor x,y automatically updated after writing to port 0x90
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-- - Added port 0x91 for video cursor X
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-- - Added port 0x92 for video cursor Y
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-- - Updated ROM to demonstrate how to use these new resources
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-- - Changed ROM to support 14 bit addresses (16 Kb)
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--
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-- 2008/05/12 - Added support for the Rotary Knob
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-- - ROT_CENTER push button (Knob) reserved for RESET
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-- - The four push buttons are now available for the user (Port 0x30)
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--
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-- 2008/05/11 - Fixed access to RAM and VRAM,
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-- Released same ROM version for DE1 and S3E
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--
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-- 2008/05/01 - Added LCD support for Spartan 3E
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--
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-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
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--
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-- 2008/04/17 - Added Video support for 40x30 mode
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--
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-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
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--
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-- TO-DO:
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-- - Implement hardware control for the A/D and IO pins
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-- - Monitor program to introduce Z80 Assmebly codes and run
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-- - Serial communication, to download assembly code from PC
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-- - Add hardware support for 80x40 Video out
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-- - SD/MMC card interface to read/store data and programs
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-------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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entity TOP_DE1 is
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port(
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-- Clocks
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CLOCK_27, -- 27 MHz
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CLOCK_50, -- 50 MHz
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EXT_CLOCK : in std_logic; -- External Clock
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-- Buttons and switches
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KEY : in std_logic_vector(3 downto 0); -- Push buttons
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SW : in std_logic_vector(9 downto 0); -- Switches
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-- LED displays
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HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
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: out std_logic_vector(6 downto 0);
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LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
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LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
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-- RS-232 interface
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UART_TXD : out std_logic; -- UART transmitter
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UART_RXD : in std_logic; -- UART receiver
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-- IRDA interface
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-- IRDA_TXD : out std_logic; -- IRDA Transmitter
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IRDA_RXD : in std_logic; -- IRDA Receiver
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-- SDRAM
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DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
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DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
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DRAM_LDQM, -- Low-byte Data Mask
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DRAM_UDQM, -- High-byte Data Mask
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DRAM_WE_N, -- Write Enable
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DRAM_CAS_N, -- Column Address Strobe
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DRAM_RAS_N, -- Row Address Strobe
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DRAM_CS_N, -- Chip Select
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DRAM_BA_0, -- Bank Address 0
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DRAM_BA_1, -- Bank Address 0
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DRAM_CLK, -- Clock
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DRAM_CKE : out std_logic; -- Clock Enable
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-- FLASH
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FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
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FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
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FL_WE_N, -- Write Enable
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FL_RST_N, -- Reset
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FL_OE_N, -- Output Enable
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FL_CE_N : out std_logic; -- Chip Enable
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-- SRAM
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SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
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SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
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SRAM_UB_N, -- High-byte Data Mask
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SRAM_LB_N, -- Low-byte Data Mask
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SRAM_WE_N, -- Write Enable
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SRAM_CE_N, -- Chip Enable
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SRAM_OE_N : out std_logic; -- Output Enable
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127 |
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-- SD card interface
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128 |
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SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
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129 |
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SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
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SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
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SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
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132 |
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133 |
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-- USB JTAG link
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134 |
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TDI, -- CPLD -> FPGA (data in)
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TCK, -- CPLD -> FPGA (clk)
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136 |
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TCS : in std_logic; -- CPLD -> FPGA (CS)
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TDO : out std_logic; -- FPGA -> CPLD (data out)
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138 |
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-- I2C bus
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140 |
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I2C_SDAT : inout std_logic; -- I2C Data
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141 |
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I2C_SCLK : out std_logic; -- I2C Clock
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142 |
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143 |
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-- PS/2 port
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PS2_DAT, -- Data
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PS2_CLK : inout std_logic; -- Clock
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146 |
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147 |
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-- VGA output
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VGA_HS, -- H_SYNC
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149 |
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VGA_VS : out std_logic; -- SYNC
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VGA_R, -- Red[3:0]
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VGA_G, -- Green[3:0]
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152 |
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VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
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153 |
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-- Audio CODEC
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155 |
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AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
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AUD_ADCDAT : in std_logic; -- ADC Data
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157 |
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AUD_DACLRCK : inout std_logic; -- DAC LR Clock
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158 |
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AUD_DACDAT : out std_logic; -- DAC Data
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159 |
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AUD_BCLK : inout std_logic; -- Bit-Stream Clock
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AUD_XCK : out std_logic; -- Chip Clock
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161 |
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-- General-purpose I/O
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163 |
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GPIO_0, -- GPIO Connection 0
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GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
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);
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end TOP_DE1;
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architecture rtl of TOP_DE1 is
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component T80se
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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173 |
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T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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174 |
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IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
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);
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port(
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLKEN : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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192 |
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A : out std_logic_vector(15 downto 0);
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DI : in std_logic_vector(7 downto 0);
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194 |
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DO : out std_logic_vector(7 downto 0)
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);
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end component;
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component rom
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port (
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Clk : in std_logic;
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201 |
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A : in std_logic_vector(13 downto 0);
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D : out std_logic_vector(7 downto 0));
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end component;
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204 |
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205 |
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component Clock_357Mhz
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206 |
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PORT (
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207 |
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clock_50Mhz : IN STD_LOGIC;
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208 |
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clock_357Mhz : OUT STD_LOGIC);
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209 |
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end component;
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210 |
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211 |
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component clk_div
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PORT
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(
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clock_25Mhz : IN STD_LOGIC;
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clock_1MHz : OUT STD_LOGIC;
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216 |
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clock_100KHz : OUT STD_LOGIC;
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217 |
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clock_10KHz : OUT STD_LOGIC;
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218 |
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clock_1KHz : OUT STD_LOGIC;
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219 |
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clock_100Hz : OUT STD_LOGIC;
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220 |
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clock_10Hz : OUT STD_LOGIC;
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221 |
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clock_1Hz : OUT STD_LOGIC);
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222 |
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end component;
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223 |
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224 |
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component decoder_7seg
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225 |
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port (
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226 |
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NUMBER : in std_logic_vector(3 downto 0);
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227 |
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HEX_DISP : out std_logic_vector(6 downto 0));
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228 |
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end component;
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230 |
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component ps2kbd
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PORT (
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keyboard_clk : inout std_logic;
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keyboard_data : inout std_logic;
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234 |
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clock : in std_logic;
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clkdelay : in std_logic;
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236 |
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reset : in std_logic;
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237 |
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read : in std_logic;
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238 |
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scan_ready : out std_logic;
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239 |
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ps2_ascii_code : out std_logic_vector(7 downto 0));
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end component;
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241 |
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242 |
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component vram8k
|
243 |
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port (
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244 |
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address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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247 |
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data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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248 |
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clock_a : IN STD_LOGIC ;
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249 |
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clock_b : IN STD_LOGIC ;
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250 |
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wren_a : IN STD_LOGIC := '1';
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251 |
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wren_b : IN STD_LOGIC := '1';
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252 |
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q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
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end component;
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256 |
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COMPONENT video
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257 |
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PORT (
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258 |
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CLOCK_25 : IN STD_LOGIC;
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259 |
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VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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260 |
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VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
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261 |
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VRAM_CLOCK : OUT STD_LOGIC;
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262 |
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VRAM_WREN : OUT STD_LOGIC;
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263 |
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VGA_R,
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264 |
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VGA_G,
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265 |
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VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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266 |
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VGA_HS,
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267 |
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VGA_VS : OUT STD_LOGIC);
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268 |
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END COMPONENT;
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269 |
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270 |
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COMPONENT video_PLL
|
271 |
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PORT
|
272 |
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(
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273 |
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inclk0 : IN STD_LOGIC := '0';
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274 |
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c0 : OUT STD_LOGIC
|
275 |
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);
|
276 |
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END COMPONENT;
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277 |
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|
278 |
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signal MREQ_n : std_logic;
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279 |
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signal IORQ_n : std_logic;
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280 |
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signal RD_n : std_logic;
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281 |
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signal WR_n : std_logic;
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282 |
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signal MWr_n : std_logic;
|
283 |
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signal Rst_n_s : std_logic;
|
284 |
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signal Clk_Z80 : std_logic;
|
285 |
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signal DI_CPU : std_logic_vector(7 downto 0);
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286 |
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signal DO_CPU : std_logic_vector(7 downto 0);
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287 |
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signal A : std_logic_vector(15 downto 0);
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288 |
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signal One : std_logic;
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289 |
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|
290 |
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signal D_ROM : std_logic_vector(7 downto 0);
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291 |
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292 |
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signal clk25mhz : std_logic;
|
293 |
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signal clk1hz : std_logic;
|
294 |
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signal clk10hz : std_logic;
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295 |
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signal clk100hz : std_logic;
|
296 |
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297 |
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signal HEX_DISP0 : std_logic_vector(6 downto 0);
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298 |
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signal HEX_DISP1 : std_logic_vector(6 downto 0);
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299 |
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signal HEX_DISP2 : std_logic_vector(6 downto 0);
|
300 |
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signal HEX_DISP3 : std_logic_vector(6 downto 0);
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301 |
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302 |
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signal NUMBER0 : std_logic_vector(3 downto 0);
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303 |
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signal NUMBER1 : std_logic_vector(3 downto 0);
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304 |
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signal NUMBER2 : std_logic_vector(3 downto 0);
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305 |
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signal NUMBER3 : std_logic_vector(3 downto 0);
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306 |
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|
307 |
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signal GPIO_0_buf_in : std_logic_vector(35 downto 0);
|
308 |
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signal GPIO_1_buf_in : std_logic_vector(35 downto 0);
|
309 |
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|
310 |
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signal vram_addra : std_logic_vector(15 downto 0);
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311 |
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signal vram_addrb : std_logic_vector(12 downto 0);
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312 |
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signal vram_dina : std_logic_vector(7 downto 0);
|
313 |
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signal vram_dinb : std_logic_vector(7 downto 0);
|
314 |
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signal vram_douta : std_logic_vector(7 downto 0);
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315 |
|
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signal vram_doutb : std_logic_vector(7 downto 0);
|
316 |
|
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signal vram_wea : std_logic;
|
317 |
|
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signal vram_web : std_logic;
|
318 |
|
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signal vram_clka : std_logic;
|
319 |
|
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signal vram_clkb : std_logic;
|
320 |
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|
321 |
|
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signal vram_douta_reg : std_logic_vector(7 downto 0);
|
322 |
|
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signal VID_CURSOR : std_logic_vector(15 downto 0);
|
323 |
|
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signal CURSOR_X : std_logic_vector(5 downto 0);
|
324 |
|
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signal CURSOR_Y : std_logic_vector(4 downto 0);
|
325 |
|
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|
326 |
|
|
-- PS/2 Keyboard
|
327 |
|
|
signal ps2_read : std_logic;
|
328 |
|
|
signal ps2_scan_ready : std_logic;
|
329 |
|
|
signal ps2_ascii_sig : std_logic_vector(7 downto 0);
|
330 |
|
|
signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);
|
331 |
|
|
signal ps2_ascii_reg : std_logic_vector(7 downto 0);
|
332 |
|
|
|
333 |
|
|
signal Z80SOC_VERSION : std_logic_vector(2 downto 0); -- "000" = DE1, "001" = S3E
|
334 |
|
|
signal Z80SOC_STACK : std_logic_vector(15 downto 0); -- Should be set to top of (RAM Memory - 1)
|
335 |
|
|
|
336 |
|
|
begin
|
337 |
|
|
|
338 |
|
|
Z80SOC_VERSION <= "000"; -- "000" = DE1, "001" = S3E
|
339 |
|
|
Z80SOC_STACK <= x"FFFE"; -- Should be set to top of (RAM Memory - 1)
|
340 |
|
|
Rst_n_s <= not SW(9);
|
341 |
|
|
|
342 |
|
|
HEX0 <= HEX_DISP0;
|
343 |
|
|
HEX1 <= HEX_DISP1;
|
344 |
|
|
HEX2 <= HEX_DISP2;
|
345 |
|
|
HEX3 <= HEX_DISP3;
|
346 |
|
|
|
347 |
|
|
-- SRAM control signals
|
348 |
|
|
SRAM_ADDR(15 downto 0) <= A - x"8000" when (A >= x"8000" and MREQ_n = '0');
|
349 |
|
|
SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= x"8000") else (others => 'Z');
|
350 |
|
|
SRAM_WE_N <= Wr_n or MREQ_n when A >= x"8000";
|
351 |
|
|
SRAM_OE_N <= Rd_n;
|
352 |
|
|
|
353 |
|
|
-- VRAM control signals
|
354 |
|
|
vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90") else
|
355 |
|
|
(A - x"4000") when (A >= x"4000" and A <= x"5FFF" and MREQ_n = '0' and IORQ_n = '1') else
|
356 |
|
|
"ZZZZZZZZZZZZZZZZ";
|
357 |
|
|
vram_wea <= '0' when ((Wr_n = '0' and MREQ_n = '0' and A >= x"4000" and A <= x"5FFF") or (Wr_n = '0' and IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90")) else
|
358 |
|
|
'1';
|
359 |
|
|
vram_dina <= DO_CPU;
|
360 |
|
|
|
361 |
|
|
-- Input to Z80
|
362 |
|
|
DI_CPU <= ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDD") else
|
363 |
|
|
Z80SOC_STACK(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDE") else
|
364 |
|
|
Z80SOC_STACK(15 downto 8) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A = x"7FDF") else
|
365 |
|
|
vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A >= x"4000" and A <= x"5FFF") else
|
366 |
|
|
SRAM_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"8000") else
|
367 |
|
|
D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else
|
368 |
|
|
SW(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else
|
369 |
|
|
("0000" & not KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else
|
370 |
|
|
GPIO_0(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"A0") else
|
371 |
|
|
GPIO_0(15 downto 8) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"A1") else
|
372 |
|
|
GPIO_0(23 downto 16) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"A2") else
|
373 |
|
|
GPIO_0(31 downto 24) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"A3") else
|
374 |
|
|
("0000" & GPIO_0(35 downto 32)) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"A4") else
|
375 |
|
|
GPIO_1(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"B0") else
|
376 |
|
|
GPIO_1(15 downto 8) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"B1") else
|
377 |
|
|
GPIO_1(23 downto 16) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"B2") else
|
378 |
|
|
GPIO_1(31 downto 24) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"B3") else
|
379 |
|
|
("0000" & GPIO_1(35 downto 32)) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"B4") else
|
380 |
|
|
ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else
|
381 |
|
|
("00" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else
|
382 |
|
|
("000" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else
|
383 |
|
|
"ZZZZZZZZ";
|
384 |
|
|
|
385 |
|
|
-- Process to latch leds and hex displays
|
386 |
|
|
pinout_process: process(Clk_Z80)
|
387 |
|
|
variable NUMBER0_sig : std_logic_vector(3 downto 0);
|
388 |
|
|
variable NUMBER1_sig : std_logic_vector(3 downto 0);
|
389 |
|
|
variable NUMBER2_sig : std_logic_vector(3 downto 0);
|
390 |
|
|
variable NUMBER3_sig : std_logic_vector(3 downto 0);
|
391 |
|
|
variable LEDG_sig : std_logic_vector(7 downto 0);
|
392 |
|
|
variable LEDR_sig : std_logic_vector(9 downto 0);
|
393 |
|
|
variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
|
394 |
|
|
variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
|
395 |
|
|
begin
|
396 |
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
397 |
|
|
if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
|
398 |
|
|
-- LEDG
|
399 |
|
|
if A(7 downto 0) = x"01" then
|
400 |
|
|
LEDG_sig := DO_CPU;
|
401 |
|
|
-- LEDR
|
402 |
|
|
elsif A(7 downto 0) = x"02" then
|
403 |
|
|
LEDR_sig(7 downto 0) := DO_CPU;
|
404 |
|
|
-- HEX1 and HEX0
|
405 |
|
|
elsif A(7 downto 0) = x"10" then
|
406 |
|
|
NUMBER0_sig := DO_CPU(3 downto 0);
|
407 |
|
|
NUMBER1_sig := DO_CPU(7 downto 4);
|
408 |
|
|
-- HEX3 and HEX2
|
409 |
|
|
elsif A(7 downto 0) = x"11" then
|
410 |
|
|
NUMBER2_sig := DO_CPU(3 downto 0);
|
411 |
|
|
NUMBER3_sig := DO_CPU(7 downto 4);
|
412 |
|
|
-- GPIO_0
|
413 |
|
|
elsif A(7 downto 0) = x"A0" then
|
414 |
|
|
GPIO_0_buf_out(7 downto 0) := DO_CPU;
|
415 |
|
|
elsif A(7 downto 0) = x"A1" then
|
416 |
|
|
GPIO_0_buf_out(15 downto 8) := DO_CPU;
|
417 |
|
|
elsif A(7 downto 0) = x"A2" then
|
418 |
|
|
GPIO_0_buf_out(23 downto 16) := DO_CPU;
|
419 |
|
|
elsif A(7 downto 0) = x"A3" then
|
420 |
|
|
GPIO_0_buf_out(31 downto 24) := DO_CPU;
|
421 |
|
|
elsif A(7 downto 0) = x"A4" then
|
422 |
|
|
GPIO_0_buf_out(35 downto 32) := DO_CPU(3 downto 0);
|
423 |
|
|
-- GPIO_1
|
424 |
|
|
elsif A(7 downto 0) = x"B0" then
|
425 |
|
|
GPIO_1_buf_out(7 downto 0) := DO_CPU;
|
426 |
|
|
elsif A(7 downto 0) = x"B1" then
|
427 |
|
|
GPIO_1_buf_out(15 downto 8) := DO_CPU;
|
428 |
|
|
elsif A(7 downto 0) = x"B2" then
|
429 |
|
|
GPIO_1_buf_out(23 downto 16) := DO_CPU;
|
430 |
|
|
elsif A(7 downto 0) = x"B3" then
|
431 |
|
|
GPIO_1_buf_out(31 downto 24) := DO_CPU;
|
432 |
|
|
elsif A(7 downto 0) = x"B4" then
|
433 |
|
|
GPIO_1_buf_out(35 downto 32) := DO_CPU(3 downto 0);
|
434 |
|
|
elsif A(7 downto 0) = x"C0" then
|
435 |
|
|
GPIO_0 <= GPIO_0_buf_out;
|
436 |
|
|
elsif A(7 downto 0) = x"C1" then
|
437 |
|
|
GPIO_1 <= GPIO_1_buf_out;
|
438 |
|
|
end if;
|
439 |
|
|
end if;
|
440 |
|
|
end if;
|
441 |
|
|
-- Latches the signals
|
442 |
|
|
NUMBER0 <= NUMBER0_sig;
|
443 |
|
|
NUMBER1 <= NUMBER1_sig;
|
444 |
|
|
NUMBER2 <= NUMBER2_sig;
|
445 |
|
|
NUMBER3 <= NUMBER3_sig;
|
446 |
|
|
LEDR(7 downto 0) <= LEDR_sig(7 downto 0);
|
447 |
|
|
LEDG <= LEDG_sig;
|
448 |
|
|
end process;
|
449 |
|
|
|
450 |
|
|
-- the following three processes deals with different clock domain signals
|
451 |
|
|
ps2_process1: process(CLOCK_50)
|
452 |
|
|
begin
|
453 |
|
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
454 |
|
|
if ps2_read = '1' then
|
455 |
|
|
if ps2_ascii_sig /= x"FF" then
|
456 |
|
|
ps2_read <= '0';
|
457 |
|
|
ps2_ascii_reg1 <= "00000000";
|
458 |
|
|
end if;
|
459 |
|
|
elsif ps2_scan_ready = '1' then
|
460 |
|
|
if ps2_ascii_sig = x"FF" then
|
461 |
|
|
ps2_read <= '1';
|
462 |
|
|
else
|
463 |
|
|
ps2_ascii_reg1 <= ps2_ascii_sig;
|
464 |
|
|
end if;
|
465 |
|
|
end if;
|
466 |
|
|
end if;
|
467 |
|
|
end process;
|
468 |
|
|
|
469 |
|
|
ps2_process2: process(Clk_Z80)
|
470 |
|
|
begin
|
471 |
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
472 |
|
|
ps2_ascii_reg <= ps2_ascii_reg1;
|
473 |
|
|
end if;
|
474 |
|
|
end process;
|
475 |
|
|
|
476 |
|
|
cursorxy: process (Clk_Z80)
|
477 |
|
|
variable VID_X : std_logic_vector(5 downto 0);
|
478 |
|
|
variable VID_Y : std_logic_vector(4 downto 0);
|
479 |
|
|
begin
|
480 |
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
481 |
|
|
if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then
|
482 |
|
|
VID_X := DO_CPU(5 downto 0);
|
483 |
|
|
elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then
|
484 |
|
|
VID_Y := DO_CPU(4 downto 0);
|
485 |
|
|
elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then
|
486 |
|
|
if VID_X = "100111" then
|
487 |
|
|
VID_X := "000000";
|
488 |
|
|
if VID_Y = "11101" then
|
489 |
|
|
VID_Y := "00000";
|
490 |
|
|
else
|
491 |
|
|
VID_Y := VID_Y + 1;
|
492 |
|
|
end if;
|
493 |
|
|
else
|
494 |
|
|
VID_X := VID_X + 1;
|
495 |
|
|
end if;
|
496 |
|
|
end if;
|
497 |
|
|
end if;
|
498 |
|
|
VID_CURSOR <= x"4000" + ( VID_X + ( VID_Y * "0101000"));
|
499 |
|
|
CURSOR_X <= VID_X;
|
500 |
|
|
CURSOR_Y <= VID_Y;
|
501 |
|
|
end process;
|
502 |
|
|
|
503 |
|
|
One <= '1';
|
504 |
|
|
z80_inst: T80se
|
505 |
|
|
port map (
|
506 |
|
|
M1_n => open,
|
507 |
|
|
MREQ_n => MREQ_n,
|
508 |
|
|
IORQ_n => IORQ_n,
|
509 |
|
|
RD_n => Rd_n,
|
510 |
|
|
WR_n => Wr_n,
|
511 |
|
|
RFSH_n => open,
|
512 |
|
|
HALT_n => open,
|
513 |
|
|
WAIT_n => One,
|
514 |
|
|
INT_n => One,
|
515 |
|
|
NMI_n => One,
|
516 |
|
|
RESET_n => Rst_n_s,
|
517 |
|
|
BUSRQ_n => One,
|
518 |
|
|
BUSAK_n => open,
|
519 |
|
|
CLK_n => Clk_Z80,
|
520 |
|
|
CLKEN => One,
|
521 |
|
|
A => A,
|
522 |
|
|
DI => DI_CPU,
|
523 |
|
|
DO => DO_CPU
|
524 |
|
|
);
|
525 |
|
|
|
526 |
|
|
video_inst: video port map (
|
527 |
|
|
CLOCK_25 => clk25mhz,
|
528 |
|
|
VRAM_DATA => vram_doutb,
|
529 |
|
|
VRAM_ADDR => vram_addrb,
|
530 |
|
|
VRAM_CLOCK => vram_clkb,
|
531 |
|
|
VRAM_WREN => vram_web,
|
532 |
|
|
VGA_R => VGA_R,
|
533 |
|
|
VGA_G => VGA_G,
|
534 |
|
|
VGA_B => VGA_B,
|
535 |
|
|
VGA_HS => VGA_HS,
|
536 |
|
|
VGA_VS => VGA_VS
|
537 |
|
|
);
|
538 |
|
|
|
539 |
|
|
vram8k_inst : vram8k PORT MAP (
|
540 |
|
|
clock_a => Clk_Z80,
|
541 |
|
|
clock_b => vram_clkb,
|
542 |
|
|
wren_a => not vram_wea, -- inverted logic so code is similar to SRAM and S3E port
|
543 |
|
|
wren_b => not vram_web, -- not necessary here, because it is always low (read)
|
544 |
|
|
address_a => vram_addra(12 downto 0),
|
545 |
|
|
address_b => vram_addrb(12 downto 0),
|
546 |
|
|
data_a => vram_dina,
|
547 |
|
|
data_b => vram_dinb,
|
548 |
|
|
q_a => vram_douta,
|
549 |
|
|
q_b => vram_doutb
|
550 |
|
|
);
|
551 |
|
|
|
552 |
|
|
rom_inst: rom
|
553 |
|
|
port map (
|
554 |
|
|
Clk => Clk_Z80,
|
555 |
|
|
A => A(13 downto 0),
|
556 |
|
|
D => D_ROM
|
557 |
|
|
);
|
558 |
|
|
|
559 |
|
|
-- PLL below is used to generate the pixel clock frequency
|
560 |
|
|
-- Uses DE1 50Mhz clock for PLL's input clock
|
561 |
|
|
video_PLL_inst : video_PLL PORT MAP (
|
562 |
|
|
inclk0 => CLOCK_50,
|
563 |
|
|
c0 => clk25mhz
|
564 |
|
|
);
|
565 |
|
|
|
566 |
|
|
clkdiv_inst: clk_div
|
567 |
|
|
port map (
|
568 |
|
|
clock_25Mhz => clk25mhz,
|
569 |
|
|
clock_1MHz => open,
|
570 |
|
|
clock_100KHz => open,
|
571 |
|
|
clock_10KHz => open,
|
572 |
|
|
clock_1KHz => open,
|
573 |
|
|
clock_100Hz => clk100hz,
|
574 |
|
|
clock_10Hz => clk10hz,
|
575 |
|
|
clock_1Hz => clk1hz
|
576 |
|
|
);
|
577 |
|
|
|
578 |
|
|
clock_z80_inst : Clock_357Mhz
|
579 |
|
|
port map (
|
580 |
|
|
clock_50Mhz => CLOCK_50,
|
581 |
|
|
clock_357Mhz => Clk_Z80
|
582 |
|
|
);
|
583 |
|
|
|
584 |
|
|
DISPHEX0 : decoder_7seg PORT MAP (
|
585 |
|
|
NUMBER => NUMBER0,
|
586 |
|
|
HEX_DISP => HEX_DISP0
|
587 |
|
|
);
|
588 |
|
|
|
589 |
|
|
DISPHEX1 : decoder_7seg PORT MAP (
|
590 |
|
|
NUMBER => NUMBER1,
|
591 |
|
|
HEX_DISP => HEX_DISP1
|
592 |
|
|
);
|
593 |
|
|
|
594 |
|
|
DISPHEX2 : decoder_7seg PORT MAP (
|
595 |
|
|
NUMBER => NUMBER2,
|
596 |
|
|
HEX_DISP => HEX_DISP2
|
597 |
|
|
);
|
598 |
|
|
|
599 |
|
|
DISPHEX3 : decoder_7seg PORT MAP (
|
600 |
|
|
NUMBER => NUMBER3,
|
601 |
|
|
HEX_DISP => HEX_DISP3
|
602 |
|
|
);
|
603 |
|
|
|
604 |
|
|
ps2_kbd_inst : ps2kbd PORT MAP (
|
605 |
|
|
keyboard_clk => PS2_CLK,
|
606 |
|
|
keyboard_data => PS2_DAT,
|
607 |
|
|
clock => CLOCK_50,
|
608 |
|
|
clkdelay => clk100hz,
|
609 |
|
|
reset => Rst_n_s,
|
610 |
|
|
read => ps2_read,
|
611 |
|
|
scan_ready => ps2_scan_ready,
|
612 |
|
|
ps2_ascii_code => ps2_ascii_sig
|
613 |
|
|
);
|
614 |
|
|
|
615 |
|
|
--
|
616 |
|
|
SRAM_DQ(15 downto 8) <= (others => 'Z');
|
617 |
|
|
SRAM_ADDR(17 downto 16) <= "00";
|
618 |
|
|
SRAM_UB_N <= '1';
|
619 |
|
|
SRAM_LB_N <= '0';
|
620 |
|
|
SRAM_CE_N <= '0';
|
621 |
|
|
--
|
622 |
|
|
UART_TXD <= 'Z';
|
623 |
|
|
DRAM_ADDR <= (others => '0');
|
624 |
|
|
DRAM_LDQM <= '0';
|
625 |
|
|
DRAM_UDQM <= '0';
|
626 |
|
|
DRAM_WE_N <= '1';
|
627 |
|
|
DRAM_CAS_N <= '1';
|
628 |
|
|
DRAM_RAS_N <= '1';
|
629 |
|
|
DRAM_CS_N <= '1';
|
630 |
|
|
DRAM_BA_0 <= '0';
|
631 |
|
|
DRAM_BA_1 <= '0';
|
632 |
|
|
DRAM_CLK <= '0';
|
633 |
|
|
DRAM_CKE <= '0';
|
634 |
|
|
FL_ADDR <= (others => '0');
|
635 |
|
|
FL_WE_N <= '1';
|
636 |
|
|
FL_RST_N <= '0';
|
637 |
|
|
FL_OE_N <= '1';
|
638 |
|
|
FL_CE_N <= '1';
|
639 |
|
|
TDO <= '0';
|
640 |
|
|
I2C_SCLK <= '0';
|
641 |
|
|
AUD_DACDAT <= '0';
|
642 |
|
|
AUD_XCK <= '0';
|
643 |
|
|
-- Set all bidirectional ports to tri-state
|
644 |
|
|
DRAM_DQ <= (others => 'Z');
|
645 |
|
|
FL_DQ <= (others => 'Z');
|
646 |
|
|
I2C_SDAT <= 'Z';
|
647 |
|
|
AUD_ADCLRCK <= 'Z';
|
648 |
|
|
AUD_DACLRCK <= 'Z';
|
649 |
|
|
AUD_BCLK <= 'Z';
|
650 |
|
|
GPIO_0 <= (others => 'Z');
|
651 |
|
|
GPIO_1 <= (others => 'Z');
|
652 |
|
|
end;
|