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[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [top_s3e.vhd] - Blame information for rev 34

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-------------------------------------------------------------------------------------------------
-- Z80_Soc (Z80 System on Chip)
-- 
-- Version history:
-------------------
-- version 0.7 for Spartan 3E
-- Release Date: 2010 / 02 / 17
--
-- version 0.6 for Spartan 3E
-- Release Date: 2008 / 05 / 21
--
-- Version 0.5 Beta for Spartan 3E
-- Developer: Ronivon Candido Costa
-- Release Date: 2008 / 05 / 01
--
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
-- This version developed and tested on: Diligent Spartan 3E
--
-- Architecture of z80soc:
-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)
--
-- External devices/resources:
-- 
--      16 KB   ROM                     Read                    (0x0000h - 0x3FFFh)
--      08 KB           Video RAM               Read/Write              (0x4000h - 0x4C7Fh)
--      02 KB           Char RAM                Read/Write              (0x4C80h - 0x547FH)
--                      Not used                                        (0x5480h - 0x5FFFh)     
--      24 KB           RAM                     Read/Write              (0x6000h - 0xBFFFh)
--                      Not Used                                        (0xC000h - 0xFFDFh)
--      01              LCD display             Write                   (0xFFE0h - 0xFFFFh)
--      08              Green Leds              Out                     (Port 0x01h)
--      04              Switches                In                      (Port 0x20h)
--      04              Push buttons    In                      (Port 0x30h)
--      01              Rotary Knob             In                      (Port 0x70h)
--      01              PS/2 keyboard   In                      (Port 0x80h)
--      01              Video write             Out                     (Port 0x90h)
--
--  Revision history:
--
-- 2008/05/20 - Modified RAM layout to support new and future improvements
--            - Added port 0x90 to write a character to video.
--            - Cursor x,y automatically updated after writing to port 0x90
--            - Added port 0x91 for video cursor X
--            - Added port 0x92 for video cursor Y
--                 - Updated ROM to demonstrate how to use these new resources
--            - Changed ROM to support 14 bit addresses (16 Kb)
--
-- 2008/05/12 - Added support for the Rotary Knob
--            - ROT_CENTER push button (Knob) reserved for RESET
--            - The four push buttons are now available for the user (Port 0x30)
--
-- 2008/05/11 - Fixed access to RAM and VRAM,
--              Released same ROM version for DE1 and S3E
--
-- 2008/05/01 - Added LCD support for Spartan 3E
--
-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E
--
--      2008/04/17 - Added Video support for 40x30 mode
--
-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1
--
-- TO-DO:
-- - Implement hardware control for the A/D and IO pins
-- - Monitor program to introduce Z80 Assmebly codes and run
--      - Serial communication, to download assembly code from PC
--      - Add hardware support for 80x40 Video out
--      - SD/MMC card interface to read/store data and programs
-------------------------------------------------------------------------------------------------
 
-- use IEEE.numeric_std.all;
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
 
entity Z80SOC_TOP is
port(
        CLOCK_50        : in std_logic;
        KEY             : in std_logic_vector(3 downto 0);               -- Push buttons
        SW              : in std_logic_vector(3 downto 0);               -- Switches
        LEDG            : out std_logic_vector(7 downto 0);              -- Green LEDs
        PS2_DAT,                                                                -- Data
        PS2_CLK : inout std_logic;                              -- Clock
        VGA_HS,                                                         -- H_SYNC
        VGA_VS  : out std_logic;                                        -- SYNC
        VGA_R,                                                          -- Red[3:0]
        VGA_G,                                                          -- Green[3:0]
        VGA_B   : out std_logic;                                        -- Blue[3:0]
        SF_D            : out std_logic_vector(3 downto 0);
        LCD_E,
        LCD_RS,
        LCD_RW,
        SF_CE0  : out std_logic;
        ROT_A,
        ROT_B,
        ROT_CENTER      : in std_logic
);
end Z80SOC_TOP;
 
architecture rtl of Z80SOC_TOP is
 
        use work.z80soc_pack.all;
 
        component T80se
        generic(
                Mode                    : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
                T2Write                 : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
                IOWait          : integer := 1  -- 0 => Single cycle I/O, 1 => Std I/O cycle
        );
        port(
                RESET_n         : in std_logic;
                CLK_n                   : in std_logic;
                CLKEN                   : in std_logic;
                WAIT_n          : in std_logic;
                INT_n                   : in std_logic;
                NMI_n                   : in std_logic;
                BUSRQ_n         : in std_logic;
                M1_n                    : out std_logic;
                MREQ_n          : out std_logic;
                IORQ_n          : out std_logic;
                RD_n                    : out std_logic;
                WR_n                    : out std_logic;
                RFSH_n          : out std_logic;
                HALT_n          : out std_logic;
                BUSAK_n         : out std_logic;
                A                       : out std_logic_vector(15 downto 0);
                DI                      : in std_logic_vector(7 downto 0);
                DO                      : out std_logic_vector(7 downto 0)
        );
        end component;
 
        component ram24k
        port (
                clka                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                addra                   : IN std_logic_VECTOR(14 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0);
                douta                   : OUT std_logic_VECTOR(7 downto 0));
        end component;
 
        component rom
        port (
                Clk                     : in std_logic;
                A                       : in std_logic_vector(11 downto 0);
                D                       : out std_logic_vector(7 downto 0));
        end component;
 
        component Clock_357Mhz
        PORT (
                clock_50Mhz             : IN    STD_LOGIC;
                clock_357Mhz    : OUT   STD_LOGIC);
        end component;
 
        component clk_div
        PORT
        (
                clock_25Mhz             : IN    STD_LOGIC;
                clock_1MHz              : OUT   STD_LOGIC;
                clock_100KHz    : OUT   STD_LOGIC;
                clock_10KHz             : OUT   STD_LOGIC;
                clock_1KHz              : OUT   STD_LOGIC;
                clock_100Hz             : OUT   STD_LOGIC;
                clock_10Hz              : OUT   STD_LOGIC;
                clock_1Hz               : OUT   STD_LOGIC);
        end component;
 
        component lcd
        port(
                clk,
                reset                   : in std_logic;
                SF_D                    : out std_logic_vector(3 downto 0);
                LCD_E,
                LCD_RS,
                LCD_RW,
                SF_CE0          : out std_logic;
                lcd_addr                : out std_logic_vector(4 downto 0);
                lcd_char                : in std_logic_vector(7 downto 0));
        end component;
 
        component lcdvram
        port (
                addra                   : IN std_logic_VECTOR(4 downto 0);
                addrb                   : IN std_logic_VECTOR(4 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        component ps2kbd
        PORT (
                keyboard_clk    : inout std_logic;
                keyboard_data   : inout std_logic;
                clock                   : in std_logic;
                clkdelay                : in std_logic;
                reset                   : in std_logic;
                read                    : in std_logic;
                scan_ready              : out std_logic;
                ps2_ascii_code  : out std_logic_vector(7 downto 0));
        end component;
 
        component vram3200x8
        port (
                addra                   : IN std_logic_VECTOR(11 downto 0);
                addrb                   : IN std_logic_VECTOR(11 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                dinb                    : IN std_logic_VECTOR(7 downto 0);
                douta                   : OUT std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0);
                web                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        component charram2k
        port (
                addra                   : IN std_logic_VECTOR(10 downto 0);
                addrb                   : IN std_logic_VECTOR(10 downto 0);
                clka                    : IN std_logic;
                clkb                    : IN std_logic;
                dina                    : IN std_logic_VECTOR(7 downto 0);
                dinb                    : IN std_logic_VECTOR(7 downto 0);
                douta                   : OUT std_logic_VECTOR(7 downto 0);
                doutb                   : OUT std_logic_VECTOR(7 downto 0);
                wea                     : IN std_logic_VECTOR(0 downto 0);
                web                     : IN std_logic_VECTOR(0 downto 0));
        end component;
 
        COMPONENT video
        PORT (
                CLOCK_25                : IN STD_LOGIC;
                VRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                VRAM_ADDR               : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
                VRAM_CLOCK              : OUT STD_LOGIC;
                VRAM_WREN               : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
                CRAM_DATA               : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                CRAM_ADDR               : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
                CRAM_WEB                        : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
                VGA_R,
                VGA_G,
                VGA_B                           : OUT STD_LOGIC;
                VGA_HS,
                VGA_VS                  : OUT STD_LOGIC);
        END COMPONENT;
 
        COMPONENT ROT_CTRL
        PORT (
                CLOCK                   : IN STD_LOGIC;
                ROT_A                   : IN    STD_LOGIC;
                ROT_B                   : IN    STD_LOGIC;
                DIRECTION               : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0));
        END COMPONENT;
 
        signal MREQ_n           : std_logic := '0';
        signal IORQ_n           : std_logic := '1';
        signal RD_n                     : std_logic := '0';
        signal WR_n                     : std_logic := '1';
        signal Rst_n_s          : std_logic;
        signal Clk_Z80          : std_logic;
        signal DI_CPU           : std_logic_vector(7 downto 0);
        signal DO_CPU           : std_logic_vector(7 downto 0);
        signal A                        : std_logic_vector(15 downto 0);
        signal One                      : std_logic := '1';
 
        signal D_ROM            : std_logic_vector(7 downto 0);
 
        signal clk25mhz         : std_logic;
        signal clk100hz         : std_logic;
        signal clk10hz          : std_logic;
        signal clk1hz           : std_logic;
 
        signal vram_addra               : std_logic_vector(15 downto 0);
        signal vram_addrb               : std_logic_vector(15 downto 0);
        signal vram_dina                : std_logic_vector(7 downto 0);
        signal vram_dinb                : std_logic_vector(7 downto 0);
        signal vram_douta               : std_logic_vector(7 downto 0);
        signal vram_doutb               : std_logic_vector(7 downto 0);
        signal vram_wea         : std_logic_VECTOR(0 downto 0) := "1";
        signal vram_web         : std_logic_VECTOR(0 downto 0) := "1";
        signal vram_clka                : std_logic;
        signal vram_clkb                : std_logic;
 
        signal cram_addra               : std_logic_vector(15 downto 0);
        signal cram_addrb               : std_logic_vector(15 downto 0);
        signal cram_dina                : std_logic_vector(7 downto 0);
        signal cram_dinb                : std_logic_vector(7 downto 0);
        signal cram_douta               : std_logic_vector(7 downto 0);
        signal cram_doutb               : std_logic_vector(7 downto 0);
        signal cram_wea         : std_logic_VECTOR(0 downto 0) := "1";
        signal cram_web         : std_logic_VECTOR(0 downto 0) := "1";
        signal cram_clka                : std_logic;
        signal cram_clkb                : std_logic;
 
        signal vram_douta_reg: std_logic_vector(7 downto 0);
        signal VID_CURSOR               : std_logic_vector(15 downto 0);
        signal CURSOR_X         : std_logic_vector(6 downto 0);
        signal CURSOR_Y         : std_logic_vector(5 downto 0);
 
        -- sram signals
        signal sram_addr                : std_logic_vector(15 downto 0);
        signal sram_din         : std_logic_vector(7 downto 0);
        signal sram_dout                : std_logic_vector(7 downto 0);
        signal sram_we                  : std_logic_vector(0 downto 0) := "1";
 
        -- LCD signals
        signal lcd_wea                  : std_logic_VECTOR(0 downto 0) := "1";
        signal lcd_addra                : std_logic_vector(4 downto 0);
        signal lcd_addrb                : std_logic_vector(4 downto 0);
        signal lcd_dina         : std_logic_vector(7 downto 0);
        signal lcd_doutb                : std_logic_vector(7 downto 0);
 
        -- VGA conversion from 4 bits to 8 bit
        signal VGA_Rs,
               VGA_Gs,
               VGA_Bs           : std_logic_vector(3 downto 0);
        signal VGA_HSs,
               VGA_VSs          : std_logic;
 
        -- PS/2 Keyboard
        signal ps2_read         : std_logic;
        signal ps2_scan_ready   : std_logic;
        signal ps2_ascii_sig    : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg1   : std_logic_vector(7 downto 0);
        signal ps2_ascii_reg    : std_logic_vector(7 downto 0);
 
        -- Rotary Control
        signal rot_dir          : std_logic_vector(1 downto 0);
        signal rot_dir_sig      : std_logic_vector(1 downto 0);
 
        signal Z80SOC_VERSION           : std_logic_vector(2 downto 0);   -- "000" = DE1, "001" = S3E
 
begin
 
        Z80SOC_VERSION <= "001";                -- "000" = DE1, "001" = S3E
        Rst_n_s <= not ROT_CENTER;
 
--      Write into VRAM
        vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90")  else
                      A - x"4000" when (A >= x"4000" and A < x"4C80");
        vram_wea(0) <= '0' when ((A >= x"4000" and A < x"4C80" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else
                '1';
        vram_dina <= DO_CPU;
 
-- Write into char ram
        cram_addra      <= A - x"4C80";
        cram_dina       <= DO_CPU;
        cram_wea(0)      <= '0' when (A >= x"4C80" and A < x"5480" and Wr_n = '0' and MReq_n = '0') else '1';
 
-- Write into LCD video ram
        lcd_addra <= A - x"FFE0";
        lcd_dina <= DO_CPU;
        lcd_wea(0) <= '0' when (A >= x"FFE0" and A <= x"FFFF" and Wr_n = '0' and MReq_n = '0') else '1';
 
-- Write into SRAM
        sram_addr <= A - x"6000";
        sram_din <= DO_CPU;
        sram_we(0) <= '0' when (A >= x"6000" and A < x"C000" and Wr_n = '0' and MReq_n = '0') else '1';
 
        DI_CPU <=       ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and A = x"FFDF") else
                        D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else
                        vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"4C80") else
                        cram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"5480") else
                        sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"C000") else
                        ("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else
                        ("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else
                        ("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else
                        ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else
                        ("0" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else
                        ("00" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else
                        "ZZZZZZZZ";
 
        -- Process to latch leds and hex displays
        pinout_process: process(Clk_Z80)
        variable LEDG_sig               : std_logic_vector(7 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                  if IORQ_n = '0' and Wr_n = '0' then
                        -- LEDG
                        if A(7 downto 0) = x"01" then
                                LEDG_sig := DO_CPU;
                        end if;
                  end if;
                end if;
                -- Latches the signals
                LEDG <= LEDG_sig;
        end process;
 
        cursorxy: process (Clk_Z80)
        variable VID_X  : std_logic_vector(6 downto 0);
        variable VID_Y  : std_logic_vector(5 downto 0);
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then
                                VID_X := DO_CPU(6 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then
                                VID_Y := DO_CPU(5 downto 0);
                        elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then
                                if VID_X = vid_cols - 1 then
                                        VID_X := "0000000";
                                        if VID_Y = vid_lines - 1 then
                                                VID_Y := "000000";
                                        else
                                                VID_Y := VID_Y + 1;
                                        end if;
                                else
                                        VID_X := VID_X + 1;
                                end if;
                        end if;
                end if;
                VID_CURSOR <= vram_base_addr + ( VID_X + ( VID_Y * conv_std_logic_vector(vid_cols,7)));
                CURSOR_X <= VID_X;
                CURSOR_Y <= VID_Y;
        end process;
 
        -- the following three processes deals with different clock domain signals
        ps2_process1: process(CLOCK_50)
        begin
                if CLOCK_50'event and CLOCK_50 = '1' then
                        if ps2_read = '1' then
                                if ps2_ascii_sig /= x"FF" then
                                        ps2_read <= '0';
                                        ps2_ascii_reg1 <= "00000000";
                                end if;
                        elsif ps2_scan_ready = '1' then
                                if ps2_ascii_sig = x"FF" then
                                        ps2_read <= '1';
                                else
                                        ps2_ascii_reg1 <= ps2_ascii_sig;
                                end if;
                        end if;
                end if;
        end process;
 
        ps2_process2: process(Clk_Z80)
        variable stack  : std_logic_vector(15 downto 0):=x"7FDE";
        begin
                if Clk_Z80'event and Clk_Z80 = '1' then
                        ps2_ascii_reg <= ps2_ascii_reg1;
                end if;
        end process;
 
        rot_process: process(clk100hz)
        begin
                if clk100hz'event and clk100hz = '1' then
                        rot_dir <= rot_dir_sig;
                end if;
        end process;
 
        One <= '1';
        z80_inst: T80se
                port map (
                        M1_n => open,
                        MREQ_n => MReq_n,
                        IORQ_n => IORq_n,
                        RD_n => Rd_n,
                        WR_n => Wr_n,
                        RFSH_n => open,
                        HALT_n => open,
                        WAIT_n => One,
                        INT_n => One,
                        NMI_n => One,
                        RESET_n => Rst_n_s,
                        BUSRQ_n => One,
                        BUSAK_n => open,
                        CLK_n => Clk_Z80,
                        CLKEN => One,
                        A => A,
                        DI => DI_CPU,
                        DO => DO_CPU
                );
 
        ps2_kbd_inst : ps2kbd PORT MAP (
                keyboard_clk    => PS2_CLK,
                keyboard_data   => PS2_DAT,
                clock                   => CLOCK_50,
                clkdelay                => clk100hz,
                reset                   => Rst_n_s,
                read                    => ps2_read,
                scan_ready              => ps2_scan_ready,
                ps2_ascii_code  => ps2_ascii_sig
        );
 
        clk25mhz_proc: process (CLOCK_50)
   begin
                if CLOCK_50'event and CLOCK_50 = '1' then
        clk25mhz <= not clk25mhz;
                end if;
   end process;
 
   clkdiv_inst: clk_div
                port map (
                clock_25Mhz             => clk25mhz,
                clock_1MHz              => open,
                clock_100KHz    => open,
                clock_10KHz             => open,
                clock_1KHz              => open,
                clock_100Hz             => clk100hz,
                clock_10Hz              => clk10hz,
                clock_1Hz               => clk1hz
        );
 
        clock_z80_inst : Clock_357Mhz
        port map (
                clock_50Mhz             => CLOCK_50,
                clock_357Mhz    => Clk_Z80
        );
 
        lcd_inst: lcd
        port map (
                clk                     => CLOCK_50,
                reset                   => not Rst_n_s,
                SF_D                    => SF_D,
                LCD_E                   => LCD_E,
                LCD_RS          => LCD_RS,
                LCD_RW          => LCD_RW,
                SF_CE0          => SF_CE0,
                lcd_addr                => lcd_addrb,
                lcd_char                => lcd_doutb
        );
 
        rom_inst: rom
                port map (
                        Clk => Clk_Z80,
                        A       => A(11 downto 0),
                        D       => D_ROM
                );
 
        video_inst: video port map (
                        CLOCK_25                        => clk25mhz,
                        VRAM_DATA               => vram_doutb,
                        VRAM_ADDR               => vram_addrb(12 downto 0),
                        VRAM_CLOCK              => vram_clkb,
                        VRAM_WREN               => vram_web,
                        CRAM_DATA               => cram_doutb,
                        CRAM_ADDR               => cram_addrb(10 downto 0),
                        CRAM_WEB                        => cram_web,
                        VGA_R                           => VGA_R,
                        VGA_G                           => VGA_G,
                        VGA_B                           => VGA_B,
                        VGA_HS                  => VGA_HS,
                        VGA_VS                  => VGA_VS
        );
 
        vram : vram3200x8
                port map (
                        addra   => vram_addra(11 downto 0),
                        addrb   => vram_addrb(11 downto 0),
                        clka            => Clk_Z80,
                        clkb            => vram_clkb,
                        dina            => vram_dina,
                        dinb            => vram_dinb,
                        douta   => vram_douta,
                        doutb   => vram_doutb,
                        wea             => NOT vram_wea,
                        web             => NOT vram_web);
 
        cram: charram2k
                port map (
                        addra   => cram_addra(10 downto 0),
                        addrb   => cram_addrb(10 downto 0),
                        clka            => Clk_Z80,
                        clkb            => vram_clkb,
                        dina            => cram_dina,
                        dinb            => cram_dinb,
                        douta   => cram_douta,
                        doutb   => cram_doutb,
                        wea             => NOT cram_wea,
                        web             => NOT cram_web);
 
        lcdvram_inst : lcdvram
                port map (
                        addra => lcd_addra,
                        addrb => lcd_addrb,
                        clka => Clk_Z80,
                        clkb => CLOCK_50,
                        dina => lcd_dina,
                        doutb => lcd_doutb,
                        wea => NOT lcd_wea
                );
 
        ram : ram24k
                port map (
                        clka            => Clk_Z80,
                        dina            => sram_din,
                        addra   => sram_addr(14 downto 0),
                        wea             => NOT sram_we,
                        douta   => sram_dout);
 
        rotary_inst: ROT_CTRL
                port map (
                        CLOCK                   => CLOCK_50,
                        ROT_A                   => ROT_A,
                        ROT_B                   => ROT_B,
                        DIRECTION       => rot_dir_sig
        );
 
end;

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Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7/] [S3E/] [vhdl/] [top_s3e.vhd] - Blame information for rev 34

Line No.	Rev	Author	Line
1	34	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- Z80_Soc (Z80 System on Chip)`
3			`--`
4			`-- Version history:`
5			`-------------------`
6			`-- version 0.7 for Spartan 3E`
7			`-- Release Date: 2010 / 02 / 17`
8			`--`
9			`-- version 0.6 for Spartan 3E`
10			`-- Release Date: 2008 / 05 / 21`
11			`--`
12			`-- Version 0.5 Beta for Spartan 3E`
13			`-- Developer: Ronivon Candido Costa`
14			`-- Release Date: 2008 / 05 / 01`
15			`--`
16			`-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80`
17			`-- This version developed and tested on: Diligent Spartan 3E`
18			`--`
19			`-- Architecture of z80soc:`
20			`-- Processor: Z80 Processor (T80 core) Runnig at 3.58 Mhz (can be changed)`
21			`--`
22			`-- External devices/resources:`
23			`--`
24			`-- 16 KB ROM Read (0x0000h - 0x3FFFh)`
25			`-- 08 KB Video RAM Read/Write (0x4000h - 0x4C7Fh)`
26			`-- 02 KB Char RAM Read/Write (0x4C80h - 0x547FH)`
27			`-- Not used (0x5480h - 0x5FFFh)`
28			`-- 24 KB RAM Read/Write (0x6000h - 0xBFFFh)`
29			`-- Not Used (0xC000h - 0xFFDFh)`
30			`-- 01 LCD display Write (0xFFE0h - 0xFFFFh)`
31			`-- 08 Green Leds Out (Port 0x01h)`
32			`-- 04 Switches In (Port 0x20h)`
33			`-- 04 Push buttons In (Port 0x30h)`
34			`-- 01 Rotary Knob In (Port 0x70h)`
35			`-- 01 PS/2 keyboard In (Port 0x80h)`
36			`-- 01 Video write Out (Port 0x90h)`
37			`--`
38			`-- Revision history:`
39			`--`
40			`-- 2008/05/20 - Modified RAM layout to support new and future improvements`
41			`-- - Added port 0x90 to write a character to video.`
42			`-- - Cursor x,y automatically updated after writing to port 0x90`
43			`-- - Added port 0x91 for video cursor X`
44			`-- - Added port 0x92 for video cursor Y`
45			`-- - Updated ROM to demonstrate how to use these new resources`
46			`-- - Changed ROM to support 14 bit addresses (16 Kb)`
47			`--`
48			`-- 2008/05/12 - Added support for the Rotary Knob`
49			`-- - ROT_CENTER push button (Knob) reserved for RESET`
50			`-- - The four push buttons are now available for the user (Port 0x30)`
51			`--`
52			`-- 2008/05/11 - Fixed access to RAM and VRAM,`
53			`-- Released same ROM version for DE1 and S3E`
54			`--`
55			`-- 2008/05/01 - Added LCD support for Spartan 3E`
56			`--`
57			`-- 2008/04(21 - Release of Version 0.5-S3E-Beta for Diligent Spartan 3E`
58			`--`
59			`-- 2008/04/17 - Added Video support for 40x30 mode`
60			`--`
61			`-- 2008/04/16 - Release of Version 0.5-DE1-Beta for Altera DE1`
62			`--`
63			`-- TO-DO:`
64			`-- - Implement hardware control for the A/D and IO pins`
65			`-- - Monitor program to introduce Z80 Assmebly codes and run`
66			`-- - Serial communication, to download assembly code from PC`
67			`-- - Add hardware support for 80x40 Video out`
68			`-- - SD/MMC card interface to read/store data and programs`
69			`-------------------------------------------------------------------------------------------------`
70
71			`-- use IEEE.numeric_std.all;`
72
73			`library IEEE;`
74			`use IEEE.STD_LOGIC_1164.all;`
75			`use IEEE.STD_LOGIC_ARITH.all;`
76			`use IEEE.STD_LOGIC_UNSIGNED.all;`
77
78			`entity Z80SOC_TOP is`
79			`port(`
80			`CLOCK_50 : in std_logic;`
81			`KEY : in std_logic_vector(3 downto 0); -- Push buttons`
82			`SW : in std_logic_vector(3 downto 0); -- Switches`
83			`LEDG : out std_logic_vector(7 downto 0); -- Green LEDs`
84			`PS2_DAT, -- Data`
85			`PS2_CLK : inout std_logic; -- Clock`
86			`VGA_HS, -- H_SYNC`
87			`VGA_VS : out std_logic; -- SYNC`
88			`VGA_R, -- Red[3:0]`
89			`VGA_G, -- Green[3:0]`
90			`VGA_B : out std_logic; -- Blue[3:0]`
91			`SF_D : out std_logic_vector(3 downto 0);`
92			`LCD_E,`
93			`LCD_RS,`
94			`LCD_RW,`
95			`SF_CE0 : out std_logic;`
96			`ROT_A,`
97			`ROT_B,`
98			`ROT_CENTER : in std_logic`
99			`);`
100			`end Z80SOC_TOP;`
101
102			`architecture rtl of Z80SOC_TOP is`
103
104			`use work.z80soc_pack.all;`
105
106			`component T80se`
107			`generic(`
108			`Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB`
109			`T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2`
110			`IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle`
111			`);`
112			`port(`
113			`RESET_n : in std_logic;`
114			`CLK_n : in std_logic;`
115			`CLKEN : in std_logic;`
116			`WAIT_n : in std_logic;`
117			`INT_n : in std_logic;`
118			`NMI_n : in std_logic;`
119			`BUSRQ_n : in std_logic;`
120			`M1_n : out std_logic;`
121			`MREQ_n : out std_logic;`
122			`IORQ_n : out std_logic;`
123			`RD_n : out std_logic;`
124			`WR_n : out std_logic;`
125			`RFSH_n : out std_logic;`
126			`HALT_n : out std_logic;`
127			`BUSAK_n : out std_logic;`
128			`A : out std_logic_vector(15 downto 0);`
129			`DI : in std_logic_vector(7 downto 0);`
130			`DO : out std_logic_vector(7 downto 0)`
131			`);`
132			`end component;`
133
134			`component ram24k`
135			`port (`
136			`clka : IN std_logic;`
137			`dina : IN std_logic_VECTOR(7 downto 0);`
138			`addra : IN std_logic_VECTOR(14 downto 0);`
139			`wea : IN std_logic_VECTOR(0 downto 0);`
140			`douta : OUT std_logic_VECTOR(7 downto 0));`
141			`end component;`
142
143			`component rom`
144			`port (`
145			`Clk : in std_logic;`
146			`A : in std_logic_vector(11 downto 0);`
147			`D : out std_logic_vector(7 downto 0));`
148			`end component;`
149
150			`component Clock_357Mhz`
151			`PORT (`
152			`clock_50Mhz : IN STD_LOGIC;`
153			`clock_357Mhz : OUT STD_LOGIC);`
154			`end component;`
155
156			`component clk_div`
157			`PORT`
158			`(`
159			`clock_25Mhz : IN STD_LOGIC;`
160			`clock_1MHz : OUT STD_LOGIC;`
161			`clock_100KHz : OUT STD_LOGIC;`
162			`clock_10KHz : OUT STD_LOGIC;`
163			`clock_1KHz : OUT STD_LOGIC;`
164			`clock_100Hz : OUT STD_LOGIC;`
165			`clock_10Hz : OUT STD_LOGIC;`
166			`clock_1Hz : OUT STD_LOGIC);`
167			`end component;`
168
169			`component lcd`
170			`port(`
171			`clk,`
172			`reset : in std_logic;`
173			`SF_D : out std_logic_vector(3 downto 0);`
174			`LCD_E,`
175			`LCD_RS,`
176			`LCD_RW,`
177			`SF_CE0 : out std_logic;`
178			`lcd_addr : out std_logic_vector(4 downto 0);`
179			`lcd_char : in std_logic_vector(7 downto 0));`
180			`end component;`
181
182			`component lcdvram`
183			`port (`
184			`addra : IN std_logic_VECTOR(4 downto 0);`
185			`addrb : IN std_logic_VECTOR(4 downto 0);`
186			`clka : IN std_logic;`
187			`clkb : IN std_logic;`
188			`dina : IN std_logic_VECTOR(7 downto 0);`
189			`doutb : OUT std_logic_VECTOR(7 downto 0);`
190			`wea : IN std_logic_VECTOR(0 downto 0));`
191			`end component;`
192
193			`component ps2kbd`
194			`PORT (`
195			`keyboard_clk : inout std_logic;`
196			`keyboard_data : inout std_logic;`
197			`clock : in std_logic;`
198			`clkdelay : in std_logic;`
199			`reset : in std_logic;`
200			`read : in std_logic;`
201			`scan_ready : out std_logic;`
202			`ps2_ascii_code : out std_logic_vector(7 downto 0));`
203			`end component;`
204
205			`component vram3200x8`
206			`port (`
207			`addra : IN std_logic_VECTOR(11 downto 0);`
208			`addrb : IN std_logic_VECTOR(11 downto 0);`
209			`clka : IN std_logic;`
210			`clkb : IN std_logic;`
211			`dina : IN std_logic_VECTOR(7 downto 0);`
212			`dinb : IN std_logic_VECTOR(7 downto 0);`
213			`douta : OUT std_logic_VECTOR(7 downto 0);`
214			`doutb : OUT std_logic_VECTOR(7 downto 0);`
215			`wea : IN std_logic_VECTOR(0 downto 0);`
216			`web : IN std_logic_VECTOR(0 downto 0));`
217			`end component;`
218
219			`component charram2k`
220			`port (`
221			`addra : IN std_logic_VECTOR(10 downto 0);`
222			`addrb : IN std_logic_VECTOR(10 downto 0);`
223			`clka : IN std_logic;`
224			`clkb : IN std_logic;`
225			`dina : IN std_logic_VECTOR(7 downto 0);`
226			`dinb : IN std_logic_VECTOR(7 downto 0);`
227			`douta : OUT std_logic_VECTOR(7 downto 0);`
228			`doutb : OUT std_logic_VECTOR(7 downto 0);`
229			`wea : IN std_logic_VECTOR(0 downto 0);`
230			`web : IN std_logic_VECTOR(0 downto 0));`
231			`end component;`
232
233			`COMPONENT video`
234			`PORT (`
235			`CLOCK_25 : IN STD_LOGIC;`
236			`VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
237			`VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);`
238			`VRAM_CLOCK : OUT STD_LOGIC;`
239			`VRAM_WREN : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);`
240			`CRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);`
241			`CRAM_ADDR : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);`
242			`CRAM_WEB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);`
243			`VGA_R,`
244			`VGA_G,`
245			`VGA_B : OUT STD_LOGIC;`
246			`VGA_HS,`
247			`VGA_VS : OUT STD_LOGIC);`
248			`END COMPONENT;`
249
250			`COMPONENT ROT_CTRL`
251			`PORT (`
252			`CLOCK : IN STD_LOGIC;`
253			`ROT_A : IN STD_LOGIC;`
254			`ROT_B : IN STD_LOGIC;`
255			`DIRECTION : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));`
256			`END COMPONENT;`
257
258			`signal MREQ_n : std_logic := '0';`
259			`signal IORQ_n : std_logic := '1';`
260			`signal RD_n : std_logic := '0';`
261			`signal WR_n : std_logic := '1';`
262			`signal Rst_n_s : std_logic;`
263			`signal Clk_Z80 : std_logic;`
264			`signal DI_CPU : std_logic_vector(7 downto 0);`
265			`signal DO_CPU : std_logic_vector(7 downto 0);`
266			`signal A : std_logic_vector(15 downto 0);`
267			`signal One : std_logic := '1';`
268
269			`signal D_ROM : std_logic_vector(7 downto 0);`
270
271			`signal clk25mhz : std_logic;`
272			`signal clk100hz : std_logic;`
273			`signal clk10hz : std_logic;`
274			`signal clk1hz : std_logic;`
275
276			`signal vram_addra : std_logic_vector(15 downto 0);`
277			`signal vram_addrb : std_logic_vector(15 downto 0);`
278			`signal vram_dina : std_logic_vector(7 downto 0);`
279			`signal vram_dinb : std_logic_vector(7 downto 0);`
280			`signal vram_douta : std_logic_vector(7 downto 0);`
281			`signal vram_doutb : std_logic_vector(7 downto 0);`
282			`signal vram_wea : std_logic_VECTOR(0 downto 0) := "1";`
283			`signal vram_web : std_logic_VECTOR(0 downto 0) := "1";`
284			`signal vram_clka : std_logic;`
285			`signal vram_clkb : std_logic;`
286
287			`signal cram_addra : std_logic_vector(15 downto 0);`
288			`signal cram_addrb : std_logic_vector(15 downto 0);`
289			`signal cram_dina : std_logic_vector(7 downto 0);`
290			`signal cram_dinb : std_logic_vector(7 downto 0);`
291			`signal cram_douta : std_logic_vector(7 downto 0);`
292			`signal cram_doutb : std_logic_vector(7 downto 0);`
293			`signal cram_wea : std_logic_VECTOR(0 downto 0) := "1";`
294			`signal cram_web : std_logic_VECTOR(0 downto 0) := "1";`
295			`signal cram_clka : std_logic;`
296			`signal cram_clkb : std_logic;`
297
298			`signal vram_douta_reg: std_logic_vector(7 downto 0);`
299			`signal VID_CURSOR : std_logic_vector(15 downto 0);`
300			`signal CURSOR_X : std_logic_vector(6 downto 0);`
301			`signal CURSOR_Y : std_logic_vector(5 downto 0);`
302
303			`-- sram signals`
304			`signal sram_addr : std_logic_vector(15 downto 0);`
305			`signal sram_din : std_logic_vector(7 downto 0);`
306			`signal sram_dout : std_logic_vector(7 downto 0);`
307			`signal sram_we : std_logic_vector(0 downto 0) := "1";`
308
309			`-- LCD signals`
310			`signal lcd_wea : std_logic_VECTOR(0 downto 0) := "1";`
311			`signal lcd_addra : std_logic_vector(4 downto 0);`
312			`signal lcd_addrb : std_logic_vector(4 downto 0);`
313			`signal lcd_dina : std_logic_vector(7 downto 0);`
314			`signal lcd_doutb : std_logic_vector(7 downto 0);`
315
316			`-- VGA conversion from 4 bits to 8 bit`
317			`signal VGA_Rs,`
318			`VGA_Gs,`
319			`VGA_Bs : std_logic_vector(3 downto 0);`
320			`signal VGA_HSs,`
321			`VGA_VSs : std_logic;`
322
323			`-- PS/2 Keyboard`
324			`signal ps2_read : std_logic;`
325			`signal ps2_scan_ready : std_logic;`
326			`signal ps2_ascii_sig : std_logic_vector(7 downto 0);`
327			`signal ps2_ascii_reg1 : std_logic_vector(7 downto 0);`
328			`signal ps2_ascii_reg : std_logic_vector(7 downto 0);`
329
330			`-- Rotary Control`
331			`signal rot_dir : std_logic_vector(1 downto 0);`
332			`signal rot_dir_sig : std_logic_vector(1 downto 0);`
333
334			`signal Z80SOC_VERSION : std_logic_vector(2 downto 0); -- "000" = DE1, "001" = S3E`
335
336			`begin`
337
338			`Z80SOC_VERSION <= "001"; -- "000" = DE1, "001" = S3E`
339			`Rst_n_s <= not ROT_CENTER;`
340
341			`-- Write into VRAM`
342			`vram_addra <= VID_CURSOR when (IORQ_n = '0' and MREQ_n = '1' and A(7 downto 0) = x"90") else`
343			`A - x"4000" when (A >= x"4000" and A < x"4C80");`
344			`vram_wea(0) <= '0' when ((A >= x"4000" and A < x"4C80" and Wr_n = '0' and MReq_n = '0') or (Wr_n = '0' and IORQ_n = '0' and A(7 downto 0) = x"90")) else`
345			`'1';`
346			`vram_dina <= DO_CPU;`
347
348			`-- Write into char ram`
349			`cram_addra <= A - x"4C80";`
350			`cram_dina <= DO_CPU;`
351			`cram_wea(0) <= '0' when (A >= x"4C80" and A < x"5480" and Wr_n = '0' and MReq_n = '0') else '1';`
352
353			`-- Write into LCD video ram`
354			`lcd_addra <= A - x"FFE0";`
355			`lcd_dina <= DO_CPU;`
356			`lcd_wea(0) <= '0' when (A >= x"FFE0" and A <= x"FFFF" and Wr_n = '0' and MReq_n = '0') else '1';`
357
358			`-- Write into SRAM`
359			`sram_addr <= A - x"6000";`
360			`sram_din <= DO_CPU;`
361			`sram_we(0) <= '0' when (A >= x"6000" and A < x"C000" and Wr_n = '0' and MReq_n = '0') else '1';`
362
363			`DI_CPU <= ("00000" & Z80SOC_VERSION) when (Rd_n = '0' and MREQ_n = '0' and A = x"FFDF") else`
364			`D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"4000") else`
365			`vram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"4C80") else`
366			`cram_douta when (MREQ_n = '0' and IORQ_n = '1' and Rd_n = '0' and A < x"5480") else`
367			`sram_dout when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"C000") else`
368			`("0000" & SW) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"20") else`
369			`("0000" & KEY) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"30") else`
370			`("000000" & rot_dir) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"70") else`
371			`ps2_ascii_reg when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"80") else`
372			`("0" & CURSOR_X) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"91") else`
373			`("00" & CURSOR_Y) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"92") else`
374			`"ZZZZZZZZ";`
375
376			`-- Process to latch leds and hex displays`
377			`pinout_process: process(Clk_Z80)`
378			`variable LEDG_sig : std_logic_vector(7 downto 0);`
379			`begin`
380			`if Clk_Z80'event and Clk_Z80 = '1' then`
381			`if IORQ_n = '0' and Wr_n = '0' then`
382			`-- LEDG`
383			`if A(7 downto 0) = x"01" then`
384			`LEDG_sig := DO_CPU;`
385			`end if;`
386			`end if;`
387			`end if;`
388			`-- Latches the signals`
389			`LEDG <= LEDG_sig;`
390			`end process;`
391
392			`cursorxy: process (Clk_Z80)`
393			`variable VID_X : std_logic_vector(6 downto 0);`
394			`variable VID_Y : std_logic_vector(5 downto 0);`
395			`begin`
396			`if Clk_Z80'event and Clk_Z80 = '1' then`
397			`if (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"91") then`
398			`VID_X := DO_CPU(6 downto 0);`
399			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"92") then`
400			`VID_Y := DO_CPU(5 downto 0);`
401			`elsif (IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' and A(7 downto 0) = x"90") then`
402			`if VID_X = vid_cols - 1 then`
403			`VID_X := "0000000";`
404			`if VID_Y = vid_lines - 1 then`
405			`VID_Y := "000000";`
406			`else`
407			`VID_Y := VID_Y + 1;`
408			`end if;`
409			`else`
410			`VID_X := VID_X + 1;`
411			`end if;`
412			`end if;`
413			`end if;`
414			`VID_CURSOR <= vram_base_addr + ( VID_X + ( VID_Y * conv_std_logic_vector(vid_cols,7)));`
415			`CURSOR_X <= VID_X;`
416			`CURSOR_Y <= VID_Y;`
417			`end process;`
418
419			`-- the following three processes deals with different clock domain signals`
420			`ps2_process1: process(CLOCK_50)`
421			`begin`
422			`if CLOCK_50'event and CLOCK_50 = '1' then`
423			`if ps2_read = '1' then`
424			`if ps2_ascii_sig /= x"FF" then`
425			`ps2_read <= '0';`
426			`ps2_ascii_reg1 <= "00000000";`
427			`end if;`
428			`elsif ps2_scan_ready = '1' then`
429			`if ps2_ascii_sig = x"FF" then`
430			`ps2_read <= '1';`
431			`else`
432			`ps2_ascii_reg1 <= ps2_ascii_sig;`
433			`end if;`
434			`end if;`
435			`end if;`
436			`end process;`
437
438			`ps2_process2: process(Clk_Z80)`
439			`variable stack : std_logic_vector(15 downto 0):=x"7FDE";`
440			`begin`
441			`if Clk_Z80'event and Clk_Z80 = '1' then`
442			`ps2_ascii_reg <= ps2_ascii_reg1;`
443			`end if;`
444			`end process;`
445
446			`rot_process: process(clk100hz)`
447			`begin`
448			`if clk100hz'event and clk100hz = '1' then`
449			`rot_dir <= rot_dir_sig;`
450			`end if;`
451			`end process;`
452
453			`One <= '1';`
454			`z80_inst: T80se`
455			`port map (`
456			`M1_n => open,`
457			`MREQ_n => MReq_n,`
458			`IORQ_n => IORq_n,`
459			`RD_n => Rd_n,`
460			`WR_n => Wr_n,`
461			`RFSH_n => open,`
462			`HALT_n => open,`
463			`WAIT_n => One,`
464			`INT_n => One,`
465			`NMI_n => One,`
466			`RESET_n => Rst_n_s,`
467			`BUSRQ_n => One,`
468			`BUSAK_n => open,`
469			`CLK_n => Clk_Z80,`
470			`CLKEN => One,`
471			`A => A,`
472			`DI => DI_CPU,`
473			`DO => DO_CPU`
474			`);`
475
476			`ps2_kbd_inst : ps2kbd PORT MAP (`
477			`keyboard_clk => PS2_CLK,`
478			`keyboard_data => PS2_DAT,`
479			`clock => CLOCK_50,`
480			`clkdelay => clk100hz,`
481			`reset => Rst_n_s,`
482			`read => ps2_read,`
483			`scan_ready => ps2_scan_ready,`
484			`ps2_ascii_code => ps2_ascii_sig`
485			`);`
486
487			`clk25mhz_proc: process (CLOCK_50)`
488			`begin`
489			`if CLOCK_50'event and CLOCK_50 = '1' then`
490			`clk25mhz <= not clk25mhz;`
491			`end if;`
492			`end process;`
493
494			`clkdiv_inst: clk_div`
495			`port map (`
496			`clock_25Mhz => clk25mhz,`
497			`clock_1MHz => open,`
498			`clock_100KHz => open,`
499			`clock_10KHz => open,`
500			`clock_1KHz => open,`
501			`clock_100Hz => clk100hz,`
502			`clock_10Hz => clk10hz,`
503			`clock_1Hz => clk1hz`
504			`);`
505
506			`clock_z80_inst : Clock_357Mhz`
507			`port map (`
508			`clock_50Mhz => CLOCK_50,`
509			`clock_357Mhz => Clk_Z80`
510			`);`
511
512			`lcd_inst: lcd`
513			`port map (`
514			`clk => CLOCK_50,`
515			`reset => not Rst_n_s,`
516			`SF_D => SF_D,`
517			`LCD_E => LCD_E,`
518			`LCD_RS => LCD_RS,`
519			`LCD_RW => LCD_RW,`
520			`SF_CE0 => SF_CE0,`
521			`lcd_addr => lcd_addrb,`
522			`lcd_char => lcd_doutb`
523			`);`
524
525			`rom_inst: rom`
526			`port map (`
527			`Clk => Clk_Z80,`
528			`A => A(11 downto 0),`
529			`D => D_ROM`
530			`);`
531
532			`video_inst: video port map (`
533			`CLOCK_25 => clk25mhz,`
534			`VRAM_DATA => vram_doutb,`
535			`VRAM_ADDR => vram_addrb(12 downto 0),`
536			`VRAM_CLOCK => vram_clkb,`
537			`VRAM_WREN => vram_web,`
538			`CRAM_DATA => cram_doutb,`
539			`CRAM_ADDR => cram_addrb(10 downto 0),`
540			`CRAM_WEB => cram_web,`
541			`VGA_R => VGA_R,`
542			`VGA_G => VGA_G,`
543			`VGA_B => VGA_B,`
544			`VGA_HS => VGA_HS,`
545			`VGA_VS => VGA_VS`
546			`);`
547
548			`vram : vram3200x8`
549			`port map (`
550			`addra => vram_addra(11 downto 0),`
551			`addrb => vram_addrb(11 downto 0),`
552			`clka => Clk_Z80,`
553			`clkb => vram_clkb,`
554			`dina => vram_dina,`
555			`dinb => vram_dinb,`
556			`douta => vram_douta,`
557			`doutb => vram_doutb,`
558			`wea => NOT vram_wea,`
559			`web => NOT vram_web);`
560
561			`cram: charram2k`
562			`port map (`
563			`addra => cram_addra(10 downto 0),`
564			`addrb => cram_addrb(10 downto 0),`
565			`clka => Clk_Z80,`
566			`clkb => vram_clkb,`
567			`dina => cram_dina,`
568			`dinb => cram_dinb,`
569			`douta => cram_douta,`
570			`doutb => cram_doutb,`
571			`wea => NOT cram_wea,`
572			`web => NOT cram_web);`
573
574			`lcdvram_inst : lcdvram`
575			`port map (`
576			`addra => lcd_addra,`
577			`addrb => lcd_addrb,`
578			`clka => Clk_Z80,`
579			`clkb => CLOCK_50,`
580			`dina => lcd_dina,`
581			`doutb => lcd_doutb,`
582			`wea => NOT lcd_wea`
583			`);`
584
585			`ram : ram24k`
586			`port map (`
587			`clka => Clk_Z80,`
588			`dina => sram_din,`
589			`addra => sram_addr(14 downto 0),`
590			`wea => NOT sram_we,`
591			`douta => sram_dout);`
592
593			`rotary_inst: ROT_CTRL`
594			`port map (`
595			`CLOCK => CLOCK_50,`
596			`ROT_A => ROT_A,`
597			`ROT_B => ROT_B,`
598			`DIRECTION => rot_dir_sig`
599			`);`
600
601			`end;`