OpenCores
URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.2/] [DE1/] [memoryCores/] [vram3200x8.cmp] - Blame information for rev 44

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 44 rrred
--Copyright (C) 1991-2010 Altera Corporation
2
--Your use of Altera Corporation's design tools, logic functions
3
--and other software and tools, and its AMPP partner logic
4
--functions, and any output files from any of the foregoing
5
--(including device programming or simulation files), and any
6
--associated documentation or information are expressly subject
7
--to the terms and conditions of the Altera Program License
8
--Subscription Agreement, Altera MegaCore Function License
9
--Agreement, or other applicable license agreement, including,
10
--without limitation, that your use is for the sole purpose of
11
--programming logic devices manufactured by Altera and sold by
12
--Altera or its authorized distributors.  Please refer to the
13
--applicable agreement for further details.
14
 
15
 
16
component vram3200x8
17
        PORT
18
        (
19
                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
20
                rdaddress               : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
21
                rdclock         : IN STD_LOGIC ;
22
                wraddress               : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
23
                wrclock         : IN STD_LOGIC  := '1';
24
                wren            : IN STD_LOGIC  := '0';
25
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
26
        );
27
end component;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.