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[/] [z80soc/] [trunk/] [V0.7.2/] [DE1/] [vhdl/] [clk_div.vhd] - Blame information for rev 44

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-------------------------------------------------------------------------------------------------
-- This design is part of:
-- Z80SoC (Z80 System on Chip)
-- Ronivon Candido Costa
-- ronivon.costa@gmail.com
--
 
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;
 
ENTITY clk_div IS
 
        PORT
        (
                clock_25Mhz                             : IN    STD_LOGIC;
                clock_1MHz                              : OUT   STD_LOGIC;
                clock_100KHz                    : OUT   STD_LOGIC;
                clock_10KHz                             : OUT   STD_LOGIC;
                clock_1KHz                              : OUT   STD_LOGIC;
                clock_100Hz                             : OUT   STD_LOGIC;
                clock_10Hz                              : OUT   STD_LOGIC;
                clock_1Hz                               : OUT   STD_LOGIC);
 
END clk_div;
 
ARCHITECTURE a OF clk_div IS
 
        SIGNAL  count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
        SIGNAL  count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
        SIGNAL  clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
        SIGNAL  clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
BEGIN
        PROCESS
        BEGIN
-- Divide by 25
                WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
                        IF count_1Mhz < 24 THEN
                                count_1Mhz <= count_1Mhz + 1;
                        ELSE
                                count_1Mhz <= "00000";
                        END IF;
                        IF count_1Mhz < 12 THEN
                                clock_1Mhz_int <= '0';
                        ELSE
                                clock_1Mhz_int <= '1';
                        END IF;
 
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
                        clock_1Mhz <= clock_1Mhz_int;
                        clock_100Khz <= clock_100Khz_int;
                        clock_10Khz <= clock_10Khz_int;
                        clock_1Khz <= clock_1Khz_int;
                        clock_100hz <= clock_100hz_int;
                        clock_10hz <= clock_10hz_int;
                        clock_1hz <= clock_1hz_int;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
                        IF count_100Khz /= 4 THEN
                                count_100Khz <= count_100Khz + 1;
                        ELSE
                                count_100khz <= "000";
                                clock_100Khz_int <= NOT clock_100Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
                        IF count_10Khz /= 4 THEN
                                count_10Khz <= count_10Khz + 1;
                        ELSE
                                count_10khz <= "000";
                                clock_10Khz_int <= NOT clock_10Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
                        IF count_1Khz /= 4 THEN
                                count_1Khz <= count_1Khz + 1;
                        ELSE
                                count_1khz <= "000";
                                clock_1Khz_int <= NOT clock_1Khz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
                        IF count_100hz /= 4 THEN
                                count_100hz <= count_100hz + 1;
                        ELSE
                                count_100hz <= "000";
                                clock_100hz_int <= NOT clock_100hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
                        IF count_10hz /= 4 THEN
                                count_10hz <= count_10hz + 1;
                        ELSE
                                count_10hz <= "000";
                                clock_10hz_int <= NOT clock_10hz_int;
                        END IF;
        END PROCESS;
 
-- Divide by 10
        PROCESS
        BEGIN
                WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
                        IF count_1hz /= 4 THEN
                                count_1hz <= count_1hz + 1;
                        ELSE
                                count_1hz <= "000";
                                clock_1hz_int <= NOT clock_1hz_int;
                        END IF;
        END PROCESS;
 
END a;
 

Line No.	Rev	Author	Line
1	44	rrred	`-------------------------------------------------------------------------------------------------`
2			`-- This design is part of:`
3			`-- Z80SoC (Z80 System on Chip)`
4			`-- Ronivon Candido Costa`
5			`-- ronivon.costa@gmail.com`
6			`--`
7
8			`library IEEE;`
9			`use IEEE.STD_LOGIC_1164.all;`
10			`use IEEE.STD_LOGIC_ARITH.all;`
11			`use IEEE.STD_LOGIC_UNSIGNED.all;`
12
13			`ENTITY clk_div IS`
14
15			`PORT`
16			`(`
17			`clock_25Mhz : IN STD_LOGIC;`
18			`clock_1MHz : OUT STD_LOGIC;`
19			`clock_100KHz : OUT STD_LOGIC;`
20			`clock_10KHz : OUT STD_LOGIC;`
21			`clock_1KHz : OUT STD_LOGIC;`
22			`clock_100Hz : OUT STD_LOGIC;`
23			`clock_10Hz : OUT STD_LOGIC;`
24			`clock_1Hz : OUT STD_LOGIC);`
25
26			`END clk_div;`
27
28			`ARCHITECTURE a OF clk_div IS`
29
30			`SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);`
31			`SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
32			`SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);`
33			`SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;`
34			`SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;`
35			`BEGIN`
36			`PROCESS`
37			`BEGIN`
38			`-- Divide by 25`
39			`WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';`
40			`IF count_1Mhz < 24 THEN`
41			`count_1Mhz <= count_1Mhz + 1;`
42			`ELSE`
43			`count_1Mhz <= "00000";`
44			`END IF;`
45			`IF count_1Mhz < 12 THEN`
46			`clock_1Mhz_int <= '0';`
47			`ELSE`
48			`clock_1Mhz_int <= '1';`
49			`END IF;`
50
51			`-- Ripple clocks are used in this code to save prescalar hardware`
52			`-- Sync all clock prescalar outputs back to master clock signal`
53			`clock_1Mhz <= clock_1Mhz_int;`
54			`clock_100Khz <= clock_100Khz_int;`
55			`clock_10Khz <= clock_10Khz_int;`
56			`clock_1Khz <= clock_1Khz_int;`
57			`clock_100hz <= clock_100hz_int;`
58			`clock_10hz <= clock_10hz_int;`
59			`clock_1hz <= clock_1hz_int;`
60			`END PROCESS;`
61
62			`-- Divide by 10`
63			`PROCESS`
64			`BEGIN`
65			`WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';`
66			`IF count_100Khz /= 4 THEN`
67			`count_100Khz <= count_100Khz + 1;`
68			`ELSE`
69			`count_100khz <= "000";`
70			`clock_100Khz_int <= NOT clock_100Khz_int;`
71			`END IF;`
72			`END PROCESS;`
73
74			`-- Divide by 10`
75			`PROCESS`
76			`BEGIN`
77			`WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';`
78			`IF count_10Khz /= 4 THEN`
79			`count_10Khz <= count_10Khz + 1;`
80			`ELSE`
81			`count_10khz <= "000";`
82			`clock_10Khz_int <= NOT clock_10Khz_int;`
83			`END IF;`
84			`END PROCESS;`
85
86			`-- Divide by 10`
87			`PROCESS`
88			`BEGIN`
89			`WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';`
90			`IF count_1Khz /= 4 THEN`
91			`count_1Khz <= count_1Khz + 1;`
92			`ELSE`
93			`count_1khz <= "000";`
94			`clock_1Khz_int <= NOT clock_1Khz_int;`
95			`END IF;`
96			`END PROCESS;`
97
98			`-- Divide by 10`
99			`PROCESS`
100			`BEGIN`
101			`WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';`
102			`IF count_100hz /= 4 THEN`
103			`count_100hz <= count_100hz + 1;`
104			`ELSE`
105			`count_100hz <= "000";`
106			`clock_100hz_int <= NOT clock_100hz_int;`
107			`END IF;`
108			`END PROCESS;`
109
110			`-- Divide by 10`
111			`PROCESS`
112			`BEGIN`
113			`WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';`
114			`IF count_10hz /= 4 THEN`
115			`count_10hz <= count_10hz + 1;`
116			`ELSE`
117			`count_10hz <= "000";`
118			`clock_10hz_int <= NOT clock_10hz_int;`
119			`END IF;`
120			`END PROCESS;`
121
122			`-- Divide by 10`
123			`PROCESS`
124			`BEGIN`
125			`WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';`
126			`IF count_1hz /= 4 THEN`
127			`count_1hz <= count_1hz + 1;`
128			`ELSE`
129			`count_1hz <= "000";`
130			`clock_1hz_int <= NOT clock_1hz_int;`
131			`END IF;`
132			`END PROCESS;`
133
134			`END a;`
135

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[/] [z80soc/] [trunk/] [V0.7.2/] [DE1/] [vhdl/] [clk_div.vhd] - Blame information for rev 44