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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [vhdl/] [T80sed.vhd] - Blame information for rev 46

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Line No. Rev Author Line
1 46 rrred
-- ****
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-- T80(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 300 started tidyup
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
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--
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-- Z80 compatible microprocessor core, synchronous top level with clock enable
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-- Different timing than the original z80
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-- Inputs needs to be synchronous and outputs may glitch
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--
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-- Version : 0238
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- Limitations :
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--
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-- File history :
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--
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--      0235 : First release
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--
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--      0236 : Added T2Write generic
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--
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--      0237 : Fixed T2Write with wait state
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--
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--      0238 : Updated for T80 interface change
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--
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--      0242 : Updated for T80 interface change
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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entity T80sed is
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        port(
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                RESET_n         : in  std_logic;
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                CLK_n           : in  std_logic;
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                CLKEN           : in  std_logic;
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                WAIT_n          : in  std_logic;
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                INT_n           : in  std_logic;
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                NMI_n           : in  std_logic;
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                BUSRQ_n         : in  std_logic;
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                M1_n            : out std_logic;
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                MREQ_n          : out std_logic;
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                IORQ_n          : out std_logic;
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                RD_n            : out std_logic;
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                WR_n            : out std_logic;
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                RFSH_n          : out std_logic;
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                HALT_n          : out std_logic;
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                BUSAK_n         : out std_logic;
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                A               : out std_logic_vector(15 downto 0);
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                DI              : in  std_logic_vector(7 downto 0);
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                DO              : out std_logic_vector(7 downto 0)
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        );
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end T80sed;
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architecture rtl of T80sed is
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        signal IntCycle_n   : std_logic;
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        signal NoRead       : std_logic;
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        signal Write        : std_logic;
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        signal IORQ         : std_logic;
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        signal DI_Reg       : std_logic_vector(7 downto 0);
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        signal MCycle       : std_logic_vector(2 downto 0);
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        signal TState       : std_logic_vector(2 downto 0);
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begin
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        u0 : T80
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                generic map(
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                        Mode      => 0,
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                        IOWait    => 1)
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                port map(
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                        CEN        => CLKEN,
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                        M1_n       => M1_n,
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                        IORQ       => IORQ,
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                        NoRead     => NoRead,
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                        Write      => Write,
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                        RFSH_n     => RFSH_n,
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                        HALT_n     => HALT_n,
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                        WAIT_n     => Wait_n,
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                        INT_n      => INT_n,
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                        NMI_n      => NMI_n,
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                        RESET_n    => RESET_n,
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                        BUSRQ_n    => BUSRQ_n,
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                        BUSAK_n    => BUSAK_n,
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                        CLK_n      => CLK_n,
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                        A          => A,
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                        DInst      => DI,
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                        DI         => DI_Reg,
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                        DO         => DO,
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                        MC         => MCycle,
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                        TS         => TState,
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                        IntCycle_n => IntCycle_n);
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        process (RESET_n, CLK_n)
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        begin
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                if RESET_n = '0' then
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                        RD_n <= '1';
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                        WR_n <= '1';
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                        IORQ_n <= '1';
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                        MREQ_n <= '1';
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                        DI_Reg <= "00000000";
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                elsif CLK_n'event and CLK_n = '1' then
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                        if CLKEN = '1' then
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                                RD_n <= '1';
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                                WR_n <= '1';
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                                IORQ_n <= '1';
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                                MREQ_n <= '1';
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                                if MCycle = "001" then
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                                        if TState = "001" or (TState = "010" and Wait_n = '0') then
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                                                RD_n <= not IntCycle_n;
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                                                MREQ_n <= not IntCycle_n;
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                                                IORQ_n <= IntCycle_n;
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                                        end if;
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                                        if TState = "011" then
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                                                MREQ_n <= '0';
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                                        end if;
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                                else
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                                        if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
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                                                RD_n <= '0';
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                                                IORQ_n <= not IORQ;
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                                                MREQ_n <= IORQ;
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                                        end if;
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                                                if ((TState = "001") or (TState = "010")) and Write = '1' then
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                                                        WR_n <= '0';
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                                                        IORQ_n <= not IORQ;
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                                                        MREQ_n <= IORQ;
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                                                end if;
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                                end if;
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                                if TState = "010" and Wait_n = '1' then
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                                        DI_Reg <= DI;
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                                end if;
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                        end if;
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                end if;
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        end process;
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end;

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