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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_fsm.v] - Blame information for rev 52

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1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
11
// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
21
// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                         --
24
// -- This is the core state machine for the memory subsystem. Talks to both  --
25
// -- processor and the TLB controller. Cache uploads and downloads are done  --
26
// -- using an incrementing burst on the Wishbone bus for maximum efficiency  --
27
// --                                                                         --   
28
// -----------------------------------------------------------------------------
29
 
30
`default_nettype none
31
 
32
`include "zap_defines.vh"
33
 
34
module zap_cache_fsm   #(
35 43 Revanth
        parameter CACHE_SIZE    = 1024  // Bytes.
36
)
37 26 Revanth
 
38 43 Revanth
// ---------------------------------------------- 
39
//  Port List 
40
// ----------------------------------------------        
41
 
42
(
43
 
44 26 Revanth
/* Clock and reset */
45
input   wire                      i_clk,
46
input   wire                      i_reset,
47
 
48
/* From/to processor */
49
input   wire    [31:0]            i_address,
50
input   wire                      i_rd,
51
input   wire                      i_wr,
52
input   wire    [31:0]            i_din,
53
input   wire    [3:0]             i_ben, /* Valid only for writes. */
54
output  reg     [31:0]            o_dat,
55
output  reg                       o_ack,
56
output  reg                       o_err,
57
output  reg     [7:0]             o_fsr,
58
output  reg     [31:0]            o_far,
59
 
60
/* From/To CP15 unit */
61
input   wire                      i_cache_en,
62
input   wire                      i_cache_inv,
63
input   wire                      i_cache_clean,
64
output  reg                       o_cache_inv_done,
65
output  reg                       o_cache_clean_done,
66
 
67
/* From/to cache. */
68
input   wire    [127:0]           i_cache_line,
69
 
70
input   wire                      i_cache_tag_dirty,
71
input   wire  [`CACHE_TAG_WDT-1:0] i_cache_tag, // Tag 
72
input   wire                      i_cache_tag_valid,
73
 
74
output  reg   [`CACHE_TAG_WDT-1:0] o_cache_tag,
75
output  reg                       o_cache_tag_dirty,
76
output  reg                       o_cache_tag_wr_en,
77
 
78
output  reg     [127:0]           o_cache_line,
79
output  reg     [15:0]            o_cache_line_ben,    /* Write + Byte enable */
80
 
81
output  reg                       o_cache_clean_req,
82
input   wire                      i_cache_clean_done,
83
 
84
output  reg                       o_cache_inv_req,
85
input   wire                      i_cache_inv_done,
86
 
87
/* From/to TLB unit */
88
input   wire    [31:0]            i_phy_addr,
89
input   wire    [7:0]             i_fsr,
90
input   wire    [31:0]            i_far,
91
input   wire                      i_fault,
92
input   wire                      i_cacheable,
93
input   wire                      i_busy,
94
 
95
/* Memory access ports, both NXT and FF. Usually you'll be connecting NXT ports */
96
output  reg             o_wb_cyc_ff, o_wb_cyc_nxt,
97
output  reg             o_wb_stb_ff, o_wb_stb_nxt,
98
output  reg     [31:0]  o_wb_adr_ff, o_wb_adr_nxt,
99
output  reg     [31:0]  o_wb_dat_ff, o_wb_dat_nxt,
100
output  reg     [3:0]   o_wb_sel_ff, o_wb_sel_nxt,
101
output  reg             o_wb_wen_ff, o_wb_wen_nxt,
102
output  reg     [2:0]   o_wb_cti_ff, o_wb_cti_nxt,/* Cycle Type Indicator - 010, 111 */
103
input   wire            i_wb_ack,
104
input   wire    [31:0]  i_wb_dat
105
 
106
);
107
 
108 52 Revanth
// ----------------------------------------------------------------------------
109 43 Revanth
// Includes and Localparams
110 52 Revanth
// ----------------------------------------------------------------------------
111 43 Revanth
 
112 26 Revanth
`include "zap_localparams.vh"
113
`include "zap_defines.vh"
114
`include "zap_functions.vh"
115
 
116
/* States */
117
localparam IDLE                 = 0; /* Resting state. */
118
localparam UNCACHEABLE          = 1; /* Uncacheable access. */
119
localparam REFRESH_1            = 2; /* Cache write hit state. Unused. */
120
localparam CLEAN_SINGLE         = 3; /* Ultimately cleans up cache line. Parent state */
121
localparam FETCH_SINGLE         = 4; /* Ultimately validates cache line. Parent state */
122
localparam REFRESH              = 5; /* Cache refresh parent state */
123
localparam INVALIDATE           = 6; /* Cache invalidate parent state */
124
localparam CLEAN                = 7; /* Cache clean parent state */
125
localparam NUMBER_OF_STATES     = 8;
126
 
127 51 Revanth
// ----------------------------------------------------------------------------
128 43 Revanth
// Signal aliases   
129 51 Revanth
// ----------------------------------------------------------------------------
130 26 Revanth
 
131 43 Revanth
wire cache_cmp   = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
132
wire cache_dirty = i_cache_tag_dirty;
133 26 Revanth
 
134 51 Revanth
// ----------------------------------------------------------------------------
135 43 Revanth
// Variables
136 51 Revanth
// ----------------------------------------------------------------------------
137 26 Revanth
 
138 43 Revanth
reg [$clog2(NUMBER_OF_STATES)-1:0]      state_ff, state_nxt;
139
reg [31:0]                              buf_ff [3:0];
140
reg [31:0]                              buf_nxt[3:0];
141
reg                                     cache_clean_req_nxt,
142
                                        cache_clean_req_ff;
143
reg                                     cache_inv_req_nxt,
144
                                        cache_inv_req_ff;
145
reg [2:0]                               adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3 AND 4(nxt).
146
reg                                     hit;                     // For debug only.
147
 
148 51 Revanth
// ----------------------------------------------------------------------------
149 43 Revanth
// Logic
150 51 Revanth
// ----------------------------------------------------------------------------
151 43 Revanth
 
152
/* Tie flops to the output */
153 26 Revanth
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
154 51 Revanth
always @* o_cache_inv_req   = cache_inv_req_ff;   // Tie inv flop to output.
155 26 Revanth
 
156 43 Revanth
/* Sequential Block */
157 26 Revanth
always @ (posedge i_clk)
158
begin
159
        if ( i_reset )
160
        begin
161 43 Revanth
                o_wb_cyc_ff             <= 0;
162
                o_wb_stb_ff             <= 0;
163
                o_wb_wen_ff             <= 0;
164
                o_wb_sel_ff             <= 0;
165
                o_wb_dat_ff             <= 0;
166
                o_wb_cti_ff             <= CTI_CLASSIC;
167
                o_wb_adr_ff             <= 0;
168
                cache_clean_req_ff      <= 0;
169
                cache_inv_req_ff        <= 0;
170
                adr_ctr_ff              <= 0;
171
                state_ff                <= IDLE;
172 26 Revanth
        end
173
        else
174
        begin
175
                o_wb_cyc_ff             <= o_wb_cyc_nxt;
176
                o_wb_stb_ff             <= o_wb_stb_nxt;
177
                o_wb_wen_ff             <= o_wb_wen_nxt;
178
                o_wb_sel_ff             <= o_wb_sel_nxt;
179
                o_wb_dat_ff             <= o_wb_dat_nxt;
180
                o_wb_cti_ff             <= o_wb_cti_nxt;
181
                o_wb_adr_ff             <= o_wb_adr_nxt;
182
                cache_clean_req_ff      <= cache_clean_req_nxt;
183
                cache_inv_req_ff        <= cache_inv_req_nxt;
184
                adr_ctr_ff              <= adr_ctr_nxt;
185
                state_ff                <= state_nxt;
186
                buf_ff[0]               <= buf_nxt[0];
187
                buf_ff[1]               <= buf_nxt[1];
188
                buf_ff[2]               <= buf_nxt[2];
189 29 Revanth
                buf_ff[3]               <= buf_nxt[3];
190 26 Revanth
        end
191
end
192
 
193 43 Revanth
/* Combo block */
194 26 Revanth
always @*
195
begin
196
        /* Default values */
197
        state_nxt               = state_ff;
198
        adr_ctr_nxt             = adr_ctr_ff;
199
        o_wb_cyc_nxt            = o_wb_cyc_ff;
200
        o_wb_stb_nxt            = o_wb_stb_ff;
201
        o_wb_adr_nxt            = o_wb_adr_ff;
202
        o_wb_dat_nxt            = o_wb_dat_ff;
203
        o_wb_cti_nxt            = o_wb_cti_ff;
204
        o_wb_wen_nxt            = o_wb_wen_ff;
205
        o_wb_sel_nxt            = o_wb_sel_ff;
206
        cache_clean_req_nxt     = cache_clean_req_ff;
207
        cache_inv_req_nxt       = cache_clean_req_ff;
208 43 Revanth
        o_fsr                   = 0;
209
        o_far                   = 0;
210
        o_cache_tag             = 0;
211
        o_cache_inv_done        = 0;
212
        o_cache_clean_done      = 0;
213
        o_cache_tag_dirty       = 0;
214
        o_cache_tag_wr_en       = 0;
215
        o_cache_line            = 0;
216
        o_cache_line_ben        = 0;
217
        o_dat                   = 0;
218
        o_ack                   = 0;
219
        o_err                   = 0;
220
        buf_nxt[0]              = buf_ff[0];
221
        buf_nxt[1]              = buf_ff[1];
222
        buf_nxt[2]              = buf_ff[2];
223
        buf_nxt[3]              = buf_ff[3];
224
        hit                     = 0;
225 26 Revanth
 
226
        case(state_ff)
227
 
228
        IDLE:
229
        begin
230
                kill_access;
231
 
232
                if ( i_cache_inv )
233
                begin
234
                        o_ack     = 1'd0;
235
                        state_nxt = INVALIDATE;
236
                end
237
                else if ( i_cache_clean )
238
                begin
239
                        o_ack     = 1'd0;
240
                        state_nxt = CLEAN;
241
                end
242
                else if ( i_fault )
243
                begin
244
                        /* MMU access fault. */
245
                        o_err = 1'd1;
246
                        o_ack = 1'd1;
247 29 Revanth
                        o_fsr = i_fsr;
248
                        o_far = i_far;
249 26 Revanth
                end
250
                else if ( i_busy )
251
                begin
252
                        /* Wait it out */
253
                end
254
                else if ( i_rd || i_wr )
255
                begin
256
                        if ( i_cacheable && i_cache_en )
257
                        begin
258
                                case ({cache_cmp,i_cache_tag_valid})
259
 
260
                                2'b11: /* Cache hit */
261
                                begin
262
                                        if ( i_rd ) /* Read request. */
263
                                        begin
264 52 Revanth
                                                /*
265
                                                 * Accelerate performance
266
                                                 * Read throughput at 80MHz
267
                                                 * clock is 80M operations per
268
                                                 * second (Hit).
269
                                                 */
270 26 Revanth
                                                o_dat   = adapt_cache_data(i_address[3:2], i_cache_line);
271 52 Revanth
                                                hit     = 1'd1;
272 26 Revanth
                                                o_ack   = 1'd1;
273
                                        end
274
                                        else if ( i_wr ) /* Write request */
275
                                        begin
276
                                                state_nxt    = REFRESH_1;
277
                                                o_ack        = 1'd0;
278
 
279 52 Revanth
                                                /*
280
                                                 * Each write to cache takes
281
                                                 * 3 cycles. Write throuput at
282
                                                 * 80MHz is 26.6M operations per
283
                                                 * second (Hit).
284
                                                 */
285 26 Revanth
                                                o_cache_line =
286
                                                {i_din,i_din,i_din,i_din};
287
 
288
                                                o_cache_line_ben  = ben_comp ( i_address[3:2], i_ben );
289
 
290
                                                /* Write to tag and also write out physical address. */
291
                                                o_cache_tag_wr_en               = 1'd1;
292
                                                o_cache_tag[`CACHE_TAG__TAG]    = i_address[`VA__CACHE_TAG];
293
                                                o_cache_tag_dirty               = 1'd1;
294
                                                o_cache_tag[`CACHE_TAG__PA]     = i_phy_addr >> 4;
295
 
296
 
297
                                        end
298
                                end
299
 
300
                                2'b01: /* Unrelated tag, possibly dirty. */
301
                                begin
302
                                        /* CPU should wait */
303
                                        o_ack = 1'd0;
304
 
305
                                        if ( cache_dirty )
306
                                        begin
307
                                                /* Set up counter */
308
                                                adr_ctr_nxt = 0;
309
 
310
                                                /* Clean a single cache line */
311
                                                state_nxt = CLEAN_SINGLE;
312
                                        end
313
                                        else if ( i_rd | i_wr )
314
                                        begin
315
                                                /* Set up counter */
316
                                                adr_ctr_nxt = 0;
317
 
318
                                                /* Fetch a single cache line */
319
                                                state_nxt = FETCH_SINGLE;
320
                                        end
321
                                end
322
 
323
                                default: /* Need to generate a new tag. */
324
                                begin
325
                                                /* CPU should wait. */
326
                                                o_ack = 1'd0;
327
 
328
                                                /* Set up counter */
329
                                                adr_ctr_nxt = 0;
330
 
331
                                                /* Fetch a single cache line */
332
                                                state_nxt = FETCH_SINGLE;
333
                                end
334
                                endcase
335
                        end
336
                        else /* Decidedly non cacheable. */
337
                        begin
338
                                state_nxt       = UNCACHEABLE;
339
                                o_ack           = 1'd0; /* Wait...*/
340
                                o_wb_stb_nxt    = 1'd1;
341
                                o_wb_cyc_nxt    = 1'd1;
342
                                o_wb_adr_nxt    = i_phy_addr;
343
                                o_wb_dat_nxt    = i_din;
344
                                o_wb_wen_nxt    = i_wr;
345 29 Revanth
                                o_wb_sel_nxt    = i_ben; // Was i_wr ? i_ben : 4'b1111
346 26 Revanth
                                o_wb_cti_nxt    = CTI_CLASSIC;
347
                        end
348
                end
349
        end
350
 
351
        UNCACHEABLE: /* Uncacheable reads and writes definitely go through this. */
352
        begin
353
                if ( i_wb_ack )
354
                begin
355
                        o_dat           = i_wb_dat;
356
                        o_ack           = 1'd1;
357
                        state_nxt       = IDLE;
358
                        kill_access;
359
                end
360
        end
361
 
362
        REFRESH_1: /* A single wait state is needed to handle B2B write-read */
363
        begin
364
                kill_access;
365
                state_nxt = REFRESH;
366
                o_ack     = 1'd0;
367
        end
368
 
369
        CLEAN_SINGLE: /* Clean single cache line */
370
        begin
371
                o_ack = 1'd0;
372
 
373
                /* Generate address */
374
                adr_ctr_nxt = adr_ctr_ff + (o_wb_stb_ff && i_wb_ack);
375
 
376
                if ( adr_ctr_nxt <= 3 )
377
                begin
378
                        /* Sync up with memory. Use PA in cache tag itself. */
379
                        wb_prpr_write( clean_single_d (i_cache_line, adr_ctr_nxt),
380
                                      {i_cache_tag[`CACHE_TAG__PA], 4'd0} + (adr_ctr_nxt << 2),
381
                                      adr_ctr_nxt != 3 ? CTI_BURST : CTI_EOB, 4'b1111);
382
                end
383
                else
384
                begin
385
                        /* Move to wait state */
386
                        kill_access;
387
                        state_nxt = REFRESH_1;
388
 
389
                        /* Update tag. Remove dirty bit. */
390
                        o_cache_tag_wr_en                      = 1'd1; // Implicitly sets valid (redundant).
391
                        o_cache_tag[`CACHE_TAG__TAG]           = i_cache_tag[`VA__CACHE_TAG]; // Preserve.
392
                        o_cache_tag_dirty                      = 1'd0;
393
                        o_cache_tag[`CACHE_TAG__PA]            = i_cache_tag[`CACHE_TAG__PA]; // Preserve.
394
                end
395
        end
396
 
397
        FETCH_SINGLE: /* Fetch a single cache line */
398
        begin
399
 
400
                o_ack = 1'd0;
401
 
402
                /* Generate address */
403
                adr_ctr_nxt = adr_ctr_ff + (o_wb_stb_ff && i_wb_ack);
404
 
405
                /* Write to buffer */
406
                buf_nxt[adr_ctr_ff] = i_wb_ack ? i_wb_dat : buf_ff[adr_ctr_ff];
407
 
408
                /* Manipulate buffer as needed */
409
                if ( i_wr )
410
                begin
411
                        buf_nxt[i_address[3:2]][7:0]   = i_ben[0] ? i_din[7:0]   : buf_nxt[i_address[3:2]][7:0];
412
                        buf_nxt[i_address[3:2]][15:8]  = i_ben[1] ? i_din[15:8]  : buf_nxt[i_address[3:2]][15:8];
413
                        buf_nxt[i_address[3:2]][23:16] = i_ben[2] ? i_din[23:16] : buf_nxt[i_address[3:2]][23:16];
414
                        buf_nxt[i_address[3:2]][31:24] = i_ben[3] ? i_din[31:24] : buf_nxt[i_address[3:2]][31:24];
415
                end
416
 
417
                if ( adr_ctr_nxt <= 3 )
418
                begin
419
 
420
                        /* Fetch line from memory */
421
                        wb_prpr_read({i_phy_addr[31:4], 4'd0} + (adr_ctr_nxt << 2),
422
                                     adr_ctr_nxt != 3 ? CTI_BURST : CTI_EOB);
423
                end
424
                else
425
                begin
426
 
427
                        /* Update cache */
428
                        o_cache_line = {buf_nxt[3], buf_ff[2], buf_ff[1], buf_ff[0]};
429
                        o_cache_line_ben  = 16'b1111111111111111;
430
 
431
                        /* Update tag. Remove dirty and set valid */
432
                        o_cache_tag_wr_en                       = 1'd1; // Implicitly sets valid.
433
                        o_cache_tag[`CACHE_TAG__TAG]            = i_address[`VA__CACHE_TAG];
434
                        o_cache_tag[`CACHE_TAG__PA]             = i_phy_addr >> 4;
435
                        o_cache_tag_dirty                       = !i_wr ? 1'd0 : 1'd1; // BUG FIX.
436
 
437
                        /* Move to wait state */
438
                        kill_access;
439
                        state_nxt = REFRESH_1;
440
                end
441
        end
442
 
443
        REFRESH: /* One extra cycle for cache and tag to update. */
444
        begin
445
                kill_access;
446
                o_ack     = i_wr && cache_cmp;
447
                state_nxt = IDLE;
448
        end
449
 
450
        INVALIDATE: /* Invalidate the cache - Almost Single Cycle */
451
        begin
452
                cache_inv_req_nxt = 1'd1;
453
                cache_clean_req_nxt = 1'd0;
454
 
455
                if ( i_cache_inv_done )
456
                begin
457
                        cache_inv_req_nxt    = 1'd0;
458
                        state_nxt            = IDLE;
459
                        o_cache_inv_done = 1'd1;
460
                end
461
        end
462
 
463
        CLEAN:  /* Force cache to clean itself */
464
        begin
465
                cache_clean_req_nxt = 1'd1;
466
                cache_inv_req_nxt   = 1'd0;
467
 
468
                if ( i_cache_clean_done )
469
                begin
470
                        cache_clean_req_nxt  = 1'd0;
471
                        state_nxt            = IDLE;
472
                        o_cache_clean_done   = 1'd1;
473
                end
474
        end
475
 
476
        endcase
477
end
478
 
479 51 Revanth
// ----------------------------------------------------------------------------
480 43 Revanth
// Tasks and functions.
481 51 Revanth
// ----------------------------------------------------------------------------
482 43 Revanth
 
483 26 Revanth
function [31:0] adapt_cache_data
484
(input [1:0] shift, input [127:0] cd);
485
begin: blk1
486
        reg [31:0] shamt;
487
        shamt = shift << 5;
488
        adapt_cache_data = cd >> shamt;
489
end
490
endfunction
491
 
492
function [15:0] ben_comp ( input [1:0] shift, input [3:0] bv );
493
begin:fblk2
494
        reg [31:0] shamt;
495
        shamt = shift << 2;
496
        ben_comp = bv << shamt;
497
end
498
endfunction
499
 
500
function [31:0] clean_single_d ( input [127:0] cl, input [31:0] sh );
501
reg [31:0] shamt;
502
begin
503
        shamt = sh << 5;
504
        clean_single_d = cl >> shamt; // Select specific 32-bit.
505
end
506
endfunction
507
 
508
/* Function to generate Wishbone read signals. */
509
task  wb_prpr_read;
510
input [31:0] i_address;
511
input [2:0]  i_cti;
512
begin
513
        o_wb_cyc_nxt = 1'd1;
514
        o_wb_stb_nxt = 1'd1;
515
        o_wb_wen_nxt = 1'd0;
516
        o_wb_sel_nxt = 4'b1111;
517
        o_wb_adr_nxt = i_address;
518
        o_wb_cti_nxt = i_cti;
519
        o_wb_dat_nxt = 0;
520
end
521
endtask
522
 
523
/* Function to generate Wishbone write signals */
524
task  wb_prpr_write;
525
input   [31:0]  i_data;
526
input   [31:0]  i_address;
527
input   [2:0]   i_cti;
528
input   [3:0]   i_ben;
529
begin
530
        o_wb_cyc_nxt = 1'd1;
531
        o_wb_stb_nxt = 1'd1;
532
        o_wb_wen_nxt = 1'd1;
533
        o_wb_sel_nxt = i_ben;
534
        o_wb_adr_nxt = i_address;
535
        o_wb_cti_nxt = i_cti;
536
        o_wb_dat_nxt = i_data;
537
end
538
endtask
539
 
540
/* Disables Wishbone */
541
task  kill_access;
542
begin
543
        o_wb_cyc_nxt = 0;
544
        o_wb_stb_nxt = 0;
545
        o_wb_wen_nxt = 0;
546
        o_wb_adr_nxt = 0;
547
        o_wb_dat_nxt = 0;
548
        o_wb_sel_nxt = 0;
549
        o_wb_cti_nxt = CTI_CLASSIC;
550
end
551
endtask
552
 
553
// ----------------------------------------------------------------------------
554
 
555
wire [31:0] buf0_ff, buf1_ff, buf2_ff;
556 43 Revanth
 
557 26 Revanth
assign buf0_ff = buf_ff[0];
558
assign buf1_ff = buf_ff[1];
559
assign buf2_ff = buf_ff[2];
560 43 Revanth
 
561 26 Revanth
wire [31:0] buf3_ff = buf_ff[3];
562
wire [31:0] buf0_nxt = buf_nxt[0];
563
wire [31:0] buf1_nxt = buf_nxt[1];
564
wire [31:0] buf2_nxt = buf_nxt[2];
565
wire [31:0] buf3_nxt = buf_nxt[3];
566
 
567
wire [31:0] dbg_addr_tag = i_address[`VA__CACHE_TAG];
568
wire [31:0] dbg_addr_pa  = i_phy_addr >> 4;
569
wire [31:0] dbg_ct_tag   = o_cache_tag[`CACHE_TAG__TAG];
570
wire [31:0] dbg_ct_pa    = o_cache_tag[`CACHE_TAG__PA];
571
 
572 43 Revanth
endmodule // zap_cache_fsm
573
 
574 26 Revanth
`default_nettype wire
575 51 Revanth
 
576
// ----------------------------------------------------------------------------
577
// END OF FILE
578
// ----------------------------------------------------------------------------

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