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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_core.v] - Blame information for rev 43

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1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                         --  
24
// -- This is the ZAP core which contains the bare processor core without any --
25
// -- cache or MMU. In other words, this is the bare pipeline.                --
26
// --                                                                         --
27
// -----------------------------------------------------------------------------
28
 
29
`default_nettype none
30
 
31
module zap_core #(
32
        // Number of branch predictor entries.
33
        parameter [31:0] BP_ENTRIES = 1024,
34
 
35
        // Depth of FIFO.
36
        parameter [31:0] FIFO_DEPTH = 4
37 43 Revanth
)
38 26 Revanth
(
39
 
40 43 Revanth
// ------------------------------------------------
41
// Clock and reset. Reset is synchronous.
42
// ------------------------------------------------
43 26 Revanth
 
44 43 Revanth
input wire                              i_clk,
45
input wire                              i_reset,
46
 
47
// -------------------------------------------------
48 26 Revanth
// Wishbone memory access for data.
49 43 Revanth
// -------------------------------------------------
50
 
51 26 Revanth
output wire                             o_data_wb_we,
52
output wire                             o_data_wb_cyc,
53
output wire                             o_data_wb_stb,
54
output wire[31:0]                       o_data_wb_adr,
55
input wire                              i_data_wb_ack,
56
input wire                              i_data_wb_err,
57
input wire  [31:0]                      i_data_wb_dat,
58
output wire [31:0]                      o_data_wb_dat,
59
output wire  [3:0]                      o_data_wb_sel,
60
 
61
// Next state stuff for Wishbone data.
62
output wire                             o_data_wb_we_nxt,
63
output wire                             o_data_wb_cyc_nxt,
64
output wire                             o_data_wb_stb_nxt,
65
output wire [31:0]                      o_data_wb_dat_nxt,
66
output wire  [3:0]                      o_data_wb_sel_nxt,
67
output wire [31:0]                      o_data_wb_adr_nxt,
68
 
69
// Force user view.
70
output wire                             o_mem_translate,
71
 
72 43 Revanth
// --------------------------------------------------
73 26 Revanth
// Interrupts. Active high.
74 43 Revanth
// --------------------------------------------------
75
 
76 26 Revanth
input wire                              i_fiq,                  // FIQ signal.
77
input wire                              i_irq,                  // IRQ signal.
78
 
79 43 Revanth
// ---------------------------------------------------
80 26 Revanth
// Wishbone instruction access ports.
81 43 Revanth
// ---------------------------------------------------
82
 
83 26 Revanth
output wire     [31:0]                  o_instr_wb_adr, // Code address.                  
84
output wire                             o_instr_wb_cyc, // Always 1.
85
output wire                             o_instr_wb_stb, // Always 1.
86
output wire                             o_instr_wb_we,  // Always 0.
87
input wire [31:0]                       i_instr_wb_dat, // A 32-bit ZAP instruction.
88
input wire                              i_instr_wb_ack, // Instruction available.
89
input wire                              i_instr_wb_err, // Instruction abort fault. Given with ack = 1.
90
output wire [3:0]                       o_instr_wb_sel, // wishbone byte select.
91
 
92
// Instruction wishbone nxt ports.
93
output wire     [31:0]                  o_instr_wb_adr_nxt,
94
output wire                             o_instr_wb_stb_nxt,
95
 
96
// Determines user or supervisory mode. Cache must use this for VM.
97
output wire      [31:0]                 o_cpsr,
98
 
99 43 Revanth
// -----------------------------------------------------
100 26 Revanth
// For MMU/cache connectivity.
101 43 Revanth
// -----------------------------------------------------
102
 
103 26 Revanth
input wire      [31:0]                  i_fsr,
104
input wire      [31:0]                  i_far,
105
output wire      [31:0]                 o_dac,
106
output wire      [31:0]                 o_baddr,
107
output wire                             o_mmu_en,
108
output wire      [1:0]                  o_sr,
109 43 Revanth
output wire                             o_pid,
110 26 Revanth
output wire                             o_dcache_inv,
111
output wire                             o_icache_inv,
112
output wire                             o_dcache_clean,
113
output wire                             o_icache_clean,
114
output wire                             o_dtlb_inv,
115
output wire                             o_itlb_inv,
116
output wire                             o_dcache_en,
117
output wire                             o_icache_en,
118
input   wire                            i_dcache_inv_done,
119
input   wire                            i_icache_inv_done,
120
input   wire                            i_dcache_clean_done,
121 43 Revanth
input   wire                            i_icache_clean_done
122 26 Revanth
);
123
 
124
// ----------------------------------------------------------------------------
125
 
126
`include "zap_localparams.vh"
127
`include "zap_defines.vh"
128
`include "zap_functions.vh"
129
 
130
localparam ARCH_REGS = 32;
131
localparam ALU_OPS   = 32;
132
localparam SHIFT_OPS = 7;
133
localparam PHY_REGS  = TOTAL_PHY_REGS;
134
localparam FLAG_WDT  = 32;
135
 
136
// ----------------------------------------------------------------------------
137
 
138
// Low Bandwidth Coprocessor (COP) I/F to CP15 control block.
139
wire                             copro_done;        // COP done.
140 43 Revanth
wire                             copro_dav;         // COP command valid.
141 26 Revanth
wire  [31:0]                     copro_word;        // COP command.
142
wire                             copro_reg_en;      // COP controls registers.
143
wire      [$clog2(PHY_REGS)-1:0] copro_reg_wr_index;// Reg. file write index.
144
wire      [$clog2(PHY_REGS)-1:0] copro_reg_rd_index;// Reg. file read index.
145
wire      [31:0]                 copro_reg_wr_data; // Reg. file write data.
146
wire     [31:0]                  copro_reg_rd_data; // Reg. file read data.
147
 
148 43 Revanth
wire                            reset;               // Tied to i_reset.
149
wire                            shelve;              // From writeback.
150
wire                            fiq;                 // Tied to FIQ.
151
wire                            irq;                 // Tied to IRQ.
152 26 Revanth
 
153
// Clear and stall signals.
154 43 Revanth
wire                            stall_from_decode;
155
wire                            clear_from_alu;
156
wire                            stall_from_issue;
157
wire                            clear_from_writeback;
158
wire                            data_stall;
159
wire                            code_stall;
160
wire                            instr_valid;
161
wire                            pipeline_is_not_empty;
162 26 Revanth
 
163
// Fetch
164 43 Revanth
wire [31:0]                     fetch_instruction;  // Instruction from the fetch unit.
165
wire                            fetch_valid;        // Instruction valid from the fetch unit.
166
wire                            fetch_instr_abort;  // abort indicator.
167
wire [31:0]                     fetch_pc_plus_8_ff; // PC + 8 generated from the fetch unit.
168
wire [31:0]                     fetch_pc_ff;        // PC generated from fetch unit.
169
wire [1:0]                      fetch_bp_state;
170 26 Revanth
 
171
// FIFO.
172 43 Revanth
wire [31:0]                     fifo_pc_plus_8;
173
wire                            fifo_valid;
174
wire                            fifo_instr_abort;
175
wire [31:0]                     fifo_instruction;
176
wire [1:0]                      fifo_bp_state;
177 26 Revanth
 
178
// Predecode
179 43 Revanth
wire [31:0]                     predecode_pc_plus_8;
180
wire [31:0]                     predecode_pc;
181
wire                            predecode_irq;
182
wire                            predecode_fiq;
183
wire                            predecode_abt;
184
wire [35:0]                     predecode_inst;
185
wire                            predecode_val;
186
wire                            predecode_force32;
187
wire                            predecode_und;
188
wire [1:0]                      predecode_taken;
189 26 Revanth
 
190 43 Revanth
// Compressed decoder.
191
wire                            thumb_irq;
192
wire                            thumb_fiq;
193
wire                            thumb_iabort;
194
wire [34:0]                     thumb_instruction;
195
wire                            thumb_valid;
196
wire                            thumb_und;
197
wire                            thumb_force32;
198
wire [1:0]                      thumb_bp_state;
199
wire [31:0]                     thumb_pc_ff;
200
wire [31:0]                     thumb_pc_plus_8_ff;
201
 
202 26 Revanth
// Decode
203
wire [3:0]                      decode_condition_code;
204
wire [$clog2(PHY_REGS)-1:0]     decode_destination_index;
205
wire [32:0]                     decode_alu_source_ff;
206
wire [$clog2(ALU_OPS)-1:0]      decode_alu_operation_ff;
207
wire [32:0]                     decode_shift_source_ff;
208
wire [$clog2(SHIFT_OPS)-1:0]    decode_shift_operation_ff;
209
wire [32:0]                     decode_shift_length_ff;
210
wire                            decode_flag_update_ff;
211
wire [$clog2(PHY_REGS)-1:0]     decode_mem_srcdest_index_ff;
212
wire                            decode_mem_load_ff;
213
wire                            decode_mem_store_ff;
214
wire                            decode_mem_pre_index_ff;
215
wire                            decode_mem_unsigned_byte_enable_ff;
216
wire                            decode_mem_signed_byte_enable_ff;
217
wire                            decode_mem_signed_halfword_enable_ff;
218
wire                            decode_mem_unsigned_halfword_enable_ff;
219
wire                            decode_mem_translate_ff;
220
wire                            decode_irq_ff;
221
wire                            decode_fiq_ff;
222
wire                            decode_abt_ff;
223
wire                            decode_swi_ff;
224
wire [31:0]                     decode_pc_plus_8_ff;
225
wire [31:0]                     decode_pc_ff;
226
wire                            decode_switch_ff;
227
wire                            decode_force32_ff;
228
wire                            decode_und_ff;
229
wire                            clear_from_decode;
230
wire [31:0]                     pc_from_decode;
231
wire [1:0]                      decode_taken_ff;
232
 
233
// Issue
234
wire [$clog2(PHY_REGS)-1:0]     issue_rd_index_0,
235
                                issue_rd_index_1,
236
                                issue_rd_index_2,
237
                                issue_rd_index_3;
238
 
239
wire [3:0]                      issue_condition_code_ff;
240
wire [$clog2(PHY_REGS)-1:0]     issue_destination_index_ff;
241
wire [$clog2(ALU_OPS)-1:0]      issue_alu_operation_ff;
242
wire [$clog2(SHIFT_OPS)-1:0]    issue_shift_operation_ff;
243
wire                            issue_flag_update_ff;
244
wire [$clog2(PHY_REGS)-1:0]     issue_mem_srcdest_index_ff;
245
wire                            issue_mem_load_ff;
246
wire                            issue_mem_store_ff;
247
wire                            issue_mem_pre_index_ff;
248
wire                            issue_mem_unsigned_byte_enable_ff;
249
wire                            issue_mem_signed_byte_enable_ff;
250
wire                            issue_mem_signed_halfword_enable_ff;
251
wire                            issue_mem_unsigned_halfword_enable_ff;
252
wire                            issue_mem_translate_ff;
253
wire                            issue_irq_ff;
254
wire                            issue_fiq_ff;
255
wire                            issue_abt_ff;
256
wire                            issue_swi_ff;
257
wire [31:0]                     issue_alu_source_value_ff;
258
wire [31:0]                     issue_shift_source_value_ff;
259
wire [31:0]                     issue_shift_length_value_ff;
260
wire [31:0]                     issue_mem_srcdest_value_ff;
261
wire [32:0]                     issue_alu_source_ff;
262
wire [32:0]                     issue_shift_source_ff;
263
wire [31:0]                     issue_pc_plus_8_ff;
264
wire [31:0]                     issue_pc_ff;
265
wire                            issue_shifter_disable_ff;
266
wire                            issue_switch_ff;
267
wire                            issue_force32_ff;
268
wire                            issue_und_ff;
269
wire  [1:0]                     issue_taken_ff;
270
 
271
wire [$clog2(PHY_REGS)-1:0]     rd_index_0;
272
wire [$clog2(PHY_REGS)-1:0]     rd_index_1;
273
wire [$clog2(PHY_REGS)-1:0]     rd_index_2;
274
wire [$clog2(PHY_REGS)-1:0]     rd_index_3;
275
 
276
// Shift
277
wire [$clog2(PHY_REGS)-1:0]     shifter_mem_srcdest_index_ff;
278
wire                            shifter_mem_load_ff;
279
wire                            shifter_mem_store_ff;
280
wire                            shifter_mem_pre_index_ff;
281
wire                            shifter_mem_unsigned_byte_enable_ff;
282
wire                            shifter_mem_signed_byte_enable_ff;
283
wire                            shifter_mem_signed_halfword_enable_ff;
284
wire                            shifter_mem_unsigned_halfword_enable_ff;
285
wire                            shifter_mem_translate_ff;
286
wire [3:0]                      shifter_condition_code_ff;
287
wire [$clog2(PHY_REGS)-1:0]     shifter_destination_index_ff;
288
wire [$clog2(ALU_OPS)-1:0]      shifter_alu_operation_ff;
289
wire                            shifter_nozero_ff;
290
wire                            shifter_flag_update_ff;
291
wire [31:0]                     shifter_mem_srcdest_value_ff;
292
wire [31:0]                     shifter_alu_source_value_ff;
293
wire [31:0]                     shifter_shifted_source_value_ff;
294
wire                            shifter_shift_carry_ff;
295
wire [31:0]                     shifter_pc_plus_8_ff;
296
wire [31:0]                     shifter_pc_ff;
297
wire                            shifter_irq_ff;
298
wire                            shifter_fiq_ff;
299
wire                            shifter_abt_ff;
300
wire                            shifter_swi_ff;
301
wire                            shifter_switch_ff;
302
wire                            shifter_force32_ff;
303
wire                            shifter_und_ff;
304
wire                            stall_from_shifter;
305
wire [1:0]                      shifter_taken_ff;
306
 
307
// ALU
308
wire [$clog2(SHIFT_OPS)-1:0]    alu_shift_operation_ff;
309
wire [31:0]                     alu_alu_result_nxt;
310
wire [31:0]                     alu_alu_result_ff;
311
wire                            alu_abt_ff;
312
wire                            alu_irq_ff;
313
wire                            alu_fiq_ff;
314
wire                            alu_swi_ff;
315
wire                            alu_dav_ff;
316
wire                            alu_dav_nxt;
317
wire [31:0]                     alu_pc_plus_8_ff;
318
wire [31:0]                     pc_from_alu;
319
wire [$clog2(PHY_REGS)-1:0]     alu_destination_index_ff;
320
wire [FLAG_WDT-1:0]             alu_flags_ff;
321
wire [$clog2(PHY_REGS)-1:0]     alu_mem_srcdest_index_ff;
322
wire                            alu_mem_load_ff;
323
wire                            alu_und_ff;
324
wire [31:0]                     alu_cpsr_nxt;
325
wire                            confirm_from_alu;
326
wire                            alu_sbyte_ff;
327
wire                            alu_ubyte_ff;
328
wire                            alu_shalf_ff;
329
wire                            alu_uhalf_ff;
330
wire [31:0]                     alu_address_ff;
331
wire [31:0]                     alu_address_nxt;
332
 
333
// Memory
334
wire [31:0]                     memory_alu_result_ff;
335
wire [$clog2(PHY_REGS)-1:0]     memory_destination_index_ff;
336
wire [$clog2(PHY_REGS)-1:0]     memory_mem_srcdest_index_ff;
337
wire                            memory_dav_ff;
338
wire [31:0]                     memory_pc_plus_8_ff;
339
wire                            memory_irq_ff;
340
wire                            memory_fiq_ff;
341
wire                            memory_swi_ff;
342
wire                            memory_instr_abort_ff;
343
wire                            memory_mem_load_ff;
344
wire  [FLAG_WDT-1:0]            memory_flags_ff;
345
wire  [31:0]                    memory_mem_rd_data;
346
wire                            memory_und_ff;
347
wire                            memory_data_abt_ff;
348
 
349
// Writeback
350 43 Revanth
wire [31:0]                     rd_data_0;
351
wire [31:0]                     rd_data_1;
352
wire [31:0]                     rd_data_2;
353
wire [31:0]                     rd_data_3;
354
wire [31:0]                     cpsr_nxt, cpsr;
355 26 Revanth
 
356 43 Revanth
// Hijack interface - related to Writeback - ALU interaction.
357
wire                            wb_hijack;
358
wire [31:0]                     wb_hijack_op1;
359
wire [31:0]                     wb_hijack_op2;
360
wire                            wb_hijack_cin;
361
wire [31:0]                     alu_hijack_sum;
362 26 Revanth
 
363 43 Revanth
// Decompile chain for debugging.
364
wire [64*8-1:0]                 decode_decompile;
365
wire [64*8-1:0]                 issue_decompile;
366
wire [64*8-1:0]                 shifter_decompile;
367
wire [64*8-1:0]                 alu_decompile;
368
wire [64*8-1:0]                 memory_decompile;
369
wire [64*8-1:0]                 rb_decompile;
370 26 Revanth
 
371
// ----------------------------------------------------------------------------
372
 
373 43 Revanth
assign o_cpsr                   = alu_flags_ff;
374
assign o_data_wb_adr            = {alu_address_ff[31:2], 2'd0};
375
assign o_data_wb_adr_nxt        = {alu_address_nxt[31:2], 2'd0};
376
assign o_instr_wb_we            = 1'd0;
377
assign o_instr_wb_sel           = 4'b1111;
378
assign reset                    = i_reset;
379
assign irq                      = i_irq;
380
assign fiq                      = i_fiq;
381
assign data_stall               = o_data_wb_stb && o_data_wb_cyc && !i_data_wb_ack;
382
assign code_stall               = (!o_instr_wb_stb && !o_instr_wb_cyc) || !i_instr_wb_ack;
383
assign instr_valid              = o_instr_wb_stb && o_instr_wb_cyc && i_instr_wb_ack & !shelve;
384
assign pipeline_is_not_empty    =         predecode_val                      ||
385
                                          (decode_condition_code    != NV)   ||
386
                                          (issue_condition_code_ff  != NV)   ||
387
                                          (shifter_condition_code_ff!= NV)   ||
388
                                          alu_dav_ff                         ||
389
                                          memory_dav_ff;
390 26 Revanth
 
391
// ----------------------------------------------------------------------------
392
 
393
// =========================
394
// FETCH STAGE 
395
// =========================
396
zap_fetch_main
397
#(
398
        .BP_ENTRIES(BP_ENTRIES)
399
)
400
u_zap_fetch_main (
401
        // Input.
402
        .i_clk                          (i_clk),
403
        .i_reset                        (reset),
404
 
405 43 Revanth
        .i_code_stall                   (code_stall),
406 26 Revanth
 
407
        .i_clear_from_writeback         (clear_from_writeback),
408
        .i_clear_from_decode            (clear_from_decode),
409
 
410
        .i_data_stall                   (1'd0),
411
 
412
        .i_clear_from_alu               (clear_from_alu),
413
 
414
        .i_stall_from_shifter           (1'd0),
415
        .i_stall_from_issue             (1'd0),
416
        .i_stall_from_decode            (1'd0),
417
 
418
        .i_pc_ff                        (o_instr_wb_adr),
419
        .i_instruction                  (i_instr_wb_dat),
420 43 Revanth
        .i_valid                        (instr_valid),
421 26 Revanth
        .i_instr_abort                  (i_instr_wb_err),
422
 
423
        .i_cpsr_ff_t                    (alu_flags_ff[T]),
424
 
425
        // Output.
426
        .o_instruction                  (fetch_instruction),
427
        .o_valid                        (fetch_valid),
428
        .o_instr_abort                  (fetch_instr_abort),
429
        .o_pc_plus_8_ff                 (fetch_pc_plus_8_ff),
430
        .o_pc_ff                        (fetch_pc_ff),
431
 
432
 
433
        .i_confirm_from_alu             (confirm_from_alu),
434
        .i_pc_from_alu                  (shifter_pc_ff),
435
        .i_taken                        (shifter_taken_ff),
436 43 Revanth
        .o_taken                        (fetch_bp_state)
437 26 Revanth
);
438
 
439
// =========================
440
// FIFO.
441
// =========================
442
zap_fifo
443
#( .WDT(67), .DEPTH(FIFO_DEPTH) ) U_ZAP_FIFO (
444 43 Revanth
        .i_clk                          (i_clk),
445
        .i_reset                        (i_reset),
446
        .i_clear_from_writeback         (clear_from_writeback),
447 26 Revanth
 
448 43 Revanth
        .i_write_inhibit                ( code_stall ),
449
        .i_data_stall                   ( data_stall ),
450 26 Revanth
 
451 43 Revanth
        .i_clear_from_alu               (clear_from_alu),
452
        .i_stall_from_shifter           (stall_from_shifter),
453
        .i_stall_from_issue             (stall_from_issue),
454
        .i_stall_from_decode            (stall_from_decode),
455
        .i_clear_from_decode            (clear_from_decode),
456 26 Revanth
 
457 43 Revanth
        .i_instr                        ({fetch_pc_plus_8_ff, fetch_instr_abort, fetch_instruction, fetch_bp_state}),
458
        .i_valid                        (fetch_valid),
459
        .o_instr                        ({fifo_pc_plus_8, fifo_instr_abort, fifo_instruction, fifo_bp_state}),
460
        .o_valid                        (fifo_valid),
461 26 Revanth
 
462 43 Revanth
        .o_wb_stb                       (o_instr_wb_stb),
463
        .o_wb_stb_nxt                   (o_instr_wb_stb_nxt),
464
        .o_wb_cyc                       (o_instr_wb_cyc)
465 26 Revanth
);
466
 
467
// =========================
468
// COMPRESSED DECODER STAGE
469
// =========================
470
zap_thumb_decoder u_zap_thumb_decoder (
471 43 Revanth
.i_clk                                  (i_clk),
472
.i_reset                                (i_reset),
473
.i_clear_from_writeback                 (clear_from_writeback),
474
.i_data_stall                           (data_stall),
475
.i_clear_from_alu                       (clear_from_alu),
476
.i_stall_from_shifter                   (stall_from_shifter),
477
.i_stall_from_issue                     (stall_from_issue),
478
.i_stall_from_decode                    (stall_from_decode),
479
.i_clear_from_decode                    (clear_from_decode),
480 26 Revanth
 
481 43 Revanth
.i_taken                                (fifo_bp_state),
482
.i_instruction                          (fifo_instruction),
483
.i_instruction_valid                    (fifo_valid),
484
.i_irq                                  (fifo_valid ? irq && !alu_flags_ff[I] : 1'd0), // Pass interrupt only if mask = 0 and instruction exists.
485
.i_fiq                                  (fifo_valid ? fiq && !alu_flags_ff[F] : 1'd0), // Pass interrupt only if mask = 0 and instruction exists.
486
.i_iabort                               (fifo_instr_abort),
487
.o_iabort                               (thumb_iabort),
488
.i_cpsr_ff_t                            (alu_flags_ff[T]),
489
.i_pc_ff                                (alu_flags_ff[T] ? fifo_pc_plus_8 - 32'd4 : fifo_pc_plus_8 - 32'd8),
490
.i_pc_plus_8_ff                         (fifo_pc_plus_8),
491 26 Revanth
 
492 43 Revanth
.o_instruction                          (thumb_instruction),
493
.o_instruction_valid                    (thumb_valid),
494
.o_und                                  (thumb_und),
495
.o_force32_align                        (thumb_force32),
496
.o_pc_ff                                (thumb_pc_ff),
497
.o_pc_plus_8_ff                         (thumb_pc_plus_8_ff),
498
.o_irq                                  (thumb_irq),
499
.o_fiq                                  (thumb_fiq),
500
.o_taken_ff                             (thumb_bp_state)
501 26 Revanth
);
502
 
503
// =========================
504
// PREDECODE STAGE 
505
// =========================
506
zap_predecode_main #(
507
        .ARCH_REGS(ARCH_REGS),
508
        .PHY_REGS(PHY_REGS),
509
        .SHIFT_OPS(SHIFT_OPS),
510
        .ALU_OPS(ALU_OPS),
511
        .COPROCESSOR_INTERFACE_ENABLE(1'd1),
512
        .COMPRESSED_EN(1'd1)
513
)
514
u_zap_predecode (
515
        // Input.
516
        .i_clk                          (i_clk),
517
        .i_reset                        (reset),
518
 
519
        .i_clear_from_writeback         (clear_from_writeback),
520 43 Revanth
        .i_data_stall                   (data_stall),
521 26 Revanth
        .i_clear_from_alu               (clear_from_alu),
522
        .i_stall_from_shifter           (stall_from_shifter),
523
        .i_stall_from_issue             (stall_from_issue),
524
 
525
        .i_irq                          (thumb_irq),
526
        .i_fiq                          (thumb_fiq),
527
 
528
        .i_abt                          (thumb_iabort),
529
        .i_pc_plus_8_ff                 (thumb_pc_plus_8_ff),
530
        .i_pc_ff                        (thumb_pc_plus_8_ff - 32'd8),
531
 
532
        .i_cpu_mode_t                   (alu_flags_ff[T]),
533
        .i_cpu_mode_mode                (alu_flags_ff[`CPSR_MODE]),
534
 
535
        .i_instruction                  (thumb_instruction),
536
        .i_instruction_valid            (thumb_valid),
537
        .i_taken                        (thumb_bp_state),
538
 
539
        .i_force32                      (thumb_force32),
540
        .i_und                          (thumb_und),
541
 
542
        .i_copro_done                   (copro_done),
543 43 Revanth
        .i_pipeline_dav                 (pipeline_is_not_empty),
544 26 Revanth
 
545
        // Output.
546
        .o_stall_from_decode            (stall_from_decode),
547
        .o_pc_plus_8_ff                 (predecode_pc_plus_8),
548
 
549
        .o_pc_ff                        (predecode_pc),
550
        .o_irq_ff                       (predecode_irq),
551
        .o_fiq_ff                       (predecode_fiq),
552
        .o_abt_ff                       (predecode_abt),
553
        .o_und_ff                       (predecode_und),
554
 
555
        .o_force32align_ff              (predecode_force32),
556
 
557
        .o_copro_dav_ff                 (copro_dav),
558
        .o_copro_word_ff                (copro_word),
559
 
560
        .o_clear_from_decode            (clear_from_decode),
561
        .o_pc_from_decode               (pc_from_decode),
562
 
563
        .o_instruction_ff               (predecode_inst),
564
        .o_instruction_valid_ff         (predecode_val),
565
 
566
        .o_taken_ff                     (predecode_taken)
567
);
568
 
569
// =====================
570
// DECODE STAGE 
571
// =====================
572
 
573
zap_decode_main #(
574
        .ARCH_REGS(ARCH_REGS),
575
        .PHY_REGS(PHY_REGS),
576
        .SHIFT_OPS(SHIFT_OPS),
577
        .ALU_OPS(ALU_OPS)
578
)
579
u_zap_decode_main (
580
        .o_decompile                    (decode_decompile),
581
 
582
        // Input.
583
        .i_clk                          (i_clk),
584
        .i_reset                        (reset),
585
 
586
        .i_clear_from_writeback         (clear_from_writeback),
587 43 Revanth
        .i_data_stall                   (data_stall),
588 26 Revanth
        .i_clear_from_alu               (clear_from_alu),
589
        .i_stall_from_shifter           (stall_from_shifter),
590
        .i_stall_from_issue             (stall_from_issue),
591
        .i_thumb_und                    (predecode_und),
592
        .i_irq                          (predecode_irq),
593
        .i_fiq                          (predecode_fiq),
594
        .i_abt                          (predecode_abt),
595
        .i_pc_plus_8_ff                 (predecode_pc_plus_8),
596
        .i_pc_ff                        (predecode_pc),
597
 
598
        .i_cpsr_ff_mode                 (alu_flags_ff[`CPSR_MODE]),
599
        .i_cpsr_ff_i                    (alu_flags_ff[I]),
600
        .i_cpsr_ff_f                    (alu_flags_ff[F]),
601
 
602
        .i_instruction                  (predecode_inst),
603
        .i_instruction_valid            (predecode_val),
604
        .i_taken                        (predecode_taken),
605
        .i_force32align                 (predecode_force32),
606
 
607
        // Output.
608
        .o_condition_code_ff            (decode_condition_code),
609
        .o_destination_index_ff         (decode_destination_index),
610
        .o_alu_source_ff                (decode_alu_source_ff),
611
        .o_alu_operation_ff             (decode_alu_operation_ff),
612
        .o_shift_source_ff              (decode_shift_source_ff),
613
        .o_shift_operation_ff           (decode_shift_operation_ff),
614
        .o_shift_length_ff              (decode_shift_length_ff),
615
        .o_flag_update_ff               (decode_flag_update_ff),
616
        .o_mem_srcdest_index_ff         (decode_mem_srcdest_index_ff),
617
        .o_mem_load_ff                  (decode_mem_load_ff),
618
        .o_mem_store_ff                 (decode_mem_store_ff),
619
        .o_mem_pre_index_ff             (decode_mem_pre_index_ff),
620
        .o_mem_unsigned_byte_enable_ff  (decode_mem_unsigned_byte_enable_ff),
621
        .o_mem_signed_byte_enable_ff    (decode_mem_signed_byte_enable_ff),
622
        .o_mem_signed_halfword_enable_ff(decode_mem_signed_halfword_enable_ff),
623
        .o_mem_unsigned_halfword_enable_ff (decode_mem_unsigned_halfword_enable_ff),
624
        .o_mem_translate_ff             (decode_mem_translate_ff),
625
        .o_pc_plus_8_ff                 (decode_pc_plus_8_ff),
626
        .o_pc_ff                        (decode_pc_ff),
627
        .o_switch_ff                    (decode_switch_ff),
628
        .o_irq_ff                       (decode_irq_ff),
629
        .o_fiq_ff                       (decode_fiq_ff),
630
        .o_abt_ff                       (decode_abt_ff),
631
        .o_swi_ff                       (decode_swi_ff),
632
        .o_und_ff                       (decode_und_ff),
633
        .o_force32align_ff              (decode_force32_ff),
634
        .o_taken_ff                     (decode_taken_ff)
635
);
636
 
637
// ==================
638
// ISSUE 
639
// ==================
640
 
641
zap_issue_main #(
642
        .PHY_REGS(PHY_REGS),
643
        .SHIFT_OPS(SHIFT_OPS),
644
        .ALU_OPS(ALU_OPS)
645
 
646
)
647
u_zap_issue_main
648
(
649
        .i_decompile(decode_decompile),
650
        .o_decompile(issue_decompile),
651
 
652
        .i_und_ff(decode_und_ff),
653
        .o_und_ff(issue_und_ff),
654
 
655
        .i_taken_ff(decode_taken_ff),
656
        .o_taken_ff(issue_taken_ff),
657
 
658
        .i_pc_ff(decode_pc_ff),
659
        .o_pc_ff(issue_pc_ff),
660
 
661
        // Inputs
662
        .i_clk                          (i_clk),
663
        .i_reset                        (reset),
664
        .i_clear_from_writeback         (clear_from_writeback),
665
        .i_stall_from_shifter           (stall_from_shifter),
666 43 Revanth
        .i_data_stall                   (data_stall),
667 26 Revanth
        .i_clear_from_alu               (clear_from_alu),
668
        .i_pc_plus_8_ff                 (decode_pc_plus_8_ff),
669
        .i_condition_code_ff            (decode_condition_code),
670
        .i_destination_index_ff         (decode_destination_index),
671
        .i_alu_source_ff                (decode_alu_source_ff),
672
        .i_alu_operation_ff             (decode_alu_operation_ff),
673
        .i_shift_source_ff              (decode_shift_source_ff),
674
        .i_shift_operation_ff           (decode_shift_operation_ff),
675
        .i_shift_length_ff              (decode_shift_length_ff),
676
        .i_flag_update_ff               (decode_flag_update_ff),
677
        .i_mem_srcdest_index_ff         (decode_mem_srcdest_index_ff),
678
        .i_mem_load_ff                  (decode_mem_load_ff),
679
        .i_mem_store_ff                 (decode_mem_store_ff),
680
        .i_mem_pre_index_ff             (decode_mem_pre_index_ff),
681
        .i_mem_unsigned_byte_enable_ff  (decode_mem_unsigned_byte_enable_ff),
682
        .i_mem_signed_byte_enable_ff    (decode_mem_signed_byte_enable_ff),
683
        .i_mem_signed_halfword_enable_ff(decode_mem_signed_halfword_enable_ff),
684
        .i_mem_unsigned_halfword_enable_ff(decode_mem_unsigned_halfword_enable_ff),
685
        .i_mem_translate_ff             (decode_mem_translate_ff),
686
        .i_irq_ff                       (decode_irq_ff),
687
        .i_fiq_ff                       (decode_fiq_ff),
688
        .i_abt_ff                       (decode_abt_ff),
689
        .i_swi_ff                       (decode_swi_ff),
690
        .i_cpu_mode                     (alu_flags_ff),
691
        // Needed to resolve CPSR refs.
692
 
693
        .i_force32align_ff              (decode_force32_ff),
694
        .o_force32align_ff              (issue_force32_ff),
695
 
696
        // Register file.
697
        .i_rd_data_0                    (rd_data_0),
698
        .i_rd_data_1                    (rd_data_1),
699
        .i_rd_data_2                    (rd_data_2),
700
        .i_rd_data_3                    (rd_data_3),
701
 
702
        // Feedback.
703
        .i_shifter_destination_index_ff (shifter_destination_index_ff),
704
        .i_alu_destination_index_ff     (alu_destination_index_ff),
705
        .i_memory_destination_index_ff  (memory_destination_index_ff),
706
        .i_alu_dav_nxt                  (alu_dav_nxt),
707
        .i_alu_dav_ff                   (alu_dav_ff),
708
        .i_memory_dav_ff                (memory_dav_ff),
709
        .i_alu_destination_value_nxt    (alu_alu_result_nxt),
710
        .i_alu_destination_value_ff     (alu_alu_result_ff),
711
        .i_memory_destination_value_ff  (memory_alu_result_ff),
712
        .i_shifter_mem_srcdest_index_ff (shifter_mem_srcdest_index_ff),
713
        .i_alu_mem_srcdest_index_ff     (alu_mem_srcdest_index_ff),
714
        .i_memory_mem_srcdest_index_ff  (memory_mem_srcdest_index_ff),
715
        .i_shifter_mem_load_ff          (shifter_mem_load_ff),
716
        .i_alu_mem_load_ff              (alu_mem_load_ff),
717
        .i_memory_mem_load_ff           (memory_mem_load_ff),
718
        .i_memory_mem_srcdest_value_ff  (memory_mem_rd_data),
719
 
720
        // Switch indicator.
721
        .i_switch_ff                    (decode_switch_ff),
722
        .o_switch_ff                    (issue_switch_ff),
723
 
724
        // Outputs.
725
        .o_rd_index_0                   (rd_index_0),
726
        .o_rd_index_1                   (rd_index_1),
727
        .o_rd_index_2                   (rd_index_2),
728
        .o_rd_index_3                   (rd_index_3),
729
        .o_condition_code_ff            (issue_condition_code_ff),
730
        .o_destination_index_ff         (issue_destination_index_ff),
731
        .o_alu_operation_ff             (issue_alu_operation_ff),
732
        .o_shift_operation_ff           (issue_shift_operation_ff),
733
        .o_flag_update_ff               (issue_flag_update_ff),
734
        .o_mem_srcdest_index_ff         (issue_mem_srcdest_index_ff),
735
        .o_mem_load_ff                  (issue_mem_load_ff),
736
        .o_mem_store_ff                 (issue_mem_store_ff),
737
        .o_mem_pre_index_ff             (issue_mem_pre_index_ff),
738
        .o_mem_unsigned_byte_enable_ff  (issue_mem_unsigned_byte_enable_ff),
739
        .o_mem_signed_byte_enable_ff    (issue_mem_signed_byte_enable_ff),
740
        .o_mem_signed_halfword_enable_ff(issue_mem_signed_halfword_enable_ff),
741
        .o_mem_unsigned_halfword_enable_ff(issue_mem_unsigned_halfword_enable_ff),
742
        .o_mem_translate_ff             (issue_mem_translate_ff),
743
        .o_irq_ff                       (issue_irq_ff),
744
        .o_fiq_ff                       (issue_fiq_ff),
745
        .o_abt_ff                       (issue_abt_ff),
746
        .o_swi_ff                       (issue_swi_ff),
747
 
748
        .o_alu_source_value_ff          (issue_alu_source_value_ff),
749
        .o_shift_source_value_ff        (issue_shift_source_value_ff),
750
        .o_shift_length_value_ff        (issue_shift_length_value_ff),
751
        .o_mem_srcdest_value_ff         (issue_mem_srcdest_value_ff),
752
 
753
        .o_alu_source_ff                (issue_alu_source_ff),
754
        .o_shift_source_ff              (issue_shift_source_ff),
755
        .o_stall_from_issue             (stall_from_issue),
756
        .o_pc_plus_8_ff                 (issue_pc_plus_8_ff),
757
        .o_shifter_disable_ff           (issue_shifter_disable_ff)
758
);
759
 
760
// =======================
761
// SHIFTER STAGE 
762
// =======================
763
 
764
zap_shifter_main #(
765
        .PHY_REGS(PHY_REGS),
766
        .ALU_OPS(ALU_OPS),
767
        .SHIFT_OPS(SHIFT_OPS)
768
)
769
u_zap_shifter_main
770
(
771 43 Revanth
        .i_decompile                    (issue_decompile),
772
        .o_decompile                    (shifter_decompile),
773 26 Revanth
 
774 43 Revanth
        .i_pc_ff                        (issue_pc_ff),
775
        .o_pc_ff                        (shifter_pc_ff),
776 26 Revanth
 
777 43 Revanth
        .i_taken_ff                     (issue_taken_ff),
778
        .o_taken_ff                     (shifter_taken_ff),
779 26 Revanth
 
780 43 Revanth
        .i_und_ff                       (issue_und_ff),
781
        .o_und_ff                       (shifter_und_ff),
782 26 Revanth
 
783 43 Revanth
        .o_nozero_ff                    (shifter_nozero_ff),
784 26 Revanth
 
785
        .i_clk                          (i_clk),
786
        .i_reset                        (reset),
787 43 Revanth
 
788 26 Revanth
        .i_clear_from_writeback         (clear_from_writeback),
789 43 Revanth
        .i_data_stall                   (data_stall),
790 26 Revanth
        .i_clear_from_alu               (clear_from_alu),
791
        .i_condition_code_ff            (issue_condition_code_ff),
792
        .i_destination_index_ff         (issue_destination_index_ff),
793
        .i_alu_operation_ff             (issue_alu_operation_ff),
794
        .i_shift_operation_ff           (issue_shift_operation_ff),
795
        .i_flag_update_ff               (issue_flag_update_ff),
796
        .i_mem_srcdest_index_ff         (issue_mem_srcdest_index_ff),
797
        .i_mem_load_ff                  (issue_mem_load_ff),
798
        .i_mem_store_ff                 (issue_mem_store_ff),
799
        .i_mem_pre_index_ff             (issue_mem_pre_index_ff),
800
        .i_mem_unsigned_byte_enable_ff  (issue_mem_unsigned_byte_enable_ff),
801
        .i_mem_signed_byte_enable_ff    (issue_mem_signed_byte_enable_ff),
802
        .i_mem_signed_halfword_enable_ff(issue_mem_signed_halfword_enable_ff),
803
        .i_mem_unsigned_halfword_enable_ff(issue_mem_unsigned_halfword_enable_ff),
804
        .i_mem_translate_ff             (issue_mem_translate_ff),
805
        .i_irq_ff                       (issue_irq_ff),
806
        .i_fiq_ff                       (issue_fiq_ff),
807
        .i_abt_ff                       (issue_abt_ff),
808
        .i_swi_ff                       (issue_swi_ff),
809
        .i_alu_source_ff                (issue_alu_source_ff),
810
        .i_shift_source_ff              (issue_shift_source_ff),
811
        .i_alu_source_value_ff          (issue_alu_source_value_ff),
812
        .i_shift_source_value_ff        (issue_shift_source_value_ff),
813
        .i_shift_length_value_ff        (issue_shift_length_value_ff),
814
        .i_mem_srcdest_value_ff         (issue_mem_srcdest_value_ff),
815
        .i_pc_plus_8_ff                 (issue_pc_plus_8_ff),
816
        .i_disable_shifter_ff           (issue_shifter_disable_ff),
817
 
818
        // Next CPSR.
819
        .i_cpsr_nxt                     (alu_cpsr_nxt),
820
        .i_cpsr_ff                      (alu_flags_ff),
821
 
822
        // Feedback
823
        .i_alu_value_nxt                (alu_alu_result_nxt),
824
        .i_alu_dav_nxt                  (alu_dav_nxt),
825
 
826
        // Switch indicator.
827
        .i_switch_ff                    (issue_switch_ff),
828
        .o_switch_ff                    (shifter_switch_ff),
829
 
830
        // Force32
831
        .i_force32align_ff              (issue_force32_ff),
832
        .o_force32align_ff              (shifter_force32_ff),
833
 
834
        // Outputs.
835
 
836
        .o_mem_srcdest_value_ff         (shifter_mem_srcdest_value_ff),
837
        .o_alu_source_value_ff          (shifter_alu_source_value_ff),
838
        .o_shifted_source_value_ff      (shifter_shifted_source_value_ff),
839
        .o_shift_carry_ff               (shifter_shift_carry_ff),
840
 
841
        .o_pc_plus_8_ff                 (shifter_pc_plus_8_ff),
842
 
843
        .o_mem_srcdest_index_ff         (shifter_mem_srcdest_index_ff),
844
        .o_mem_load_ff                  (shifter_mem_load_ff),
845
        .o_mem_store_ff                 (shifter_mem_store_ff),
846
        .o_mem_pre_index_ff             (shifter_mem_pre_index_ff),
847
        .o_mem_unsigned_byte_enable_ff  (shifter_mem_unsigned_byte_enable_ff),
848
        .o_mem_signed_byte_enable_ff    (shifter_mem_signed_byte_enable_ff),
849
        .o_mem_signed_halfword_enable_ff(shifter_mem_signed_halfword_enable_ff),
850
        .o_mem_unsigned_halfword_enable_ff(shifter_mem_unsigned_halfword_enable_ff),
851
        .o_mem_translate_ff             (shifter_mem_translate_ff),
852
 
853
        .o_condition_code_ff            (shifter_condition_code_ff),
854
        .o_destination_index_ff         (shifter_destination_index_ff),
855
        .o_alu_operation_ff             (shifter_alu_operation_ff),
856
        .o_flag_update_ff               (shifter_flag_update_ff),
857
 
858
        // Interrupts.
859
        .o_irq_ff                       (shifter_irq_ff),
860
        .o_fiq_ff                       (shifter_fiq_ff),
861
        .o_abt_ff                       (shifter_abt_ff),
862
        .o_swi_ff                       (shifter_swi_ff),
863
 
864
        // Stall
865
        .o_stall_from_shifter           (stall_from_shifter)
866
);
867
 
868
// ===============
869
// ALU STAGE 
870
// ===============
871
 
872
zap_alu_main #(
873
        .PHY_REGS(PHY_REGS),
874
        .SHIFT_OPS(SHIFT_OPS),
875
        .ALU_OPS(ALU_OPS)
876
)
877
u_zap_alu_main
878
(
879 43 Revanth
        .i_decompile                    (shifter_decompile),
880
        .o_decompile                    (alu_decompile),
881 26 Revanth
 
882 43 Revanth
        .i_hijack                       ( wb_hijack     ),
883
        .i_hijack_op1                   ( wb_hijack_op1 ),
884
        .i_hijack_op2                   ( wb_hijack_op2 ),
885
        .i_hijack_cin                   ( wb_hijack_cin ),
886
        .o_hijack_sum                   ( alu_hijack_sum ),
887 26 Revanth
 
888 43 Revanth
        .i_taken_ff                     (shifter_taken_ff),
889
        .o_confirm_from_alu             (confirm_from_alu),
890 26 Revanth
 
891
        .i_pc_ff                        (shifter_pc_ff),
892
 
893 43 Revanth
        .i_und_ff                       (shifter_und_ff),
894
        .o_und_ff                       (alu_und_ff),
895 26 Revanth
 
896 43 Revanth
        .i_nozero_ff                    ( shifter_nozero_ff ),
897 26 Revanth
 
898 43 Revanth
         .i_clk                          (i_clk),
899 26 Revanth
         .i_reset                        (reset),
900 43 Revanth
         .i_clear_from_writeback         (clear_from_writeback),
901
         .i_data_stall                   (data_stall),
902
         .i_cpsr_nxt                     (cpsr_nxt),
903 26 Revanth
         .i_flag_update_ff               (shifter_flag_update_ff),
904
         .i_switch_ff                    (shifter_switch_ff),
905
 
906
         .i_force32align_ff              (shifter_force32_ff),
907
 
908
         .i_mem_srcdest_value_ff        (shifter_mem_srcdest_value_ff),
909
         .i_alu_source_value_ff         (shifter_alu_source_value_ff),
910
         .i_shifted_source_value_ff     (shifter_shifted_source_value_ff),
911
         .i_shift_carry_ff              (shifter_shift_carry_ff),
912
         .i_pc_plus_8_ff                (shifter_pc_plus_8_ff),
913
 
914
         .i_abt_ff                      (shifter_abt_ff),
915
         .i_irq_ff                      (shifter_irq_ff),
916
         .i_fiq_ff                      (shifter_fiq_ff),
917
         .i_swi_ff                      (shifter_swi_ff),
918
 
919
         .i_mem_srcdest_index_ff        (shifter_mem_srcdest_index_ff),
920
         .i_mem_load_ff                 (shifter_mem_load_ff),
921
         .i_mem_store_ff                (shifter_mem_store_ff),
922
         .i_mem_pre_index_ff            (shifter_mem_pre_index_ff),
923
         .i_mem_unsigned_byte_enable_ff (shifter_mem_unsigned_byte_enable_ff),
924
         .i_mem_signed_byte_enable_ff   (shifter_mem_signed_byte_enable_ff),
925
         .i_mem_signed_halfword_enable_ff(shifter_mem_signed_halfword_enable_ff),
926
         .i_mem_unsigned_halfword_enable_ff(shifter_mem_unsigned_halfword_enable_ff),
927
         .i_mem_translate_ff            (shifter_mem_translate_ff),
928
 
929
         .i_condition_code_ff           (shifter_condition_code_ff),
930
         .i_destination_index_ff        (shifter_destination_index_ff),
931
         .i_alu_operation_ff            (shifter_alu_operation_ff),  // {OP,S}
932
 
933
         .i_data_mem_fault              (i_data_wb_err),
934
 
935
         .o_alu_result_nxt              (alu_alu_result_nxt),
936
 
937
         .o_alu_result_ff               (alu_alu_result_ff),
938
 
939
         .o_abt_ff                      (alu_abt_ff),
940
         .o_irq_ff                      (alu_irq_ff),
941
         .o_fiq_ff                      (alu_fiq_ff),
942
         .o_swi_ff                      (alu_swi_ff),
943
 
944
         .o_dav_ff                      (alu_dav_ff),
945
         .o_dav_nxt                     (alu_dav_nxt),
946
 
947
         .o_pc_plus_8_ff                (alu_pc_plus_8_ff),
948
 
949
         // Data access address. Ignore [1:0].
950
         .o_mem_address_ff              (alu_address_ff),
951
         .o_clear_from_alu              (clear_from_alu),
952
         .o_pc_from_alu                 (pc_from_alu),
953
         .o_destination_index_ff        (alu_destination_index_ff),
954
         .o_flags_ff                    (alu_flags_ff),       // Output flags.
955
         .o_flags_nxt                   (alu_cpsr_nxt),
956
 
957
         .o_mem_srcdest_value_ff           (),
958
         .o_mem_srcdest_index_ff           (alu_mem_srcdest_index_ff),
959
         .o_mem_load_ff                    (alu_mem_load_ff),
960
         .o_mem_store_ff                   (),
961
 
962
         .o_ben_ff                         (),
963
 
964
         .o_mem_unsigned_byte_enable_ff    (alu_ubyte_ff),
965
         .o_mem_signed_byte_enable_ff      (alu_sbyte_ff),
966
         .o_mem_signed_halfword_enable_ff  (alu_shalf_ff),
967
         .o_mem_unsigned_halfword_enable_ff(alu_uhalf_ff),
968
         .o_mem_translate_ff               (o_mem_translate),
969
 
970
        .o_address_nxt ( alu_address_nxt ),
971
 
972
        .o_data_wb_we_nxt  (o_data_wb_we_nxt),
973
        .o_data_wb_cyc_nxt (o_data_wb_cyc_nxt),
974
        .o_data_wb_stb_nxt (o_data_wb_stb_nxt),
975
        .o_data_wb_dat_nxt (o_data_wb_dat_nxt),
976
        .o_data_wb_sel_nxt (o_data_wb_sel_nxt),
977
 
978
        .o_data_wb_we_ff   (o_data_wb_we),
979
        .o_data_wb_cyc_ff  (o_data_wb_cyc),
980
        .o_data_wb_stb_ff  (o_data_wb_stb),
981
        .o_data_wb_dat_ff  (o_data_wb_dat),
982
        .o_data_wb_sel_ff  (o_data_wb_sel)
983
 
984
);
985
 
986
// ====================
987
// MEMORY 
988
// ====================
989
 
990
zap_memory_main #(
991
       .PHY_REGS(PHY_REGS)
992
)
993
u_zap_memory_main
994
(
995 43 Revanth
        .i_decompile                    (alu_decompile),
996
        .o_decompile                    (memory_decompile),
997 26 Revanth
 
998 43 Revanth
        .i_und_ff                       (alu_und_ff),
999
        .o_und_ff                       (memory_und_ff),
1000 26 Revanth
 
1001
        .i_mem_address_ff               (alu_address_ff),
1002
 
1003
 
1004
        .i_clk                          (i_clk),
1005
        .i_reset                        (reset),
1006
 
1007
        .i_sbyte_ff                     (alu_sbyte_ff),     // Signed byte.
1008
        .i_ubyte_ff                     (alu_ubyte_ff),     // Unsigned byte.
1009
        .i_shalf_ff                     (alu_shalf_ff),     // Signed half word.
1010
        .i_uhalf_ff                     (alu_uhalf_ff),     // Unsigned half word.
1011
 
1012
        .i_clear_from_writeback         (clear_from_writeback),
1013 43 Revanth
        .i_data_stall                   (data_stall),
1014 26 Revanth
        .i_alu_result_ff                (alu_alu_result_ff),
1015
        .i_flags_ff                     (alu_flags_ff),
1016
 
1017
        .i_mem_load_ff                  (alu_mem_load_ff),
1018
 
1019
        .i_mem_rd_data                 (i_data_wb_dat),// From memory.
1020
 
1021
        .i_mem_fault                    (i_data_wb_err),      // From cache.
1022
 
1023
        .o_mem_fault                    (memory_data_abt_ff),
1024
 
1025
 
1026
        .i_dav_ff                       (alu_dav_ff),
1027
        .i_pc_plus_8_ff                 (alu_pc_plus_8_ff),
1028
 
1029
        .i_destination_index_ff         (alu_destination_index_ff),
1030
 
1031
        .i_irq_ff                       (alu_irq_ff),
1032
        .i_fiq_ff                       (alu_fiq_ff),
1033
        .i_instr_abort_ff               (alu_abt_ff),
1034
        .i_swi_ff                       (alu_swi_ff),
1035
 
1036
        // Used to speed up loads. 
1037
        .i_mem_srcdest_index_ff         (alu_mem_srcdest_index_ff),
1038
 
1039
        // Can come in handy since this is reused for several other things.
1040
        .i_mem_srcdest_value_ff         (o_data_wb_dat),
1041
 
1042
        .o_alu_result_ff                (memory_alu_result_ff),
1043
        .o_flags_ff                     (memory_flags_ff),
1044
 
1045
        .o_destination_index_ff         (memory_destination_index_ff),
1046
        .o_mem_srcdest_index_ff         (memory_mem_srcdest_index_ff),
1047
 
1048
        .o_dav_ff                       (memory_dav_ff),
1049
        .o_pc_plus_8_ff                 (memory_pc_plus_8_ff),
1050
 
1051
        .o_irq_ff                       (memory_irq_ff),
1052
        .o_fiq_ff                       (memory_fiq_ff),
1053
        .o_swi_ff                       (memory_swi_ff),
1054
        .o_instr_abort_ff               (memory_instr_abort_ff),
1055
 
1056
        .o_mem_load_ff                  (memory_mem_load_ff),
1057
 
1058
 
1059
        .o_mem_rd_data                 (memory_mem_rd_data)
1060
);
1061
 
1062
// ==================
1063
// WRITEBACK 
1064
// ==================
1065
 
1066
zap_writeback #(
1067
        .PHY_REGS(PHY_REGS)
1068
)
1069
u_zap_writeback
1070
(
1071
        .i_decompile            (memory_decompile),
1072
        .o_decompile            (rb_decompile),
1073
 
1074
        .o_shelve               (shelve),
1075
 
1076
        .i_clk                  (i_clk), // ZAP clock.
1077
 
1078
 
1079
        .i_reset                (reset),           // ZAP reset.
1080
        .i_valid                (memory_dav_ff),
1081 43 Revanth
        .i_data_stall           (data_stall),
1082 26 Revanth
        .i_clear_from_alu       (clear_from_alu),
1083
        .i_pc_from_alu          (pc_from_alu),
1084
        .i_stall_from_decode    (stall_from_decode),
1085
        .i_stall_from_issue     (stall_from_issue),
1086
        .i_stall_from_shifter   (stall_from_shifter),
1087
 
1088
        .i_thumb                (alu_flags_ff[T]), // To indicate thumb state.
1089
 
1090
        .i_clear_from_decode    (clear_from_decode),
1091
        .i_pc_from_decode       (pc_from_decode),
1092
 
1093 43 Revanth
        .i_code_stall           (code_stall),
1094 26 Revanth
 
1095
        // Used to valid writes on i_wr_index1.
1096
        .i_mem_load_ff          (memory_mem_load_ff),
1097
 
1098
        .i_rd_index_0           (rd_index_0),
1099
        .i_rd_index_1           (rd_index_1),
1100
        .i_rd_index_2           (rd_index_2),
1101
        .i_rd_index_3           (rd_index_3),
1102
 
1103
        .i_wr_index             (memory_destination_index_ff),
1104
        .i_wr_data              (memory_alu_result_ff),
1105
        .i_flags                (memory_flags_ff),
1106
        .i_wr_index_1           (memory_mem_srcdest_index_ff),// load index.
1107
        .i_wr_data_1            (memory_mem_rd_data),         // load data.
1108
 
1109
        .i_irq                  (memory_irq_ff),
1110
        .i_fiq                  (memory_fiq_ff),
1111
        .i_instr_abt            (memory_instr_abort_ff),
1112
        .i_data_abt             (memory_data_abt_ff),
1113
        .i_swi                  (memory_swi_ff),
1114
        .i_und                  (memory_und_ff),
1115
 
1116
        .i_pc_buf_ff            (memory_pc_plus_8_ff),
1117
 
1118
        .i_copro_reg_en         (copro_reg_en),
1119
        .i_copro_reg_wr_index   (copro_reg_wr_index),
1120
        .i_copro_reg_rd_index   (copro_reg_rd_index),
1121
        .i_copro_reg_wr_data    (copro_reg_wr_data),
1122
 
1123
        .o_copro_reg_rd_data_ff (copro_reg_rd_data),
1124
 
1125
        .o_rd_data_0            (rd_data_0),
1126
        .o_rd_data_1            (rd_data_1),
1127
        .o_rd_data_2            (rd_data_2),
1128
        .o_rd_data_3            (rd_data_3),
1129
 
1130
        .o_pc                   (o_instr_wb_adr),
1131
        .o_pc_nxt               (o_instr_wb_adr_nxt),
1132
        .o_cpsr_nxt             (cpsr_nxt),
1133
        .o_clear_from_writeback (clear_from_writeback),
1134
 
1135
        .o_hijack               (wb_hijack),
1136
        .o_hijack_op1           (wb_hijack_op1),
1137
        .o_hijack_op2           (wb_hijack_op2),
1138
        .o_hijack_cin           (wb_hijack_cin),
1139
 
1140
        .i_hijack_sum           (alu_hijack_sum)
1141
);
1142
 
1143
// ==================================
1144
// CP15 CB
1145
// ==================================
1146
 
1147
zap_cp15_cb u_zap_cp15_cb (
1148
        .i_clk                  (i_clk),
1149
        .i_reset                (i_reset),
1150
        .i_cp_word              (copro_word),
1151
        .i_cp_dav               (copro_dav),
1152
        .o_cp_done              (copro_done),
1153
        .i_cpsr                 (o_cpsr),
1154
        .o_reg_en               (copro_reg_en),
1155
        .o_reg_wr_data          (copro_reg_wr_data),
1156
        .i_reg_rd_data          (copro_reg_rd_data),
1157
        .o_reg_wr_index         (copro_reg_wr_index),
1158
        .o_reg_rd_index         (copro_reg_rd_index),
1159
 
1160
        .i_fsr                  (i_fsr),
1161
        .i_far                  (i_far),
1162
        .o_dac                  (o_dac),
1163
        .o_baddr                (o_baddr),
1164
        .o_mmu_en               (o_mmu_en),
1165
        .o_sr                   (o_sr),
1166 43 Revanth
        .o_pid                  (o_pid),
1167 26 Revanth
        .o_dcache_inv           (o_dcache_inv),
1168
        .o_icache_inv           (o_icache_inv),
1169
        .o_dcache_clean         (o_dcache_clean),
1170
        .o_icache_clean         (o_icache_clean),
1171
        .o_dtlb_inv             (o_dtlb_inv),
1172
        .o_itlb_inv             (o_itlb_inv),
1173
        .o_dcache_en            (o_dcache_en),
1174
        .o_icache_en            (o_icache_en),
1175
        .i_dcache_inv_done      (i_dcache_inv_done),
1176
        .i_icache_inv_done      (i_icache_inv_done),
1177
        .i_dcache_clean_done    (i_dcache_clean_done),
1178
        .i_icache_clean_done    (i_icache_clean_done)
1179
);
1180
 
1181
reg [(8*8)-1:0] CPU_MODE; // Max 8 characters i.e. 64-bit string.
1182
 
1183
always @*
1184
case(o_cpsr[`CPSR_MODE])
1185 43 Revanth
FIQ:     CPU_MODE = "FIQ";
1186
IRQ:     CPU_MODE = "IRQ";
1187
USR:     CPU_MODE = "USR";
1188
UND:     CPU_MODE = "UND";
1189
SVC:     CPU_MODE = "SVC";
1190
ABT:     CPU_MODE = "ABT";
1191
SYS:     CPU_MODE = "SYS";
1192
default: CPU_MODE = "???";
1193 26 Revanth
endcase
1194
 
1195
 
1196
endmodule // zap_core.v
1197 43 Revanth
 
1198 26 Revanth
`default_nettype wire

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