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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decompile.v] - Blame information for rev 39

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1 26 Revanth
// ---------------------------------------------------------------------------
2
// --                                                                       --
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// --                   (C) 2016-2018 Revanth Kamaraj.                      --
4
// --                                                                       -- 
5
// -- ------------------------------------------------------------------------
6
// --                                                                       --
7
// -- This program is free software; you can redistribute it and/or         --
8
// -- modify it under the terms of the GNU General Public License           --
9
// -- as published by the Free Software Foundation; either version 2        --
10
// -- of the License, or (at your option) any later version.                --
11
// --                                                                       --
12
// -- This program is distributed in the hope that it will be useful,       --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of        --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         --
15
// -- GNU General Public License for more details.                          --
16
// --                                                                       --
17
// -- You should have received a copy of the GNU General Public License     --
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// -- along with this program; if not, write to the Free Software           --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA         --
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// -- 02110-1301, USA.                                                      --
21
// --                                                                       --
22
// ---------------------------------------------------------------------------
23
// --                                                                       --       
24
// -- When running in simulation mode, this module will decompile binary    --
25
// -- ARM instructions to assembler instructions for debug purposes.        --
26
// -- When running in synthesis mode, the output of this module is tied     --       
27
// -- to a constant since this module really finds use only in debug.       --       
28
// --                                                                       --
29
// ---------------------------------------------------------------------------
30
 
31
`default_nettype none
32
 
33
module zap_decompile #(parameter INS_WDT = 36) (
34
                input wire      [36-1:0]        i_instruction,  // 36-bit instruction.
35
                input wire                      i_dav,          // Instruction valid.
36
                output reg      [64*8-1:0]      o_decompile     // 1024 bytes max of assembler string.
37
        );
38
 
39
`ifndef SYNTHESIS // if simulating...
40
 
41
`include "zap_defines.vh"
42
`include "zap_localparams.vh"
43
`include "zap_functions.vh"
44
 
45
 
46
// These defines can be wrapped around a single `ifndef instead of several of
47
// them as shown.
48
 
49
`ifndef CCC
50
        `define CCC cond_code(i_instruction[31:28])
51
`endif
52
 
53
`ifndef CRB
54
        `define CRB arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]})
55
`endif
56
 
57
`ifndef CRD
58
        `define CRD arch_reg_num({i_instruction[`DP_RD_EXTEND], i_instruction[`DP_RD]})
59
`endif
60
 
61
`ifndef CDR1
62
        `define CRD1 arch_reg_num({i_instruction[`SRCDEST_EXTEND], i_instruction[`SRCDEST]})
63
`endif
64
 
65
`ifndef CRN
66
        `define CRN arch_reg_num({i_instruction[`DP_RA_EXTEND], i_instruction[`DP_RA]})
67
`endif
68
 
69
`ifndef CRN1
70
        `define CRN1 arch_reg_num({i_instruction[`BASE_EXTEND], i_instruction[`BASE]})
71
`endif
72
 
73
`ifndef COPCODE
74
        `define COPCODE get_opcode({i_instruction[`OPCODE_EXTEND], i_instruction[24:21]})
75
`endif
76
 
77
`ifndef CSHTYPE
78
        `define CSHTYPE get_shtype(i_instruction[6:5])
79
`endif
80
 
81
`ifndef CRS
82
        `define CRS arch_reg_num(i_instruction[11:8]);
83
`endif
84
 
85
`ifndef CRM
86
        `define CRM arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]});
87
`endif
88
 
89
// Decompile block. Makes task calls.
90
always @*
91
begin
92
                if ( !i_dav )
93
                begin
94
                        o_decompile = "IGNORE";
95
                end
96
                else if ( i_instruction[27:24] == 4'b1110 && i_instruction[4] )
97
                begin
98
                        if ( i_instruction[20] )  // R <- CPSR
99
                                $sformat(o_decompile, "MRC%s", `CCC);
100
                        else
101
                                $sformat(o_decompile, "MCR%s", `CCC);
102
                end
103
                else if ( i_instruction[27:25] == 3'b100 ) // LDMSTM
104
                begin
105
                        if ( i_instruction[20] ) // Load
106
                                $sformat(o_decompile, "LDM%s %b %s %b", `CCC, i_instruction[24:20], i_instruction[19:16], i_instruction[15:0]);
107
                        else
108 32 Revanth
                                $sformat(o_decompile, "STM%s %b %s %b", `CCC, i_instruction[24:20], i_instruction[19:16], i_instruction[15:0]);
109 26 Revanth
                end
110
                else
111
                casez ( i_instruction[31:0] )
112
                BX_INST:                                        decode_bx          ( i_instruction ); //
113
                MRS:                                            decode_mrs         ( i_instruction ); //  
114
                MSR_IMMEDIATE:                                  decode_msr_immed   ( i_instruction ); //
115
                MSR:                                            decode_msr         ( i_instruction ); //
116
                DATA_PROCESSING_IMMEDIATE:                      decode_dp_immed    ( i_instruction ); //
117
                DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT:       decode_dp_rss      ( i_instruction ); //
118
                DATA_PROCESSING_INSTRUCTION_SPECIFIED_SHIFT:    decode_dp_iss      ( i_instruction ); //
119
                BRANCH_INSTRUCTION:                             decode_branch      ( i_instruction ); //   
120
                LS_INSTRUCTION_SPECIFIED_SHIFT:                 decode_ls_iss      ( i_instruction ); //
121
                LS_IMMEDIATE:                                   decode_ls          ( i_instruction ); //
122
                MULT_INST:                                      decode_mult        ( i_instruction ); //
123
                LMULT_INST:                                     decode_lmult       ( i_instruction ); //
124
                HALFWORD_LS:                                    decode_halfword_ls ( i_instruction ); // 
125
                SOFTWARE_INTERRUPT:                             decode_swi         ( i_instruction ); //
126
 
127
                default:
128
                begin
129
                        o_decompile = "UNRECOGNIZED INSTRUCTION!";
130
                end
131
                endcase
132
end
133
 
134
task decode_swi ( input [INS_WDT-1:0] i_instruction );
135
begin
136
        $sformat(o_decompile, "SWIAL %0d", $unsigned(i_instruction[24:0]));
137
end
138
endtask
139
 
140
task decode_branch ( input [INS_WDT-1:0] i_instruction );
141
begin
142
        if ( !i_instruction[24] )
143
                $sformat(o_decompile, "B%s %0d", `CCC, $signed(i_instruction[23:0]));
144
        else
145
                $sformat(o_decompile, "BL%s %0d", `CCC, $signed(i_instruction[23:0]));
146
end
147
endtask
148
 
149
task decode_bx ( input [INS_WDT-1:0] i_instruction );
150
begin
151
        $sformat(o_decompile, "BX%s %s", `CCC, `CRB );
152
end
153
endtask
154
 
155
task decode_dp_immed ( input [INS_WDT-1:0] i_instruction );
156
begin:blk111
157
        reg [6*8-1:0] opcode; reg [4*8-1:0] cc, dest_reg, src_reg;
158
        integer imm_amt, ror_amt;
159
 
160
        opcode   = `COPCODE;
161
        cc       = `CCC;
162
        dest_reg = `CRD;
163
        src_reg  = `CRN;
164
        imm_amt  = $unsigned(i_instruction[7:0]);
165
        ror_amt  = $unsigned(i_instruction[11:8]);
166
 
167
        $sformat(o_decompile, "%s%s %s,%s,%0d ROR %0d", opcode, cc, dest_reg, src_reg, imm_amt, ror_amt);
168
end
169
endtask
170
 
171
task decode_dp_rss ( input [INS_WDT-1:0] i_instruction );
172
begin:bk222
173
        reg [4*8-1:0] cc, dest_reg, src_reg, sh_src_reg, shamt_reg;
174
        reg [6*8-1:0] opcode;
175
        reg [5*8-1:0] shtype;
176
        integer shamt;
177
 
178
        opcode      = `COPCODE;
179
        cc          = `CCC;
180
        dest_reg    = `CRD;
181
        src_reg     = `CRN;
182
        shtype      = `CSHTYPE;
183
        sh_src_reg  = `CRM;
184
        shamt_reg   = `CRS;
185
 
186
        $sformat(o_decompile, "%s%s %s,%s,%s %s %s", opcode, cc, dest_reg, src_reg, sh_src_reg, shtype, shamt_reg);
187
end
188
endtask
189
 
190
task decode_dp_iss ( input [INS_WDT-1:0] i_instruction );
191
begin:blk333
192
        reg [4*8-1:0] cc, dest_reg, src_reg, sh_src_reg;
193
        reg [6*8-1:0] opcode;
194
        reg [4*8-1:0] shtype;
195
        integer shamt;
196
 
197
        opcode      = `COPCODE;
198
        cc          = `CCC;
199
        dest_reg    = `CRD;
200
        src_reg     = `CRN;
201
        shtype      = `CSHTYPE;
202
        sh_src_reg  = `CRM;
203
        shamt       = $unsigned(i_instruction[11:7]);
204
 
205
        $sformat(o_decompile, "%s%s %s,%s,%s %s %0d", opcode, cc, dest_reg, src_reg, sh_src_reg, shtype, shamt);
206
end
207
endtask
208
 
209
task decode_mrs ( input [INS_WDT-1:0] i_instruction );
210
begin
211
        if ( i_instruction[22] ) // SPSR
212
                $sformat(o_decompile, "MRS%s %s,SPSR",`CCC, `CRD);
213
        else                     // CPSR
214
                $sformat(o_decompile, "MRS%s %s,CPSR",`CCC, `CRD);
215
end
216
endtask
217
 
218
task decode_msr ( input [INS_WDT-1:0] i_instruction );
219
begin
220
        if ( i_instruction[22] ) // SPSR
221
                $sformat(o_decompile, "MSR%s SPSR,%s",`CCC, `CRB);
222
        else
223
                $sformat(o_decompile, "MSR%s CPSR,%s", `CCC, `CRB);
224
end
225
endtask
226
 
227
task decode_msr_immed ( input [INS_WDT-1:0] i_instruction );
228
begin
229
         if ( i_instruction[22] ) // SPSR
230
                $sformat(o_decompile, "MSR%s SPSR,%dROR%d",`CCC, $unsigned(i_instruction[7:0]), $unsigned(i_instruction[11:8]));
231
        else
232
                $sformat(o_decompile, "MSR%s CPSR,%dROR%d",`CCC, $unsigned(i_instruction[7:0]), $unsigned(i_instruction[11:8]));
233
end
234
endtask
235
 
236
// LS ISS
237
task decode_ls_iss ( input [INS_WDT-1:0] i_instruction );
238
begin:blk2323
239
        reg [32*8-1:0] ls_iss_offset;
240
 
241
        $sformat(ls_iss_offset, "%s%s%d", `CRB, `CSHTYPE, $unsigned(i_instruction[11:7]));
242
 
243
        // If word load
244
        if ( i_instruction[20] )
245
                if ( !i_instruction[22] )
246
                begin
247
                case ( {i_instruction[24], i_instruction[21]} )
248
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
249
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s,%s]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
250
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s],%s" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
251
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
252
                endcase
253
                end
254
                else
255
                begin
256
                case( {i_instruction[24], i_instruction[21]}  )
257
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
258
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s,%s]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
259
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s],%s" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
260
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
261
                endcase
262
                end
263
        else
264
                if ( !i_instruction[22] )
265
                begin
266
                case ( {i_instruction[24], i_instruction[21]} )
267
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
268
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%s %s[%s,%s]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
269
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%s %s[%s],%s",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
270
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
271
                endcase
272
                end
273
                else
274
                begin
275
                case( {i_instruction[24], i_instruction[21]} )
276
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
277
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s,%s]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
278
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s],%s",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
279
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
280
                endcase
281
                end
282
end
283
endtask
284
 
285
// LS immediate
286
task decode_ls ( input [INS_WDT-1:0] i_instruction );
287
begin:blk4343
288
        integer ls_iss_offset; // Forgive the naming convention...
289
 
290
        ls_iss_offset = i_instruction[11:0];
291
 
292
        // If word load
293
        if ( i_instruction[20] )
294
                if ( !i_instruction[22] )
295
                begin
296
                case ( {i_instruction[24], i_instruction[21]} )
297
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
298
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s,%0d]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
299
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s],%0d" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
300
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
301
                endcase
302
                end
303
                else
304
                begin
305
                case( {i_instruction[24], i_instruction[21]}  )
306
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
307
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s,%0d]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
308
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s],%0d" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
309
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
310
                endcase
311
                end
312
        else
313
                if ( !i_instruction[22] )
314
                begin
315
                case ( {i_instruction[24], i_instruction[21]} )
316
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
317
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%s %s[%s,%0d]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
318
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%s %s[%s],%0d",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
319
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
320
                endcase
321
                end
322
                else
323
                begin
324
                case( {i_instruction[24], i_instruction[21]} )
325
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
326
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s,%0d]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
327
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s],%0d",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
328
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
329
                endcase
330
                end
331
 
332
end
333
endtask
334
 
335
// Mult. MUL, MLA
336
task decode_mult ( input [INS_WDT-1:0] i_instruction );
337
begin
338
        if ( i_instruction[21] == 1'd0 )
339 39 Revanth
                $sformat(o_decompile, "MUL%s %s,%s,%s",`CCC,`CRN,`CRD,arch_reg_num(i_instruction[11:8]));
340 26 Revanth
        else
341 39 Revanth
                $sformat(o_decompile, "MLA%s %s,%s,%s,%s",`CCC,`CRN,`CRD,arch_reg_num(i_instruction[11:8]), arch_reg_num(i_instruction[3:0]));
342 26 Revanth
end
343
endtask
344
 
345
`ifndef XUMULL
346
 
347
        `define XUMULL 3'b100
348
        `define XUMLAL 3'b101
349
        `define XSMULL 3'b110
350
        `define XSMLAL 3'b111
351
 
352
`endif
353
 
354
// Long Mult. UMULL, UMLAL, SMULL, SMLAL
355
task decode_lmult ( input [INS_WDT-1:0] i_instruction );
356
begin
357
      case(i_instruction[23:21])
358
        `XUMULL: $sformat(o_decompile, "UMULL %s:%s=%s*%s" ,i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
359
        `XUMLAL: $sformat(o_decompile, "UMLAL %s:%s+=%s*%s",i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
360
        `XSMULL: $sformat(o_decompile, "SMULL %s:%s=%s*%s" ,i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
361
        `XSMLAL: $sformat(o_decompile, "SMLAL %s:%s+=%s*%s",i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
362
      endcase
363
end
364
endtask
365
 
366
task decode_halfword_ls ( input [INS_WDT-1:0] i_instruction );
367
begin
368
      o_decompile = "***HALFWORD LD/ST***";
369
end
370
endtask
371
 
372
// Returns shift type.
373
function [4*8-1:0] get_shtype ( input [2:0] x );
374
begin
375
        case(x)
376
        0: get_shtype = "LSL";
377
        1: get_shtype = "LSR";
378
        2: get_shtype = "ASR";
379
        3: get_shtype = "ROR";
380
        4: get_shtype = "RRC";
381
        5: get_shtype = "RORI";
382
        6: get_shtype = "ROR1";
383
        7: get_shtype = "<-->";
384
        endcase
385
end
386
endfunction
387
 
388
// Returns opcode in english.
389
function [6*8-1:0] get_opcode ( input [4:0] x );
390
begin
391
        case(x)
392
        0: get_opcode = "AND"        ;  //= 0;
393
        1: get_opcode = "EOR"        ;  //= 1;
394
        2: get_opcode = "SUB"        ;  //= 2;
395
        3: get_opcode = "RSB"        ;  //= 3;
396
        4: get_opcode = "ADD"        ;  //= 4;
397
        5: get_opcode = "ADC"        ;  //= 5;
398
        6: get_opcode = "SBC"        ;  //= 6;
399
        7: get_opcode = "RSC"        ;  //= 7;
400
        8: get_opcode = "TST"        ;  //= 8;
401
        9: get_opcode = "TEQ"        ;  //= 9;
402
        10:get_opcode = "CMP"        ;  //= 10;
403
        11:get_opcode = "CMN"        ;  //= 11;
404
        12:get_opcode = "ORR"        ;  //= 12;
405
        13:get_opcode = "MOV"        ;  //= 13;
406
        14:get_opcode = "BIC"        ;  //= 14;
407
        15:get_opcode = "MVN"        ;  //= 15;
408
        16:get_opcode = "MUL"        ;  //= 16; // Multiply ( 32 x 32 = 32 ) -> Translated to MAC.
409
        17:get_opcode = "MLA"        ;  //= 17; // Multiply-Accumulate ( 32 x 32 + 32 = 32 ). 
410
        18:get_opcode = "FMOV"       ;  //= 18; 
411
        19:get_opcode = "MMOV"       ;  //= 19; 
412
        20:get_opcode = "UMLALL"     ;  //= 20; // Unsigned multiply accumulate (Write lower reg).
413
        21:get_opcode = "UMLALH"     ;  //= 21;
414
        22:get_opcode = "SMLALL"     ;  //= 22; // Signed multiply accumulate (Write lower reg).
415
        23:get_opcode = "SMLALH"     ;  //= 23;
416
        24:get_opcode = "CLZ"        ;  //= 24; // Count Leading zeros.
417
        default: get_opcode = "<-->";
418
        endcase
419
end
420
endfunction
421
 
422
// Returns arch reg number (5 bit number as input.)
423
function [4*8-1:0] arch_reg_num ( input [4:0] reg_num );
424
begin:blk434234
425
        reg [4*8-1:0] x;
426
 
427
        case(reg_num)
428
                5'd0 :  x = "R0  ";
429
                5'd1 :  x = "R1  ";
430
                5'd2 :  x = "R2  ";
431
                5'd3 :  x = "R3  ";
432
                5'd4 :  x = "R4  ";
433
                5'd5 :  x = "R5  ";
434
                5'd6 :  x = "R6  ";
435
                5'd7 :  x = "R7  ";
436
                5'd8 :  x = "R8  ";
437
                5'd9 :  x = "R9  ";
438
                5'd10 : x = "R10 ";
439
                5'd11 : x = "R11 ";
440
                5'd12 : x = "R12 ";
441
                5'd13 : x = "SP  ";
442
                5'd14 : x = "LR  ";
443
                5'd15 : x = "PC  ";
444
                5'd16 : x = "RAZ ";
445
                5'd17 : x = "CPSR";
446
                5'd18 : x = "R8x ";
447
                5'd19 : x = "R9x ";
448
                5'd20 : x = "R10x";
449
                5'd21 : x = "R11x";
450
                5'd22 : x = "R12x";
451
                5'd23 : x = "R13x";
452
                5'd24 : x = "R14x";
453
                5'd25 : x = "DMY0";
454
                5'd26 : x = "DMY1";
455
                5'd27 : x = "SPSR";
456
                5'd28 : x = "<-->";
457
                5'd29 : x = "<-->";
458
                5'd30 : x = "<-->";
459
                5'd31 : x = "<-->";
460
           endcase
461
 
462
        arch_reg_num = x;
463
end
464
endfunction
465
 
466
// Returns a text version of the condition code.
467
function [2*8-1:0] cond_code ( input [3:0] cond );
468
begin: blk49329483
469
        reg [2*8-1:0] ok;
470
 
471
        case(cond)
472
        EQ:     ok = "EQ";
473
        NE:     ok = "NE";
474
        CS:     ok = "CS";
475
        CC:     ok = "CC";
476
        MI:     ok = "MI";
477
        PL:     ok = "PL";
478
        VS:     ok = "VS";
479
        VC:     ok = "VC";
480
        HI:     ok = "HI";
481
        LS:     ok = "LS";
482
        GE:     ok = "GE";
483
        LT:     ok = "LT";
484
        GT:     ok = "GT";
485
        LE:     ok = "LE";
486
        AL:     ok = "AL";
487
        NV:     ok = "NV";
488
        endcase
489
 
490
        cond_code = ok;
491
end
492
endfunction
493
 
494
`else
495
 
496
// `ifdef SYNTHESIS
497
always @*
498
        o_decompile = 0; // In synthesis mode.
499
 
500
`endif
501
 
502
endmodule // zap_decompile.v
503
 
504
`default_nettype wire

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