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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decompile.v] - Blame information for rev 43

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1 26 Revanth
// ---------------------------------------------------------------------------
2
// --                                                                       --
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// --                   (C) 2016-2018 Revanth Kamaraj.                      --
4
// --                                                                       -- 
5
// -- ------------------------------------------------------------------------
6
// --                                                                       --
7
// -- This program is free software; you can redistribute it and/or         --
8
// -- modify it under the terms of the GNU General Public License           --
9
// -- as published by the Free Software Foundation; either version 2        --
10
// -- of the License, or (at your option) any later version.                --
11
// --                                                                       --
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// -- This program is distributed in the hope that it will be useful,       --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of        --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         --
15
// -- GNU General Public License for more details.                          --
16
// --                                                                       --
17
// -- You should have received a copy of the GNU General Public License     --
18
// -- along with this program; if not, write to the Free Software           --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA         --
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// -- 02110-1301, USA.                                                      --
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// --                                                                       --
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// ---------------------------------------------------------------------------
23
// --                                                                       --       
24
// -- When running in simulation mode, this module will decompile binary    --
25
// -- ARM instructions to assembler instructions for debug purposes.        --
26
// -- When running in synthesis mode, the output of this module is tied     --       
27
// -- to a constant since this module really finds use only in debug.       --       
28
// --                                                                       --
29
// ---------------------------------------------------------------------------
30
 
31
`default_nettype none
32
 
33
module zap_decompile #(parameter INS_WDT = 36) (
34 43 Revanth
                input wire      [36-1:0]        i_instruction,  // 36-bit instruction into decode.
35 26 Revanth
                input wire                      i_dav,          // Instruction valid.
36
                output reg      [64*8-1:0]      o_decompile     // 1024 bytes max of assembler string.
37
        );
38
 
39 43 Revanth
`ifndef SYNTHESIS
40 26 Revanth
 
41
`include "zap_defines.vh"
42
`include "zap_localparams.vh"
43
`include "zap_functions.vh"
44
 
45 43 Revanth
`ifndef ZAP_DECOMPILE_DEFINES
46
        `define CCC     cond_code(i_instruction[31:28])
47
        `define CRB     arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]})
48
        `define CRD     arch_reg_num({i_instruction[`DP_RD_EXTEND], i_instruction[`DP_RD]})
49
        `define CRD1    arch_reg_num({i_instruction[`SRCDEST_EXTEND], i_instruction[`SRCDEST]})
50
        `define CRN     arch_reg_num({i_instruction[`DP_RA_EXTEND], i_instruction[`DP_RA]})
51
        `define CRN1    arch_reg_num({i_instruction[`BASE_EXTEND], i_instruction[`BASE]})
52 26 Revanth
        `define COPCODE get_opcode({i_instruction[`OPCODE_EXTEND], i_instruction[24:21]})
53
        `define CSHTYPE get_shtype(i_instruction[6:5])
54 43 Revanth
        `define CRS     arch_reg_num(i_instruction[11:8]);
55
        `define CRM     arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]});
56 26 Revanth
`endif
57
 
58
always @*
59
begin
60
                if ( !i_dav )
61
                begin
62
                        o_decompile = "IGNORE";
63
                end
64
                else if ( i_instruction[27:24] == 4'b1110 && i_instruction[4] )
65
                begin
66
                        if ( i_instruction[20] )  // R <- CPSR
67
                                $sformat(o_decompile, "MRC%s", `CCC);
68
                        else
69
                                $sformat(o_decompile, "MCR%s", `CCC);
70
                end
71
                else if ( i_instruction[27:25] == 3'b100 ) // LDMSTM
72
                begin
73
                        if ( i_instruction[20] ) // Load
74
                                $sformat(o_decompile, "LDM%s %b %s %b", `CCC, i_instruction[24:20], i_instruction[19:16], i_instruction[15:0]);
75
                        else
76 32 Revanth
                                $sformat(o_decompile, "STM%s %b %s %b", `CCC, i_instruction[24:20], i_instruction[19:16], i_instruction[15:0]);
77 26 Revanth
                end
78
                else
79
                casez ( i_instruction[31:0] )
80
                BX_INST:                                        decode_bx          ( i_instruction ); //
81
                MRS:                                            decode_mrs         ( i_instruction ); //  
82
                MSR_IMMEDIATE:                                  decode_msr_immed   ( i_instruction ); //
83
                MSR:                                            decode_msr         ( i_instruction ); //
84
                DATA_PROCESSING_IMMEDIATE:                      decode_dp_immed    ( i_instruction ); //
85
                DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT:       decode_dp_rss      ( i_instruction ); //
86
                DATA_PROCESSING_INSTRUCTION_SPECIFIED_SHIFT:    decode_dp_iss      ( i_instruction ); //
87
                BRANCH_INSTRUCTION:                             decode_branch      ( i_instruction ); //   
88
                LS_INSTRUCTION_SPECIFIED_SHIFT:                 decode_ls_iss      ( i_instruction ); //
89
                LS_IMMEDIATE:                                   decode_ls          ( i_instruction ); //
90
                MULT_INST:                                      decode_mult        ( i_instruction ); //
91
                LMULT_INST:                                     decode_lmult       ( i_instruction ); //
92
                HALFWORD_LS:                                    decode_halfword_ls ( i_instruction ); // 
93
                SOFTWARE_INTERRUPT:                             decode_swi         ( i_instruction ); //
94
 
95
                default:
96
                begin
97
                        o_decompile = "UNRECOGNIZED INSTRUCTION!";
98
                end
99
                endcase
100
end
101
 
102
task decode_swi ( input [INS_WDT-1:0] i_instruction );
103
begin
104
        $sformat(o_decompile, "SWIAL %0d", $unsigned(i_instruction[24:0]));
105
end
106
endtask
107
 
108
task decode_branch ( input [INS_WDT-1:0] i_instruction );
109
begin
110
        if ( !i_instruction[24] )
111
                $sformat(o_decompile, "B%s %0d", `CCC, $signed(i_instruction[23:0]));
112
        else
113
                $sformat(o_decompile, "BL%s %0d", `CCC, $signed(i_instruction[23:0]));
114
end
115
endtask
116
 
117
task decode_bx ( input [INS_WDT-1:0] i_instruction );
118
begin
119
        $sformat(o_decompile, "BX%s %s", `CCC, `CRB );
120
end
121
endtask
122
 
123
task decode_dp_immed ( input [INS_WDT-1:0] i_instruction );
124
begin:blk111
125
        reg [6*8-1:0] opcode; reg [4*8-1:0] cc, dest_reg, src_reg;
126
        integer imm_amt, ror_amt;
127
 
128
        opcode   = `COPCODE;
129
        cc       = `CCC;
130
        dest_reg = `CRD;
131
        src_reg  = `CRN;
132
        imm_amt  = $unsigned(i_instruction[7:0]);
133
        ror_amt  = $unsigned(i_instruction[11:8]);
134
 
135
        $sformat(o_decompile, "%s%s %s,%s,%0d ROR %0d", opcode, cc, dest_reg, src_reg, imm_amt, ror_amt);
136
end
137
endtask
138
 
139
task decode_dp_rss ( input [INS_WDT-1:0] i_instruction );
140
begin:bk222
141
        reg [4*8-1:0] cc, dest_reg, src_reg, sh_src_reg, shamt_reg;
142
        reg [6*8-1:0] opcode;
143
        reg [5*8-1:0] shtype;
144
        integer shamt;
145
 
146
        opcode      = `COPCODE;
147
        cc          = `CCC;
148
        dest_reg    = `CRD;
149
        src_reg     = `CRN;
150
        shtype      = `CSHTYPE;
151
        sh_src_reg  = `CRM;
152
        shamt_reg   = `CRS;
153
 
154
        $sformat(o_decompile, "%s%s %s,%s,%s %s %s", opcode, cc, dest_reg, src_reg, sh_src_reg, shtype, shamt_reg);
155
end
156
endtask
157
 
158
task decode_dp_iss ( input [INS_WDT-1:0] i_instruction );
159
begin:blk333
160
        reg [4*8-1:0] cc, dest_reg, src_reg, sh_src_reg;
161
        reg [6*8-1:0] opcode;
162
        reg [4*8-1:0] shtype;
163
        integer shamt;
164
 
165
        opcode      = `COPCODE;
166
        cc          = `CCC;
167
        dest_reg    = `CRD;
168
        src_reg     = `CRN;
169
        shtype      = `CSHTYPE;
170
        sh_src_reg  = `CRM;
171
        shamt       = $unsigned(i_instruction[11:7]);
172
 
173
        $sformat(o_decompile, "%s%s %s,%s,%s %s %0d", opcode, cc, dest_reg, src_reg, sh_src_reg, shtype, shamt);
174
end
175
endtask
176
 
177
task decode_mrs ( input [INS_WDT-1:0] i_instruction );
178
begin
179
        if ( i_instruction[22] ) // SPSR
180
                $sformat(o_decompile, "MRS%s %s,SPSR",`CCC, `CRD);
181
        else                     // CPSR
182
                $sformat(o_decompile, "MRS%s %s,CPSR",`CCC, `CRD);
183
end
184
endtask
185
 
186
task decode_msr ( input [INS_WDT-1:0] i_instruction );
187
begin
188
        if ( i_instruction[22] ) // SPSR
189
                $sformat(o_decompile, "MSR%s SPSR,%s",`CCC, `CRB);
190
        else
191
                $sformat(o_decompile, "MSR%s CPSR,%s", `CCC, `CRB);
192
end
193
endtask
194
 
195
task decode_msr_immed ( input [INS_WDT-1:0] i_instruction );
196
begin
197
         if ( i_instruction[22] ) // SPSR
198
                $sformat(o_decompile, "MSR%s SPSR,%dROR%d",`CCC, $unsigned(i_instruction[7:0]), $unsigned(i_instruction[11:8]));
199
        else
200
                $sformat(o_decompile, "MSR%s CPSR,%dROR%d",`CCC, $unsigned(i_instruction[7:0]), $unsigned(i_instruction[11:8]));
201
end
202
endtask
203
 
204
// LS ISS
205
task decode_ls_iss ( input [INS_WDT-1:0] i_instruction );
206
begin:blk2323
207
        reg [32*8-1:0] ls_iss_offset;
208
 
209
        $sformat(ls_iss_offset, "%s%s%d", `CRB, `CSHTYPE, $unsigned(i_instruction[11:7]));
210
 
211
        // If word load
212
        if ( i_instruction[20] )
213
                if ( !i_instruction[22] )
214
                begin
215
                case ( {i_instruction[24], i_instruction[21]} )
216
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
217
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s,%s]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
218
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s],%s" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
219
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
220
                endcase
221
                end
222
                else
223
                begin
224
                case( {i_instruction[24], i_instruction[21]}  )
225
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
226
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s,%s]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
227
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s],%s" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
228
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
229
                endcase
230
                end
231
        else
232
                if ( !i_instruction[22] )
233
                begin
234
                case ( {i_instruction[24], i_instruction[21]} )
235
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
236
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%s %s[%s,%s]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
237
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%s %s[%s],%s",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
238
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
239
                endcase
240
                end
241
                else
242
                begin
243
                case( {i_instruction[24], i_instruction[21]} )
244
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB %s[%s,%s]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
245
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s,%s]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
246
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s],%s",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
247
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB T%s[%s],%s", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
248
                endcase
249
                end
250
end
251
endtask
252
 
253
// LS immediate
254
task decode_ls ( input [INS_WDT-1:0] i_instruction );
255
begin:blk4343
256
        integer ls_iss_offset; // Forgive the naming convention...
257
 
258
        ls_iss_offset = i_instruction[11:0];
259
 
260
        // If word load
261
        if ( i_instruction[20] )
262
                if ( !i_instruction[22] )
263
                begin
264
                case ( {i_instruction[24], i_instruction[21]} )
265
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
266
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s,%0d]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
267
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%s %s[%s],%0d" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
268
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%s T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
269
                endcase
270
                end
271
                else
272
                begin
273
                case( {i_instruction[24], i_instruction[21]}  )
274
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
275
                {1'd1, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s,%0d]" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
276
                {1'd0, 1'd0}: $sformat(o_decompile,"LDR%sB %s[%s],%0d" , `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
277
                {1'd1, 1'd1}: $sformat(o_decompile,"LDR%sB T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
278
                endcase
279
                end
280
        else
281
                if ( !i_instruction[22] )
282
                begin
283
                case ( {i_instruction[24], i_instruction[21]} )
284
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
285
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%s %s[%s,%0d]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
286
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%s %s[%s],%0d",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
287
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%s T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
288
                endcase
289
                end
290
                else
291
                begin
292
                case( {i_instruction[24], i_instruction[21]} )
293
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB %s[%s,%0d]!", `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex with writeback
294
                {1'd1, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s,%0d]",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Preindex without writeback
295
                {1'd0, 1'd0}: $sformat(o_decompile,"STR%sB %s[%s],%0d",  `CCC,`CRD1,`CRN1, ls_iss_offset); // Post index
296
                {1'd1, 1'd1}: $sformat(o_decompile,"STR%sB T%s[%s],%0d", `CCC,`CRD1,`CRN1, ls_iss_offset);// Force user view of memory.
297
                endcase
298
                end
299
 
300
end
301
endtask
302
 
303
// Mult. MUL, MLA
304
task decode_mult ( input [INS_WDT-1:0] i_instruction );
305
begin
306
        if ( i_instruction[21] == 1'd0 )
307 39 Revanth
                $sformat(o_decompile, "MUL%s %s,%s,%s",`CCC,`CRN,`CRD,arch_reg_num(i_instruction[11:8]));
308 26 Revanth
        else
309 39 Revanth
                $sformat(o_decompile, "MLA%s %s,%s,%s,%s",`CCC,`CRN,`CRD,arch_reg_num(i_instruction[11:8]), arch_reg_num(i_instruction[3:0]));
310 26 Revanth
end
311
endtask
312
 
313
`ifndef XUMULL
314
 
315
        `define XUMULL 3'b100
316
        `define XUMLAL 3'b101
317
        `define XSMULL 3'b110
318
        `define XSMLAL 3'b111
319
 
320
`endif
321
 
322
// Long Mult. UMULL, UMLAL, SMULL, SMLAL
323
task decode_lmult ( input [INS_WDT-1:0] i_instruction );
324
begin
325
      case(i_instruction[23:21])
326
        `XUMULL: $sformat(o_decompile, "UMULL %s:%s=%s*%s" ,i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
327
        `XUMLAL: $sformat(o_decompile, "UMLAL %s:%s+=%s*%s",i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
328
        `XSMULL: $sformat(o_decompile, "SMULL %s:%s=%s*%s" ,i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
329
        `XSMLAL: $sformat(o_decompile, "SMLAL %s:%s+=%s*%s",i_instruction[19:16], i_instruction[15:12], i_instruction[3:0], i_instruction[11:8] );
330
      endcase
331
end
332
endtask
333
 
334
task decode_halfword_ls ( input [INS_WDT-1:0] i_instruction );
335
begin
336
      o_decompile = "***HALFWORD LD/ST***";
337
end
338
endtask
339
 
340
// Returns shift type.
341
function [4*8-1:0] get_shtype ( input [2:0] x );
342
begin
343
        case(x)
344
        0: get_shtype = "LSL";
345
        1: get_shtype = "LSR";
346
        2: get_shtype = "ASR";
347
        3: get_shtype = "ROR";
348
        4: get_shtype = "RRC";
349
        5: get_shtype = "RORI";
350
        6: get_shtype = "ROR1";
351
        7: get_shtype = "<-->";
352
        endcase
353
end
354
endfunction
355
 
356
// Returns opcode in english.
357
function [6*8-1:0] get_opcode ( input [4:0] x );
358
begin
359
        case(x)
360
        0: get_opcode = "AND"        ;  //= 0;
361
        1: get_opcode = "EOR"        ;  //= 1;
362
        2: get_opcode = "SUB"        ;  //= 2;
363
        3: get_opcode = "RSB"        ;  //= 3;
364
        4: get_opcode = "ADD"        ;  //= 4;
365
        5: get_opcode = "ADC"        ;  //= 5;
366
        6: get_opcode = "SBC"        ;  //= 6;
367
        7: get_opcode = "RSC"        ;  //= 7;
368
        8: get_opcode = "TST"        ;  //= 8;
369
        9: get_opcode = "TEQ"        ;  //= 9;
370
        10:get_opcode = "CMP"        ;  //= 10;
371
        11:get_opcode = "CMN"        ;  //= 11;
372
        12:get_opcode = "ORR"        ;  //= 12;
373
        13:get_opcode = "MOV"        ;  //= 13;
374
        14:get_opcode = "BIC"        ;  //= 14;
375
        15:get_opcode = "MVN"        ;  //= 15;
376
        16:get_opcode = "MUL"        ;  //= 16; // Multiply ( 32 x 32 = 32 ) -> Translated to MAC.
377
        17:get_opcode = "MLA"        ;  //= 17; // Multiply-Accumulate ( 32 x 32 + 32 = 32 ). 
378
        18:get_opcode = "FMOV"       ;  //= 18; 
379
        19:get_opcode = "MMOV"       ;  //= 19; 
380
        20:get_opcode = "UMLALL"     ;  //= 20; // Unsigned multiply accumulate (Write lower reg).
381
        21:get_opcode = "UMLALH"     ;  //= 21;
382
        22:get_opcode = "SMLALL"     ;  //= 22; // Signed multiply accumulate (Write lower reg).
383
        23:get_opcode = "SMLALH"     ;  //= 23;
384
        24:get_opcode = "CLZ"        ;  //= 24; // Count Leading zeros.
385
        default: get_opcode = "<-->";
386
        endcase
387
end
388
endfunction
389
 
390
// Returns arch reg number (5 bit number as input.)
391
function [4*8-1:0] arch_reg_num ( input [4:0] reg_num );
392
begin:blk434234
393
        reg [4*8-1:0] x;
394
 
395
        case(reg_num)
396
                5'd0 :  x = "R0  ";
397
                5'd1 :  x = "R1  ";
398
                5'd2 :  x = "R2  ";
399
                5'd3 :  x = "R3  ";
400
                5'd4 :  x = "R4  ";
401
                5'd5 :  x = "R5  ";
402
                5'd6 :  x = "R6  ";
403
                5'd7 :  x = "R7  ";
404
                5'd8 :  x = "R8  ";
405
                5'd9 :  x = "R9  ";
406
                5'd10 : x = "R10 ";
407
                5'd11 : x = "R11 ";
408
                5'd12 : x = "R12 ";
409
                5'd13 : x = "SP  ";
410
                5'd14 : x = "LR  ";
411
                5'd15 : x = "PC  ";
412
                5'd16 : x = "RAZ ";
413
                5'd17 : x = "CPSR";
414
                5'd18 : x = "R8x ";
415
                5'd19 : x = "R9x ";
416
                5'd20 : x = "R10x";
417
                5'd21 : x = "R11x";
418
                5'd22 : x = "R12x";
419
                5'd23 : x = "R13x";
420
                5'd24 : x = "R14x";
421
                5'd25 : x = "DMY0";
422
                5'd26 : x = "DMY1";
423
                5'd27 : x = "SPSR";
424
                5'd28 : x = "<-->";
425
                5'd29 : x = "<-->";
426
                5'd30 : x = "<-->";
427
                5'd31 : x = "<-->";
428
           endcase
429
 
430
        arch_reg_num = x;
431
end
432
endfunction
433
 
434
// Returns a text version of the condition code.
435
function [2*8-1:0] cond_code ( input [3:0] cond );
436
begin: blk49329483
437
        reg [2*8-1:0] ok;
438
 
439
        case(cond)
440
        EQ:     ok = "EQ";
441
        NE:     ok = "NE";
442
        CS:     ok = "CS";
443
        CC:     ok = "CC";
444
        MI:     ok = "MI";
445
        PL:     ok = "PL";
446
        VS:     ok = "VS";
447
        VC:     ok = "VC";
448
        HI:     ok = "HI";
449
        LS:     ok = "LS";
450
        GE:     ok = "GE";
451
        LT:     ok = "LT";
452
        GT:     ok = "GT";
453
        LE:     ok = "LE";
454
        AL:     ok = "AL";
455
        NV:     ok = "NV";
456
        endcase
457
 
458
        cond_code = ok;
459
end
460
endfunction
461
 
462
`else
463
 
464
always @*
465
        o_decompile = 0; // In synthesis mode.
466
 
467
`endif
468
 
469
endmodule // zap_decompile.v
470
 
471
`default_nettype wire

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