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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_defines.vh] - Blame information for rev 43

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`ifndef _ZAP_DEFINES_VH_
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`define _ZAP_DEFINES_VH_
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`define CPSR_MODE 4:0
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`define BASE_EXTEND             33      // Base address register for MEMOPS.
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`define BASE                    19:16   // Base address extend.
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`define SRCDEST_EXTEND          32      // Data Src/Dest extend register for MEMOPS.
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`define SRCDEST                 15:12   // Data src/dest register MEMOPS.
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`define DP_RD_EXTEND            33      // Destination source extend.
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`define DP_RD                   15:12   // Destination source.
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`define DP_RB_EXTEND            32      // Shift source extend.
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`define DP_RB                   3:0     // Shift source. ARM refers to this as rm.
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`define DP_RA                   19:16   // ALU source. ARM rn.
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`define DP_RA_EXTEND            34      // ALU source extend. ARM rn.
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`define OPCODE_EXTEND           35      // To differentiate lower and higher -> 
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                                        // 1 means higher, 0 lower.
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47 43 Revanth
// Instruction fields in CP15 instruction.
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`define opcode_2                7:5
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`define crm                     3:0
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`define crn                     19:16
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`define cp_id                   11:8
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// ----------------------------------------------------------------------------
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// Generic defines.
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`define ID 1:0  // Determine type of descriptor.
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// Virtual Address Breakup
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`define VA__TABLE_INDEX       31:20
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`define VA__L2_TABLE_INDEX    19:12
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`define VA__4K_PAGE_INDEX     11:0
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`define VA__64K_PAGE_INDEX    15:0
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`define VA__1M_SECTION_INDEX  19:0
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`define VA__TRANSLATION_BASE  31:14
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`define VA__CACHE_INDEX      4+$clog2(CACHE_SIZE/16)-1:4
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`define VA__SECTION_INDEX   20+$clog2(SECTION_TLB_ENTRIES)-1:20
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`define VA__LPAGE_INDEX     16+$clog2(LPAGE_TLB_ENTRIES)-1:16
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`define VA__SPAGE_INDEX     12+$clog2(SPAGE_TLB_ENTRIES)-1:12
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`define VA__CACHE_TAG       31:4+$clog2(CACHE_SIZE/16)
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`define VA__SPAGE_TAG       31:12+$clog2(SPAGE_TLB_ENTRIES)
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`define VA__LPAGE_TAG       31:16+$clog2(LPAGE_TLB_ENTRIES)
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`define VA__SECTION_TAG     31:20+$clog2(SECTION_TLB_ENTRIES)
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`define VA__SPAGE_AP_SEL    11:10
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`define VA__LPAGE_AP_SEL    15:14
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// L1 Section Descriptior Breakup
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`define L1_SECTION__BASE      31:20
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`define L1_SECTION__DAC_SEL   8:5
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`define L1_SECTION__AP        11:10
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`define L1_SECTION__CB        3:2
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// L1 Page Descriptor Breakup
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`define L1_PAGE__PTBR    31:10
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`define L1_PAGE__DAC_SEL 8:5
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// L2 Page Descriptor Breakup
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`define L2_SPAGE__BASE   31:12
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`define L2_SPAGE__AP     11:4
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`define L2_SPAGE__CB     3:2
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`define L2_LPAGE__BASE   31:16
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`define L2_LPAGE__AP     11:4
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`define L2_LPAGE__CB     3:2
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// Section TLB Structure - 1:0 is undefined.
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`define SECTION_TLB__BASE    31:20
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`define SECTION_TLB__DAC_SEL 8:5
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`define SECTION_TLB__AP     11:10
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`define SECTION_TLB__CB     3:2
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`define SECTION_TLB__TAG 32+(32-$clog2(SECTION_TLB_ENTRIES)-20)-1:32
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// Lpage TLB Structure - 1:0 is undefined
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`define LPAGE_TLB__BASE      31:16
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`define LPAGE_TLB__DAC_SEL   15:12 // Squeezed in blank space.
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`define LPAGE_TLB__AP        11:4
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`define LPAGE_TLB__CB        3:2
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`define LPAGE_TLB__TAG 32+(32-$clog2(LPAGE_TLB_ENTRIES)-16)-1:32
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// Spage TLB Structure - 1:0 is undefined
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`define SPAGE_TLB__BASE      31:12
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`define SPAGE_TLB__AP        11:4
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`define SPAGE_TLB__CB        3:2
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`define SPAGE_TLB__DAC_SEL   35:32
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`define SPAGE_TLB__TAG 36+(32-$clog2(SPAGE_TLB_ENTRIES)-12)-1:36
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// Cache tag width. Tag consists of the tag and the physical address. valid and dirty are stored as flops.
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`define CACHE_TAG__TAG             (31 - 4 - $clog2(CACHE_SIZE/16) + 1) -1   : 0
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`define CACHE_TAG__PA         27 + (31 - 4 - $clog2(CACHE_SIZE/16) + 1) : 31 - 4 - $clog2(CACHE_SIZE/16) + 1
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`define CACHE_TAG_WDT         27 + (31 - 4 - $clog2(CACHE_SIZE/16) + 1) + 1
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// TLB widths.
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`define SECTION_TLB_WDT       (32 + (32-$clog2(SECTION_TLB_ENTRIES)-20))
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`define LPAGE_TLB_WDT         (32 + (32-$clog2(LPAGE_TLB_ENTRIES)-16))
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`define SPAGE_TLB_WDT         (36 + (32-$clog2(SPAGE_TLB_ENTRIES)-12))
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// ----------------------------------------------------------------------------
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`endif

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