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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_localparams.vh] - Blame information for rev 43

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1 26 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
23
 
24
// Identifier for L1
25
localparam [1:0] SECTION_ID = 2'b10;
26
localparam [1:0] PAGE_ID    = 2'b01;
27
 
28
// Identifier for L2
29
localparam [1:0] SPAGE_ID   = 2'b10;
30
localparam [1:0] LPAGE_ID   = 2'b01;
31
 
32
// APSR bits.
33
// K  U (kernel user) permissions.
34
localparam APSR_NA_NA = 4'b00_00;
35
localparam APSR_RO_RO = 4'b00_01;
36
localparam APSR_RO_NA = 4'b00_10;
37
localparam APSR_RW_NA = 4'b01_??;
38
localparam APSR_RW_RO = 4'b10_??;
39
localparam APSR_RW_RW = 4'b11_??;
40
 
41
// DAC bits.
42
localparam DAC_MANAGER = 2'b11;
43
localparam DAC_CLIENT  = 2'b01;
44
 
45
// FSR related.
46
// These localparams relate to FSR values. Notice how
47
// only some FSR values make sense in this implementation.
48
 
49
//Section.
50
localparam [3:0] FSR_SECTION_DOMAIN_FAULT      = 4'b1001;
51
localparam [3:0] FSR_SECTION_TRANSLATION_FAULT = 4'b0101;
52
localparam [3:0] FSR_SECTION_PERMISSION_FAULT  = 4'b1101;
53
 
54
//Page.
55
localparam [3:0] FSR_PAGE_TRANSLATION_FAULT    = 4'b0111;
56
localparam [3:0] FSR_PAGE_DOMAIN_FAULT         = 4'b1011;
57
localparam [3:0] FSR_PAGE_PERMISSION_FAULT     = 4'b1111;
58
 
59
 
60
 
61
///////////////////////////////////////////////////////////////////////////////
62
 
63
// Standard opcodes.
64
// These map to the opcode map in the spec.
65
localparam [3:0] AND   = 0;
66
localparam [3:0] EOR   = 1;
67
localparam [3:0] SUB   = 2;
68
localparam [3:0] RSB   = 3;
69
localparam [3:0] ADD   = 4;
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localparam [3:0] ADC   = 5;
71
localparam [3:0] SBC   = 6;
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localparam [3:0] RSC   = 7;
73
localparam [3:0] TST   = 8;
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localparam [3:0] TEQ   = 9;
75
localparam [3:0] CMP   = 10;
76
localparam [3:0] CMN   = 11;
77
localparam [3:0] ORR   = 12;
78
localparam [3:0] MOV   = 13;
79
localparam [3:0] BIC   = 14;
80
localparam [3:0] MVN   = 15;
81
 
82
// Internal opcodes used to 
83
// implement some instructions.
84
localparam [4:0] MUL   = 16; // Multiply ( 32 x 32 = 32 ) -> Translated to MAC.
85
localparam [4:0] MLA   = 17; // Multiply-Accumulate ( 32 x 32 + 32 = 32 ). 
86
 
87
// Flag MOV. Will write upper 4-bits to flags if mask bit [3] is set to 1. 
88
// Also writes to target register similarly. 
89
// Mask bit comes from non-shift operand.
90
localparam [4:0] FMOV  = 18;
91
 
92
// Same as FMOV but does not touch the flags in the ALU. This is MASK MOV. 
93
// Set to 1 will update, 0 will not 
94
// (0000 -> No updates, 0001 -> [7:0] update) and so on.
95
localparam [4:0] MMOV  = 19;
96
 
97
localparam [4:0] UMLALL = 20; // Unsigned multiply accumulate (Write lower reg).
98
localparam [4:0] UMLALH = 21;
99
 
100
localparam [4:0] SMLALL = 22; // Signed multiply accumulate (Write lower reg).
101
localparam [4:0] SMLALH = 23;
102
 
103
localparam [4:0] CLZ    = 24; // Count Leading zeros.
104
 
105 43 Revanth
// Conditionals defined as per v5T spec.
106 26 Revanth
localparam EQ =  4'h0;
107
localparam NE =  4'h1;
108
localparam CS =  4'h2;
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localparam CC =  4'h3;
110
localparam MI =  4'h4;
111
localparam PL =  4'h5;
112
localparam VS =  4'h6;
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localparam VC =  4'h7;
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localparam HI =  4'h8;
115
localparam LS =  4'h9;
116
localparam GE =  4'hA;
117
localparam LT =  4'hB;
118
localparam GT =  4'hC;
119
localparam LE =  4'hD;
120
localparam AL =  4'hE;
121
localparam NV =  4'hF; // NeVer execute!
122
 
123
// CPSR flags.
124
localparam N = 31;
125
localparam Z = 30;
126
localparam C = 29;
127
localparam V = 28;
128
localparam I = 7;
129
localparam F = 6;
130
localparam T = 5;
131
 
132
// For transferring indices/immediates across stages.
133
localparam              INDEX_EN       =       1'd0;
134
localparam              IMMED_EN       =       1'd1;
135
 
136
// Processor Modes
137
localparam FIQ = 5'b10_001;
138
localparam IRQ = 5'b10_010;
139
localparam ABT = 5'b10_111;
140
localparam SVC = 5'b10_011;
141
localparam USR = 5'b10_000;
142
localparam SYS = 5'b11_111;
143
localparam UND = 5'b11_011;
144
 
145
// Instruction definitions.
146
/* ARM */
147
 
148
localparam      [31:0]  DATA_PROCESSING_IMMEDIATE                       =                                       32'b????_00_1_????_?_????_????_????????????;
149
localparam      [31:0]  DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT        =                                       32'b????_00_0_????_?_????_????_????0??1????;
150
localparam      [31:0]  DATA_PROCESSING_INSTRUCTION_SPECIFIED_SHIFT     =                                       32'b????_00_0_????_?_????_????_???????0????;
151
 
152
// BL never reaches the unit.
153
localparam      [31:0]  BRANCH_INSTRUCTION                              =                                       32'b????_101?_????_????_????_????_????_????;
154
 
155
localparam      [31:0]  MRS                                             =                                       32'b????_00010_?_001111_????_????_????_????;
156
localparam      [31:0]  MSR_IMMEDIATE                                   =                                       32'b????_00_1_10?10_????_1111_????_????_????;
157
 
158
localparam      [31:0]  MSR                                             =                                       32'b????_00_0_10?10_????_1111_????_????_????;
159
 
160
localparam      [31:0]  LS_INSTRUCTION_SPECIFIED_SHIFT                  =                                       32'b????_01_1_?????_????_????_????_????_????;
161
localparam      [31:0]  LS_IMMEDIATE                                    =                                       32'b????_01_0_?????_????_????_????_????_????;
162
 
163
localparam      [31:0]  BX_INST                                         =                                       32'b????_0001_0010_1111_1111_1111_0001_????;
164
 
165
localparam      [31:0]  MULT_INST                                       =                                       32'b????_0000_00?_?_????_????_????_1001_????;
166
 
167
// M MULT INST - UMULL, UMLAL, SMULL, SMLAL.
168
localparam      [31:0]  LMULT_INST                                      =                                       32'b????_0000_1??_?_????_????_????_1001_????;
169
 
170
// Halfword memory.
171
localparam      [31:0]  HALFWORD_LS                                     =                                       32'b????_000_?????_????_????_????_1??1_????;
172
 
173
// Software interrupt.
174
localparam      [31:0]  SOFTWARE_INTERRUPT                              =                                       32'b????_1111_????_????_????_????_????_????;
175
 
176
// Swap.
177
localparam      [31:0]  SWAP                                            =                                       32'b????_00010_?_00_????_????_00001001_????;
178
 
179
// Write to coprocessor.
180
localparam      [31:0]  MCR                                             =                                       32'b????_1110_???_0_????_????_1111_???_1_????;
181 43 Revanth
localparam      [31:0]  MCR2                                             =                                       32'b1111_1110???0_????????????_???1_????;
182 26 Revanth
 
183
// Read from coprocessor.
184
localparam      [31:0]  MRC                                             =                                       32'b????_1110_???_1_????_????_1111_???_1_????;
185 43 Revanth
localparam      [31:0]  MRC2                                             =                                       32'b1111_1110???1_????????????_???1_????;
186 26 Revanth
 
187
// LDC, STC
188
localparam      [31:0]  LDC                                             =                                       32'b????_110_????1_????_????_????_????????;
189
localparam      [31:0]  STC                                             =                                       32'b????_110_????0_????_????_????_????????;
190
 
191 43 Revanth
// LDC2, STC2
192
localparam      [31:0]  LDC2                                             =                                       32'b1111_110????1_????????????_????_????;
193
localparam      [31:0]  STC2                                             =                                       32'b1111_110????0_????????????_????_????;
194
 
195 26 Revanth
// CDP
196
localparam      [31:0]  CDP                                             =                                       32'b????_1110_????????_????????_????????;
197
 
198 37 Revanth
// CLZ
199
localparam      [31:0]  CLZ_INSTRUCTION                                 =                                       32'b????_00010110_1111_????_1111_0001_????;
200 26 Revanth
 
201 37 Revanth
// BLX(1)
202
localparam      [31:0] BLX1                                             =                                       32'b1111_101_?_????????_????????_????????;
203
 
204
// BLX(2)
205
localparam      [31:0] BLX2                                             =                                       32'b????_00010010_1111_1111_1111_0011_????;
206
 
207
/* Thumb ISA */
208
 
209 26 Revanth
//B
210
localparam      [15:0]  T_BRANCH_COND                                   =                                       16'b1101_????_????????;
211
localparam      [15:0]  T_BRANCH_NOCOND                                 =                                       16'b11100_???????????;
212
localparam      [15:0]  T_BL                                            =                                       16'b1111_?_???????????;
213
localparam      [15:0]  T_BX                                            =                                       16'b01000111_0_?_???_000;
214 37 Revanth
localparam      [15:0]  T_BLX1                                          =                                       16'b11101_???????????;
215
localparam      [15:0]  T_BLX2                                          =                                       16'b010001111_?_???_000;
216 26 Revanth
 
217
// SWI
218
localparam      [15:0]  T_SWI                                           =                                       16'b11011111_????????;
219
 
220
// Shifts.
221
localparam      [15:0]  T_SHIFT                                         =                                       16'b000_??_?????_???_???;
222
 
223
// Add sub LO.
224
localparam      [15:0]  T_ADD_SUB_LO                                    =                                       16'b00011_?_?_???_???_???;
225
 
226
// MCAS Imm.
227
localparam      [15:0]  T_MCAS_IMM                                      =                                       16'b001_??_???_????????;
228
 
229
// ALU Lo.
230
localparam      [15:0]  T_ALU_LO                                        =                                       16'b010000_????_???_???;
231
 
232
// ALU hi.
233
localparam      [15:0]  T_ALU_HI                                        =                                       16'b010001_??_?_?_???_???;
234
 
235
// *Get address.
236
localparam      [15:0]  T_GET_ADDR                                      =                                       16'b1010_?_???_????????;
237
 
238
// *Add offset to SP.
239
localparam      [15:0]  T_MOD_SP                                        =                                       16'b10110000_?_????_???;
240
 
241
// PC relative load.
242
localparam      [15:0]  T_PC_REL_LOAD                                   =                                       16'b01001_???_????????;
243
 
244
// LDR_STR_5BIT_OFF
245
localparam      [15:0] T_LDR_STR_5BIT_OFF                               =                                       16'b011_?_?_?????_???_???;
246
 
247
// LDRH_STRH_5BIT_OFF
248
localparam      [15:0] T_LDRH_STRH_5BIT_OFF                             =                                       16'b1000_?_?????_???_???;
249
 
250
// Signed LDR/STR
251
localparam      [15:0]  T_LDRH_STRH_REG                                 =                                       16'b0101_???_???_???_???;
252
 
253
// SP relative LDR/STR
254
localparam      [15:0]  T_SP_REL_LDR_STR                                =                                       16'b1001_?_???_????????;
255
 
256
// LDMIA/STMIA
257
localparam      [15:0]  T_LDMIA_STMIA                                   =                                       16'b1100_?_???_????????;
258
 
259
// PUSH POP
260
localparam      [15:0]  T_POP_PUSH                                      =                                       16'b1011_?_10_?_????????;
261
 
262
//
263
// Architectural Registers.
264
// Architectural registers are registered defined by the architecture plus
265
// a few more. Basically instructions index into architectural registers.
266
//
267
localparam [3:0] ARCH_SP   = 13;
268
localparam [3:0] ARCH_LR   = 14;
269
localparam [3:0] ARCH_PC   = 15;
270
localparam RAZ_REGISTER    = 16; // Serves as $0 does on MIPS.
271
 
272
// These always point to user registers irrespective of mode.
273
localparam ARCH_USR2_R8    = 18;
274
localparam ARCH_USR2_R9    = 19;
275
localparam ARCH_USR2_R10   = 20;
276
localparam ARCH_USR2_R11   = 21;
277
localparam ARCH_USR2_R12   = 22;
278
localparam ARCH_USR2_R13   = 23;
279
localparam ARCH_USR2_R14   = 24;
280
 
281
// Dummy architectural registers.
282
localparam ARCH_DUMMY_REG0 = 25;
283
localparam ARCH_DUMMY_REG1 = 26;
284
 
285
// CPSR and SPSR.
286
localparam ARCH_CPSR       = 17;
287
localparam ARCH_CURR_SPSR  = 27; // Alias to real SPSR.
288
 
289
// Total architectural registers.
290
localparam TOTAL_ARCH_REGS = 28;
291
 
292
//
293
// Physical registers.
294
// Physical registers can be mapped directly into the internal
295
// register file.
296
//
297
localparam  PHY_PC               =       15; // DO NOT CHANGE!
298
localparam  PHY_RAZ_REGISTER     =       16; // DO NOT CHANGE!
299
localparam  PHY_CPSR             =       17; // DO NOT CHANGE!
300
 
301
localparam  PHY_USR_R0           =       0;
302
localparam  PHY_USR_R1           =       1;
303
localparam  PHY_USR_R2           =       2;
304
localparam  PHY_USR_R3           =       3;
305
localparam  PHY_USR_R4           =       4;
306
localparam  PHY_USR_R5           =       5;
307
localparam  PHY_USR_R6           =       6;
308
localparam  PHY_USR_R7           =       7;
309
localparam  PHY_USR_R8           =       8;
310
localparam  PHY_USR_R9           =       9;
311
localparam  PHY_USR_R10          =       10;
312
localparam  PHY_USR_R11          =       11;
313
localparam  PHY_USR_R12          =       12;
314
localparam  PHY_USR_R13          =       13;
315
localparam  PHY_USR_R14          =       14;
316
 
317
localparam  PHY_FIQ_R8           =       18;
318
localparam  PHY_FIQ_R9           =       19;
319
localparam  PHY_FIQ_R10          =       20;
320
localparam  PHY_FIQ_R11          =       21;
321
localparam  PHY_FIQ_R12          =       22;
322
localparam  PHY_FIQ_R13          =       23;
323
localparam  PHY_FIQ_R14          =       24;
324
 
325
localparam  PHY_IRQ_R13          =       25;
326
localparam  PHY_IRQ_R14          =       26;
327
 
328
localparam  PHY_SVC_R13          =       27;
329
localparam  PHY_SVC_R14          =       28;
330
 
331
localparam  PHY_UND_R13          =       29;
332
localparam  PHY_UND_R14          =       30;
333
 
334
localparam  PHY_ABT_R13          =       31;
335
localparam  PHY_ABT_R14          =       32;
336
 
337
// Dummy registers for various purposes.
338
localparam  PHY_DUMMY_REG0       =       33;
339
localparam  PHY_DUMMY_REG1       =       34;
340
 
341
// SPSRs.
342
localparam  PHY_FIQ_SPSR         =       35;
343
localparam  PHY_IRQ_SPSR         =       36;
344
localparam  PHY_SVC_SPSR         =       37;
345
localparam  PHY_UND_SPSR         =       38;
346
localparam  PHY_ABT_SPSR         =       39;
347
 
348
//
349
// Count of total registers 
350
// (Can go up to 64 with no problems). Used to set register index widths of
351
// the control signals.
352
//
353
localparam  TOTAL_PHY_REGS       =       40;
354
 
355
// Shift type.
356
localparam [1:0] LSL  = 0;
357
localparam [1:0] LSR  = 1;
358
localparam [1:0] ASR  = 2;
359
localparam [1:0] ROR  = 3;
360
localparam [2:0] RRC  = 4; // Encoded as ROR #0.
361
localparam [2:0] RORI = 5;
362
localparam [2:0] ROR_1= 6; // ROR with instruction specified shift.
363
 
364
// Wishbone CTI.
365
localparam CTI_CLASSIC  = 3'b000;
366
localparam CTI_BURST    = 3'b010;
367
localparam CTI_EOB      = 3'b111;

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