OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_predecode_compress.v] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
11
// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
21
// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                         -- 
24
// --  Implements a 16-bit instruction decoder. The 16-bit instruction set is --
25
// --  not logically organized so as to save on encoding and thus the functs  --
26
// --  seem a bit complex.                                                    --
27
// --                                                                         --
28
// -----------------------------------------------------------------------------
29
 
30
`default_nettype none
31
 
32
module zap_predecode_compress (
33
        // Clock and reset.
34
        input wire              i_clk,
35
 
36
        // Input from I-cache.
37
        // Instruction and valid qualifier.
38
        input wire [31:0]       i_instruction,
39
        input wire              i_instruction_valid,
40
 
41 38 Revanth
        // Offset input.
42
        input wire [11:0]       i_offset,
43
 
44 26 Revanth
        // Interrupts. Active high level sensitive signals.
45
        input wire              i_irq,
46
        input wire              i_fiq,
47
 
48
        // Ensure compressed mode is active (T bit).
49
        input wire              i_cpsr_ff_t,
50
 
51
        //
52
        // Outputs to the ARM decoder.
53
        // 
54
 
55
        // Instruction, valid, undefined by this decoder and force 32-bit
56
        // align signals (requires memory to keep lower 2 bits as 00).
57
        output reg [34:0]       o_instruction,
58
        output reg              o_instruction_valid,
59
        output reg              o_und,
60
        output reg              o_force32_align,
61
 
62
        // Interrupt status output.
63
        output reg              o_irq,
64
        output reg              o_fiq
65
);
66
 
67
///////////////////////////////////////////////////////////////////////////////
68
 
69
`include "zap_defines.vh"
70
`include "zap_localparams.vh"
71
`include "zap_functions.vh"
72
 
73
///////////////////////////////////////////////////////////////////////////////
74
 
75 38 Revanth
reg [11:0] offset_w;  // Previous offset.
76 26 Revanth
 
77
///////////////////////////////////////////////////////////////////////////////
78
 
79 38 Revanth
always @*
80
        offset_w = i_offset;
81 26 Revanth
 
82
///////////////////////////////////////////////////////////////////////////////
83
 
84
always @*
85
begin
86
        // If you are not in compressed mode, just pass stuff on.
87
        o_instruction_valid     = i_instruction_valid;
88
        o_und                   = 0;
89
        o_instruction           = i_instruction;
90
        o_irq                   = i_irq;
91
        o_fiq                   = i_fiq;
92
        o_force32_align         = 0;
93
 
94
        if ( i_cpsr_ff_t && i_instruction_valid ) // compressed mode enable
95
        begin
96
                casez ( i_instruction[15:0] )
97 38 Revanth
                        T_BLX1                  : decode_blx1;
98
                        T_BLX2                  : decode_blx2;
99 26 Revanth
                        T_ADD_SUB_LO            : decode_add_sub_lo;
100
                        T_SWI                   : decode_swi;
101
                        T_BRANCH_COND           : decode_conditional_branch;
102
                        T_BRANCH_NOCOND         : decode_unconditional_branch;
103
                        T_BL                    : decode_bl;
104
                        T_BX                    : decode_bx;
105
                        T_SHIFT                 : decode_shift;
106
                        T_MCAS_IMM              : decode_mcas_imm;    // MOV,CMP,ADD,SUB IMM.
107
                        T_ALU_LO                : decode_alu_lo;
108
                        T_ALU_HI                : decode_alu_hi;
109
                        T_PC_REL_LOAD           : decode_pc_rel_load; // LDR Rd, [PC, {#imm8,0,0}] 
110
                        T_LDR_STR_5BIT_OFF      : decode_ldr_str_5bit_off;
111
                        T_LDRH_STRH_5BIT_OFF    : decode_ldrh_strh_5bit_off;
112
                        T_LDRH_STRH_REG         : decode_ldrh_strh_reg; // Complex. 
113
                        T_SP_REL_LDR_STR        : decode_sp_rel_ldr_str;
114
                        T_LDMIA_STMIA           : decode_ldmia_stmia;
115
                        T_POP_PUSH              : decode_pop_push;
116
                        T_GET_ADDR              : decode_get_addr;
117
                        T_MOD_SP                : decode_mod_sp;
118
                        default:
119
                        begin
120
                                `ifdef COMP_DEBUG
121
                                $display($time, "%m: Not implemented in compressed decoder!!!");
122
                                `endif
123
                                o_und = 1; // Will take UND trap.
124
                        end
125
                endcase
126
        end
127
end
128
 
129
///////////////////////////////////////////////////////////////////////////////
130
 
131
task decode_get_addr;
132
begin: dcdGetAddr
133
        reg [11:0] imm;
134
        reg [3:0] rd;
135
 
136
        rd              = i_instruction[10:8];
137
        imm[7:0]        = i_instruction[7:0];
138
        imm[11:8]       = 4'd15; // To achieve a left shift of 2 i.e., *4
139
 
140
        o_instruction = 0;
141
 
142
        // ADD Rd, PC, imm
143
        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd15, rd, imm};
144
 
145
        // ADD Rd, SP, imm
146
        if ( i_instruction[11] ) // SP
147
        begin
148
            o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd13, rd, imm};
149
        end
150
end
151
endtask
152
 
153
///////////////////////////////////////////////////////////////////////////////
154
 
155
task decode_mod_sp;
156
begin: dcdModSp
157
        reg [11:0] imm;
158
 
159
        imm[7:0]        = i_instruction[6:0];
160
        imm[11:8]       = 4'd15; // To achieve a left shift of 2 i.e., *4
161
 
162
        o_instruction = 0;
163
 
164
        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd0, 4'd13, 4'd13, imm};
165
 
166
        // SUB/ADD R13, R13, imm
167
        if ( i_instruction[7] != 0 ) // SUB
168
        begin
169
         o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd0, 4'd13, 4'd13, imm};
170
        end
171
end
172
endtask
173
 
174
///////////////////////////////////////////////////////////////////////////////
175
 
176
task decode_pop_push;
177
begin: decodePopPush
178
        //
179
        // Uses an FD stack. Thus it is DA type i.e., post index down by 4. 
180
        // Writeback is implicit so make W = 0.
181
        //
182
 
183
        reg [3:0] base;
184
        reg [15:0] reglist;
185
 
186
        o_instruction = 0;
187
        base = 13;
188
 
189
        reglist = i_instruction[7:0];
190
 
191
        if ( i_instruction[8] == 1 && i_instruction[11] ) // Pop.
192
        begin
193
                reglist[15] = 1'd1;
194
        end
195
        else if ( i_instruction[8] == 1 && !i_instruction[11] ) // Push.
196
        begin
197
                reglist[14] = 1'd1;
198
        end
199
 
200
        o_instruction = {AL, 3'b100, 1'd0, 1'd0, 1'd0, 1'd1, i_instruction[11],
201
                                                        base, reglist};
202
end
203
endtask
204
 
205
///////////////////////////////////////////////////////////////////////////////
206
 
207
task decode_ldmia_stmia;
208
begin: dcdLdmiaStmia
209
        // Implicit IA type i.e., post index up by 4. Make WB = 1.
210
 
211
        reg [3:0] base;
212
        reg [15:0] reglist;
213
 
214
        base = i_instruction[10:8];
215
        reglist = i_instruction[7:0];
216
 
217
        o_instruction = 0;
218
        o_instruction = {AL, 3'b100, 1'd0, 1'd1, 1'd0, 1'd1, i_instruction[11],
219
                                base, reglist};
220
end
221
endtask
222
 
223
///////////////////////////////////////////////////////////////////////////////
224
 
225
task decode_sp_rel_ldr_str;
226
begin: dcdLdrRelStr
227
        reg [3:0] srcdest;
228
        reg [3:0] base;
229
        reg [11:0] imm;
230
 
231
        srcdest = i_instruction[10:8];
232
        base    = ARCH_SP;
233
        imm    = i_instruction[7:0] << 2;
234
 
235
        o_instruction = 0;
236
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, 1'd0, 1'd0, i_instruction[11],
237
                        base, srcdest, imm};
238
end
239
endtask
240
 
241
///////////////////////////////////////////////////////////////////////////////
242
 
243
task decode_ldrh_strh_reg;
244
begin: dcdLdrhStrh
245
        // Use different load store format, instead of 3'b010, use 3'b011
246
 
247
        reg X,S,H;
248
        reg [3:0] srcdest, base;
249
        reg [11:0] offset;
250
 
251
        X = i_instruction[9];
252
        S = i_instruction[10];
253
        H = i_instruction[11];
254
        srcdest = i_instruction[2:0];
255
        base    = i_instruction[5:3];
256
        offset = i_instruction[8:6];
257
 
258
        o_instruction = 0;
259
 
260
        if ( X == 0 )
261
        begin
262
          case({H,S})
263
          0: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd0, 1'd0, 1'd0, base, srcdest, offset};// STR
264
          1: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd1, 1'd0, 1'd0, base, srcdest, offset};// STRB
265
          2: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, offset};// LDR
266
          3: o_instruction = {AL, 3'b011, 1'd1, 1'd0, 1'd1, 1'd0, 1'd1, base, srcdest, offset};// LDRB
267
          endcase
268
        end
269
        else
270
        begin
271
         case({S,H})
272
         0: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd0, base, srcdest, 4'd0, 2'b01,offset[3:0]};// STRH
273
         1: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b01,offset[3:0]};// LDRH
274
         2: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b10,offset[3:0]};// LDSB
275
         3: o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd0, 1'd0, 1'd1, base, srcdest, 4'd0, 2'b11,offset[3:0]};// LDSH
276
         endcase
277
        end
278
end
279
endtask
280
 
281
///////////////////////////////////////////////////////////////////////////////
282
 
283
task decode_ldrh_strh_5bit_off;
284
begin: dcdLdrhStrh5BitOff
285
 
286
        reg [3:0] rn;
287
        reg [3:0] rd;
288
        reg [7:0] imm;
289
 
290
        o_instruction = 0;
291
 
292
        rn = i_instruction[5:3];
293
        rd = i_instruction[2:0];
294
        imm[7:0] = i_instruction[10:6] << 1;
295
 
296
        // Unsigned halfword transfer
297
        o_instruction = {AL, 3'b000, 1'd1, 1'd0, 1'd1, 1'd0, i_instruction[11],
298
                                        rn, rd, imm[7:4], 2'b01,imm[3:0]};
299
end
300
endtask
301
 
302
///////////////////////////////////////////////////////////////////////////////
303
 
304
task decode_ldr_str_5bit_off;
305
begin: dcLdrStr5BitOff
306
        reg [3:0] rn;
307
        reg [3:0] rd;
308
        reg [11:0] imm;
309
 
310
        o_instruction = 0;
311
 
312
        rn = i_instruction[5:3];
313
        rd = i_instruction[2:0];
314
 
315
        if ( i_instruction[12] == 1'd0 )
316
                imm[11:0] = i_instruction[10:6] << 2;
317
        else
318
                imm[11:0] = i_instruction[10:6];
319
 
320
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, i_instruction[12], 1'd0,
321
                                               i_instruction[11], rn, rd, imm};
322
end
323
endtask
324
 
325
///////////////////////////////////////////////////////////////////////////////
326
 
327
task decode_pc_rel_load;
328
begin: dcPcRelLoad
329
        reg [3:0] rd;
330
        reg [11:0] imm;
331
 
332
        rd = i_instruction[10:8];
333
        imm = i_instruction[7:0] << 2;
334
 
335
        o_force32_align = 1'd1;
336
        o_instruction = 0;
337
        o_instruction = {AL, 3'b010, 1'd1, 1'd0, 1'd0, 1'd0,
338
                                        1'd1, 4'b1111, rd, imm};
339
end
340
endtask
341
 
342
///////////////////////////////////////////////////////////////////////////////
343
 
344
task decode_alu_hi;
345
begin:dcAluHi
346
        // Performs operations on HI registers (atleast some of them). 
347
        reg [1:0] op;
348
        reg [3:0] rd;
349
        reg [3:0] rs;
350
 
351
        o_instruction = 0;
352
 
353
        op = i_instruction[9:8];
354
        rd = {i_instruction[7], i_instruction[2:0]};
355
        rs = {i_instruction[6], i_instruction[5:3]};
356
 
357
        case(op)
358
        0: o_instruction[31:0] = {AL, 2'b00, 1'b0, ADD, 1'b0, rd, rd, 8'd0, rs}; // ADD Rd, Rd, Rs 
359
        1: o_instruction[31:0] = {AL, 2'b00, 1'b0, CMP, 1'b1, rd, rd, 8'd0, rs}; // CMP Rd, Rs
360
        2: o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'b0, rd, rd, 8'd0, rs}; // MOV Rd, Rs
361
        3:
362
        begin
363
                $display($time, "%m: This should never happen, should be taken by BX...!");
364
                $finish;
365
        end
366
        endcase
367
end
368
endtask
369
 
370
///////////////////////////////////////////////////////////////////////////////
371
 
372
task decode_alu_lo;
373
begin: tskDecAluLo
374
        reg [3:0] op;
375
        reg [3:0] rs, rd;
376
        reg [3:0] rn;
377
 
378
        op = i_instruction[9:6];
379
        rs = i_instruction[5:3];
380
        rd = i_instruction[2:0];
381
 
382
        o_instruction = 0;
383
 
384
        case(op)
385
        0:      o_instruction[31:0] = {AL, 2'b00, 1'b0, AND, 1'd1, rd, rd, 8'd0, rs};                   // ANDS Rd, Rd, Rs
386
        1:      o_instruction[31:0] = {AL, 2'b00, 1'b0, EOR, 1'd1, rd, rd, 8'd0, rs};                   // EORS Rd, Rd, Rs
387
        2:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, LSL, 1'd1, rd};    // MOVS Rd, Rd, LSL Rs
388
        3:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, LSR, 1'd1, rd};    // MOVS Rd, Rd, LSR Rs
389
        4:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, ASR, 1'd1, rd};    // MOVS Rd, Rd, ASR Rs
390
        5:      o_instruction[31:0] = {AL, 2'b00, 1'b0, ADC, 1'd1, rd, rd, 8'd0, rs};                   // ADCS Rd, Rd, Rs
391
        6:      o_instruction[31:0] = {AL, 2'b00, 1'b0, SBC, 1'd1, rd, rd, 8'd0, rs};                   // SBCS Rd, Rs, Rs        
392
        7:      o_instruction[31:0] = {AL, 2'b00, 1'b0, MOV, 1'd1, rd, rd, rs, 1'd0, ROR, 1'd1, rd};    // MOVS Rd, Rd, ROR Rs.
393
        8:      o_instruction[31:0] = {AL, 2'b00, 1'b0, TST, 1'd1, rd, rd, 8'd0, rs};                   // TST Rd, Rs
394
        9:      o_instruction[31:0] = {AL, 2'b00, 1'b1, RSB, 1'd1, rs, rd, 12'd0};                      // Rd = 0 - Rs
395
        10:     o_instruction[31:0] = {AL, 2'b00, 1'b1, CMP, 1'd1, rd, rd, 8'd0, rs};                   // CMP Rd, Rs
396
        11:     o_instruction[31:0] = {AL, 2'b00, 1'b1, CMN, 1'd1, rd, rd, 8'd0, rs};                   // CMN Rd, Rs
397
        12:     o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd1, rd, rd, 8'd0, rs};                   // ORRS Rd, Rd, rs 
398
        13:     o_instruction[31:0] = {AL, 4'b0000, 3'b000, 1'd1, rd, 4'd0, rd, 4'b1001, rs};           // MULS Rd, Rs, Rd
399
        14:     o_instruction[31:0] = {AL, 2'b00, 1'b1, BIC, 1'd1, rd, rd, 8'd0, rs};                   // BICS rd, rd, rs 
400
        15:     o_instruction[31:0] = {AL, 2'b00, 1'b1, MVN, 1'd1, rd, rd, 8'd0, rs};                   // MVNS rd, rd, rs
401
        endcase
402
end
403
endtask
404
 
405
///////////////////////////////////////////////////////////////////////////////
406
 
407
task decode_mcas_imm;
408
begin: tskDecodeMcasImm
409
        reg [1:0]  op;
410
        reg [3:0]  rd;
411
        reg [11:0] imm;
412
 
413
        o_instruction = 0;
414
 
415
        op = i_instruction[12:11];
416
        rd = i_instruction[10:8];
417
        imm =i_instruction[7:0];
418
 
419
        case (op)
420
                0:
421
                begin
422
                        // MOV Rd, Offset8
423
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, MOV, 1'd1, rd, rd, imm};
424
                end
425
                1:
426
                begin
427
                        // CMP Rd, Offset8
428
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, CMP, 1'd1, rd, rd, imm};
429
                end
430
                2:
431
                begin
432
                        // ADDS Rd, Rd, Offset8
433
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd1, rd, rd, imm};
434
                end
435
                3:
436
                begin
437
                        // SUBS Rd, Rd, Offset8
438
                        o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd1, rd, rd, imm};
439
                end
440
        endcase
441
end
442
endtask
443
 
444
///////////////////////////////////////////////////////////////////////////////
445
 
446
task decode_add_sub_lo;
447
begin: tskDecodeAddSubLo
448
        reg [3:0] rn, rd, rs;
449
        reg [11:0] imm;
450
 
451
        o_instruction = 0;
452
 
453
        rn = i_instruction[8:6];
454
        rd = i_instruction[2:0];
455
        rs = i_instruction[5:3];
456
        imm = rn;
457
 
458
        case({i_instruction[9], i_instruction[10]})
459
        0:
460
        begin
461
                // Add Rd, Rs, Rn - Instr spec shift.
462
                o_instruction[31:0] = {AL, 2'b00, 1'b0, ADD, 1'd1, rs, rd, 8'd0, rn};
463
        end
464
        1:
465
        begin
466
                // Adds Rd, Rs, #Offset3 - Immediate.
467
                o_instruction[31:0] = {AL, 2'b00, 1'b1, ADD, 1'd1, rn, rd, imm};
468
        end
469
        2:
470
        begin
471
                // SUBS Rd, Rs, Rn - Instr spec shift.
472
                o_instruction[31:0] = {AL, 2'b00, 1'b0, SUB, 1'd1, rs, rd, 8'd0, rn};
473
        end
474
        3:
475
        begin
476
                // SUBS Rd, Rs, #Offset3 - Immediate.
477
                o_instruction[31:0] = {AL, 2'b00, 1'b1, SUB, 1'd1, rn, rd, imm};
478
        end
479
        endcase
480
end
481
endtask
482
 
483
///////////////////////////////////////////////////////////////////////////////
484
 
485
task decode_conditional_branch;
486
begin
487
        // An MSB of 1 indicates a left shift of 1.
488
        o_instruction           = {1'd1, 2'b0, i_instruction[11:8], 3'b101, 1'b0, 24'd0};
489
        o_instruction[23:0]     = $signed(i_instruction[7:0]);
490
end
491
endtask
492
 
493
///////////////////////////////////////////////////////////////////////////////
494
 
495
task decode_unconditional_branch;
496
begin
497
        // An MSB of 1 indicates a left shift of 1.
498
        o_instruction           = {1'd1, 2'b0, AL, 3'b101, 1'b0, 24'd0};
499
        o_instruction[23:0]     = $signed(i_instruction[10:0]);
500
end
501
endtask
502
 
503
///////////////////////////////////////////////////////////////////////////////
504
 
505 38 Revanth
task decode_blx1;
506
begin
507
        o_instruction = 0; // Default value.
508
 
509
        // Generate a BLX1.
510
        o_instruction[31:25] =  7'b1111_101;    // BLX1 identifier.   
511
        o_instruction[24]    =  1'd0;           // H - bit.
512
        o_instruction[23:0]  =  ($signed(offset_w) << 12) | (i_instruction[10:0] << 1);  // Corrected.
513
        o_irq                = 1'd0;
514
        o_fiq                = 1'd0;
515
end
516
endtask
517
 
518
////////////////////////////////////////////////////////////////////////////////
519
 
520
task decode_blx2;
521
begin
522
        o_instruction = {4'b1110,4'b0001,4'b0010,4'b1111,4'b1111,4'b1111,4'b0011, i_instruction[6:3]};
523
        o_irq         = 1'd0;
524
        o_fiq         = 1'd0;
525
end
526
endtask
527
 
528
///////////////////////////////////////////////////////////////////////////////
529
 
530 26 Revanth
task decode_bl;
531
begin
532
        case ( i_instruction[11] )
533
                1'd0:
534
                begin
535 38 Revanth
                        // Send out a dummy instruction. Preserve lower
536
                        // 12-bits though to serve as offset. Set condition
537
                        // code to NV.
538
                        o_instruction        = i_instruction[11:0];
539
                        o_instruction[31:28] = 4'b1111;
540
                        o_irq                = 1'd0;
541
                        o_fiq                = 1'd0;
542 26 Revanth
                end
543
                1'd1:
544
                begin
545
                        // Generate a full jump.
546
                        o_instruction = {1'd1, 2'b0, AL, 3'b101, 1'b1, 24'd0};
547 38 Revanth
                        o_instruction[23:0] = ($signed(offset_w) << 12) | (i_instruction[10:0] << 1);  // Corrected.
548 26 Revanth
                        o_irq           = 1'd0;
549
                        o_fiq           = 1'd0;
550
                end
551
        endcase
552
end
553
endtask
554
 
555
///////////////////////////////////////////////////////////////////////////////
556
 
557
task decode_bx;
558
begin
559
        // Generate a BX Rm.
560
        o_instruction = 32'b0000_0001_0010_1111_1111_1111_0001_0000;
561
        o_instruction[31:28] = AL;
562
        o_instruction[3:0]   = i_instruction[6:3];
563
end
564
endtask
565
 
566
///////////////////////////////////////////////////////////////////////////////
567
 
568
task decode_swi;
569
begin
570
        // Generate a SWI.
571
        o_instruction = 32'b0000_1111_0000_0000_0000_0000_0000_0000;
572
        o_instruction[31:28] = AL;
573
        o_instruction[7:0]   = i_instruction[7:0];
574
end
575
endtask
576
 
577
///////////////////////////////////////////////////////////////////////////////
578
 
579
task decode_shift;
580
begin
581
        // Compressed shift instructions. Decompress to ARM with instruction specified shift.
582
        o_instruction           = 32'd0;                // Extension -> 0.
583
        o_instruction[31:28]    = AL;                   // Always execute.
584
        o_instruction[27:26]    = 2'b00;                // Data processing.
585
        o_instruction[25]       = 1'd0;                 // Immediate is ZERO.
586
        o_instruction[24:21]    = MOV;                  // Operation is MOV.
587
        o_instruction[20]       = 1'd1;                 // Do update flags.
588
        o_instruction[19:16]    = 4'd0;                 // ALU source. Doesn't matter.
589
        o_instruction[15:12]    = i_instruction[2:0] ;  // Destination. 
590
        o_instruction[11:7]     = i_instruction[10:6];  // Shamt.
591
        o_instruction[6:5]      = i_instruction[12:11]; // Shtype.
592
        o_instruction[3:0]      = i_instruction[5:3];   // Shifter source.
593
end
594
endtask
595
 
596
///////////////////////////////////////////////////////////////////////////////
597
 
598
endmodule
599
`default_nettype wire

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.