OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_wb_merger.v] - Blame information for rev 51

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 26 Revanth
// -----------------------------------------------------------------------------
2
// --                                                                         --
3
// --                   (C) 2016-2018 Revanth Kamaraj.                        --
4
// --                                                                         -- 
5
// -- --------------------------------------------------------------------------
6
// --                                                                         --
7
// -- This program is free software; you can redistribute it and/or           --
8
// -- modify it under the terms of the GNU General Public License             --
9
// -- as published by the Free Software Foundation; either version 2          --
10
// -- of the License, or (at your option) any later version.                  --
11
// --                                                                         --
12
// -- This program is distributed in the hope that it will be useful,         --
13
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
14
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
15
// -- GNU General Public License for more details.                            --
16
// --                                                                         --
17
// -- You should have received a copy of the GNU General Public License       --
18
// -- along with this program; if not, write to the Free Software             --
19
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
20
// -- 02110-1301, USA.                                                        --
21
// --                                                                         --
22
// -----------------------------------------------------------------------------
23
// --                                                                         -- 
24
// -- Merges two Wishbone busses onto a single bus. One side can from the     --
25
// -- instruction cache while the other from data cache. This module can      --
26
// -- be used to connect any 2 generic Wishbone devices.                      --
27
// --                                                                         --
28
// -----------------------------------------------------------------------------
29
 
30
`default_nettype none
31
 
32
module zap_wb_merger (
33
 
34 51 Revanth
// Clock and reset       
35 26 Revanth
input wire i_clk,
36
input wire i_reset,
37
 
38
// Wishbone bus 1
39
input wire i_c_wb_stb,
40
input wire i_c_wb_cyc,
41
input wire i_c_wb_wen,
42
input wire [3:0] i_c_wb_sel,
43
input wire [31:0] i_c_wb_dat,
44
input wire [31:0] i_c_wb_adr,
45
input wire [2:0] i_c_wb_cti,
46
output reg o_c_wb_ack,
47
 
48
// Wishbone bus 2
49
input wire i_d_wb_stb,
50
input wire i_d_wb_cyc,
51
input wire i_d_wb_wen,
52
input wire [3:0] i_d_wb_sel,
53
input wire [31:0] i_d_wb_dat,
54
input wire [31:0] i_d_wb_adr,
55
input wire [2:0] i_d_wb_cti,
56
output reg o_d_wb_ack,
57
 
58
// Common bus
59
output reg o_wb_cyc,
60
output reg o_wb_stb,
61
output reg o_wb_wen,
62
output reg [3:0] o_wb_sel,
63
output reg [31:0] o_wb_dat,
64
output reg [31:0] o_wb_adr,
65
output reg [2:0] o_wb_cti,
66
input wire i_wb_ack
67
 
68
);
69
 
70
`include "zap_defines.vh"
71
`include "zap_localparams.vh"
72
 
73
localparam CODE = 1'd0;
74
localparam DATA = 1'd1;
75
 
76
reg sel_ff, sel_nxt;
77
 
78
always @ (posedge i_clk)
79
begin
80
        if ( i_reset )
81
                sel_ff <= CODE;
82
        else
83
                sel_ff <= sel_nxt;
84
end
85
 
86
always @*
87
begin
88
        if ( sel_ff == CODE )
89
        begin
90
                o_c_wb_ack = i_wb_ack;
91
                o_d_wb_ack = 1'd0;
92
        end
93
        else
94
        begin
95
                o_d_wb_ack = i_wb_ack;
96
                o_c_wb_ack = 1'd0;
97
        end
98
end
99
 
100
always @*
101
begin
102
        case(sel_ff)
103
        CODE:
104
        begin
105
                if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_d_wb_stb )
106
                        sel_nxt = DATA;
107
                else if ( !i_c_wb_stb && i_d_wb_stb )
108
                        sel_nxt = DATA;
109
                else
110
                        sel_nxt = sel_ff;
111
        end
112
 
113
        DATA:
114
        begin
115
                if ( i_wb_ack && (o_wb_cti == CTI_CLASSIC || o_wb_cti == CTI_EOB) && i_c_wb_stb )
116
                        sel_nxt = CODE;
117
                else if ( i_c_wb_stb && !i_d_wb_stb )
118
                        sel_nxt = CODE;
119
                else
120
                        sel_nxt = sel_ff;
121
        end
122
        endcase
123
end
124
 
125
always @ (posedge i_clk)
126
begin
127
        if ( i_reset )
128
        begin
129
                o_wb_cyc <= 0;
130
                o_wb_stb <= 0;
131
                o_wb_wen <= 0;
132
                o_wb_sel <= 0;
133
                o_wb_dat <= 0;
134
                o_wb_adr <= 0;
135
                o_wb_cti <= 0;
136
        end
137
        else if ( sel_nxt == CODE )
138
        begin
139
                o_wb_cyc <= i_c_wb_cyc;
140
                o_wb_stb <= i_c_wb_stb;
141
                o_wb_wen <= i_c_wb_wen;
142
                o_wb_sel <= i_c_wb_sel;
143
                o_wb_dat <= i_c_wb_dat;
144
                o_wb_adr <= i_c_wb_adr;
145
                o_wb_cti <= i_c_wb_cti;
146
        end
147
        else
148
        begin
149
                o_wb_cyc <= i_d_wb_cyc;
150
                o_wb_stb <= i_d_wb_stb;
151
                o_wb_wen <= i_d_wb_wen;
152
                o_wb_sel <= i_d_wb_sel;
153
                o_wb_dat <= i_d_wb_dat;
154
                o_wb_adr <= i_d_wb_adr;
155
                o_wb_cti <= i_d_wb_cti;
156
        end
157
end
158
 
159
endmodule
160 51 Revanth
 
161 26 Revanth
`default_nettype wire
162 51 Revanth
 
163
// ----------------------------------------------------------------------------
164
// EOF
165
// ----------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.