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[/] [zap/] [trunk/] [src/] [scripts/] [Config.cfg_template] - Blame information for rev 43

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1 41 Revanth
#// -----------------------------------------------------------------------------
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#// --                                                                         --
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#// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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#// --                                                                         --
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#// -- --------------------------------------------------------------------------
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#// --                                                                         --
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#// -- This program is free software; you can redistribute it and/or           --
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#// -- modify it under the terms of the GNU General Public License             --
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#// -- as published by the Free Software Foundation; either version 2          --
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#// -- of the License, or (at your option) any later version.                  --
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#// --                                                                         --
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#// -- This program is distributed in the hope that it will be useful,         --
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#// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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#// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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#// -- GNU General Public License for more details.                            --
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#// --                                                                         --
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#// -- You should have received a copy of the GNU General Public License       --
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#// -- along with this program; if not, write to the Free Software             --
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#// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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#// -- 02110-1301, USA.                                                        --
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#// --                                                                         --
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#// -----------------------------------------------------------------------------
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25 26 Revanth
# Basic template for use in other TCs.
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%Config = (
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        # CPU configuration.
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        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
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        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
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        CODE_SECTION_TLB_ENTRIES    => 8,       # Instruction section TLB entries.
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        CODE_SPAGE_TLB_ENTRIES      => 32,      # Instruction small page TLB entries.
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        CODE_LPAGE_TLB_ENTRIES      => 16,      # Instruction large page TLB entries.
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        DATA_SECTION_TLB_ENTRIES    => 8,       # Data section TLB entries.
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        DATA_SPAGE_TLB_ENTRIES      => 32,      # Data small page TLB entries.
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        DATA_LPAGE_TLB_ENTRIES      => 16,      # Data large page TLB entries.
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        BP_DEPTH                    => 1024,    # Branch predictor depth.
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        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
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        STORE_BUFFER_DEPTH          => 8,       # Store buffer depth.
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        SYNTHESIS                   => 1,       # Make this to 1 to simulate compile from a synthesis perspective.
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        # Testbench configuration.
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        WAVES                       => 0,       # 1 Enables wave logging.
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        UART0_TX_TERMINAL           => 1,       # 1 Enables UART TX terminal 0. 0 disables it.
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        UART1_TX_TERMINAL           => 1,       # 1 Enables UART TX terminal 1. 0 disables it.
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        UART0_RX_TERMINAL           => 1,       # RX terminal 0. Characters typed go to UART RX.
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        UART1_RX_TERMINAL           => 1,       # RX terminal 1. Characters typed go to UART RX.
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        EXT_RAM_SIZE                => 32768,   # External RAM size.
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        SEED                        => -1,      # Seed. Use -1 to use random seed.
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        DUMP_START                  => 2000,    # Starting memory address from which to dump.
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        DUMP_SIZE                   => 200,     # Length of dump in bytes.
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        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
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        REG_CHECK                   => {"r1" => "32'h4",
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                                        "r2" => "32'd3"},      # Make this an anonymous has with entries like "r10" => "32'h0" etc.
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        FINAL_CHECK                 => {"32'h100" => "32'd4",
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                                        "32'h66" => "32'h4"}       # Make this an anonymous hash with entries like verilog_address => verilog_value etc.
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);
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