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[/] [zap/] [trunk/] [src/] [testbench/] [ram.v] - Blame information for rev 43

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1 43 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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module ram #(parameter SIZE_IN_BYTES = 4096)  (
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input wire                   i_clk,
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input wire                   i_wb_cyc,
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input wire                   i_wb_stb,
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input wire [31:0]            i_wb_adr,
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input wire [31:0]            i_wb_dat,
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input wire  [3:0]            i_wb_sel,
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input wire                   i_wb_we,
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output reg [31:0]       o_wb_dat = 32'd0,
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output reg              o_wb_ack = 1'd0
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);
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`include "zap_defines.vh"
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`include "zap_localparams.vh"
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`include "zap_functions.vh"
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integer seed = `SEED;
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reg [31:0] ram [SIZE_IN_BYTES/4 -1:0];
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// Initialize the RAM with the generated image.
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initial
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begin:blk1
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        integer i;
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        integer j;
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        reg [7:0] mem [SIZE_IN_BYTES-1:0];
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        j = 0;
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        for ( i=0;i<SIZE_IN_BYTES;i=i+1)
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                mem[i] = 8'd0;
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        `include `MEMORY_IMAGE
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        for (i=0;i<SIZE_IN_BYTES/4;i=i+1)
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        begin
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                ram[i] = {mem[j+3], mem[j+2], mem[j+1], mem[j]};
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                j = j + 4;
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        end
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end
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// Wishbone RAM.
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        // Models a variable delay RAM.
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        always @ ( negedge i_clk )
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        begin:blk
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                reg stall;
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                stall = $random(seed);
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                if ( !i_wb_we && i_wb_cyc && i_wb_stb && !stall )
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                begin
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                        o_wb_ack         <= 1'd1;
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                        o_wb_dat         <= ram [ i_wb_adr >> 2 ];
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                end
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                else if ( i_wb_we && i_wb_cyc && i_wb_stb && !stall )
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                begin
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                        o_wb_ack         <= 1'd1;
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                        o_wb_dat         <= 'dx;
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                        if ( i_wb_sel[0] ) ram [ i_wb_adr >> 2 ][7:0]   <= i_wb_dat[7:0];
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                        if ( i_wb_sel[1] ) ram [ i_wb_adr >> 2 ][15:8]  <= i_wb_dat[15:8];
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                        if ( i_wb_sel[2] ) ram [ i_wb_adr >> 2 ][23:16] <= i_wb_dat[23:16];
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                        if ( i_wb_sel[3] ) ram [ i_wb_adr >> 2 ][31:24] <= i_wb_dat[31:24];
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                end
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                else
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                begin
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                        o_wb_ack    <= 1'd0;
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                        o_wb_dat    <= 'dx;
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                end
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        end
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endmodule // ram
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`default_nettype wire

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