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[/] [zap/] [trunk/] [src/] [testbench/] [uart_tx_dumper.v] - Blame information for rev 43

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1 43 Revanth
// -----------------------------------------------------------------------------
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// --                                                                         --
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// --                   (C) 2016-2018 Revanth Kamaraj.                        --
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// --                                                                         -- 
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// -- --------------------------------------------------------------------------
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// --                                                                         --
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// -- This program is free software; you can redistribute it and/or           --
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// -- modify it under the terms of the GNU General Public License             --
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// -- as published by the Free Software Foundation; either version 2          --
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// -- of the License, or (at your option) any later version.                  --
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// --                                                                         --
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// -- This program is distributed in the hope that it will be useful,         --
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// -- but WITHOUT ANY WARRANTY; without even the implied warranty of          --
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// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the           --
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// -- GNU General Public License for more details.                            --
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// --                                                                         --
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// -- You should have received a copy of the GNU General Public License       --
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// -- along with this program; if not, write to the Free Software             --
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// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
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// -- 02110-1301, USA.                                                        --
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// --                                                                         --
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// -----------------------------------------------------------------------------
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`default_nettype none
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//
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// P = 0 UART0 P = 1 UART1
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//
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// Assumes no parity, 8 bits per character and
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// 1 stop bit. 
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// Writes UART output to a file.
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//
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// If UART0, output file is `UART0_FILE_PATH
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// If UART1, output file is `UART1_FILE_PATH
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//
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module uart_tx_dumper #(parameter [0:0] P = 0 ) ( input wire i_clk, input wire i_line );
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localparam UART_WAIT_FOR_START = 0;
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localparam UART_RX             = 1;
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localparam UART_STOP_BIT       = 2;
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integer                 uart_state   = UART_WAIT_FOR_START;
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reg                     uart_sof     = 1'd0;
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reg                     uart_eof     = 1'd0;
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integer                 uart_ctr     = 0;
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integer                 uart_bit_ctr = 1'dx;
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reg [7:0]               uart_sr      = 0;
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reg [7:0]               UART_SR      = 0;
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reg                     UART_SR_DAV  = 0;
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wire                    uart;
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integer    signed       fh;
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assign uart = i_line;
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always @ ( posedge i_clk )
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begin
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        UART_SR_DAV = 1'd0;
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        uart_sof = 1'd0;
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        uart_eof = 1'd0;
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        case ( uart_state )
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                UART_WAIT_FOR_START:
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                begin
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                        if ( !uart )
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                        begin
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                                uart_ctr = uart_ctr + 1;
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                                uart_sof = 1'd1;
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                        end
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                        if ( !uart && uart_ctr == 16  )
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                        begin
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                                uart_sof     = 1'd0;
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                                uart_state   = UART_RX;
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                                uart_ctr     = 0;
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                                uart_bit_ctr = 0;
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                        end
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                end
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                UART_RX:
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                begin
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                        uart_ctr++;
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                        if ( uart_ctr == 2 )
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                                uart_sr = uart_sr >> 1 | uart << 7;
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                        if ( uart_ctr == 16 )
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                        begin
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                                uart_bit_ctr++;
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                                uart_ctr = 0;
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                                if ( uart_bit_ctr == 8 )
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                                begin
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                                        uart_state  = UART_STOP_BIT;
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                                        UART_SR     = uart_sr;
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                                        UART_SR_DAV = 1'd1;
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                                        uart_ctr    = 0;
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                                        uart_bit_ctr = 0;
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                                end
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                        end
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                end
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                UART_STOP_BIT:
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                begin
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                        uart_ctr++;
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                        if ( uart && uart_ctr == 16 ) // Stop bit.
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                        begin
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                                uart_state      = UART_WAIT_FOR_START;
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                                uart_bit_ctr    = 0;
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                                uart_ctr        = 0;
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                        end
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                end
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        endcase
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end
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initial
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begin
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        if ( P == 0 )
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                fh = $fopen(`UART0_FILE_PATH_TX, "w");
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        else
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                fh = $fopen(`UART1_FILE_PATH_TX, "w");
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        if ( fh == -1 )
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        begin
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                $display($time, " - %m :: Error: Failed to open UART output log.");
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                $finish;
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        end
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end
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always @ (negedge i_clk)
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begin
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        if ( UART_SR_DAV )
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        begin
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                $display("UART Wrote %c", UART_SR);
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                $fwrite(fh, "%c", UART_SR);
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                $fflush(fh);
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        end
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end
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endmodule // uart_tx_dumper
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`default_nettype wire

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