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[/] [zap/] [trunk/] [src/] [ts/] [factorial/] [factorial.s] - Blame information for rev 43

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Line No. Rev Author Line
1 29 Revanth
//
2 26 Revanth
// Startup file for factorial.
3 29 Revanth
//
4 26 Revanth
 
5
.global _Reset
6
 
7
// Set up an interrupt vector table.
8
_Reset   : b there
9
_Undef   : b UNDEF
10
_Swi     : b SWI
11
_Pabt    : b __pabt
12
_Dabt    : b __dabt
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reserved : b _Reset
14
irq      : b IRQ
15
fiq      : b FIQ
16
 
17
UNDEF:
18 29 Revanth
 
19 26 Revanth
// Undefined vector.
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// LR Points to next instruction.
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stmfa sp!, {r0-r12, r14}
22 29 Revanth
 
23 26 Revanth
// Corrupt registers.
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mov r0, #1
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mov r1, #2
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mov r2, #3
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mov r3, #4
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mov r4, #5
29
mov r5, #6
30
mov r6, #7
31
mov r7, #8
32
mov r8, #9
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mov r9, #10
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mov r10, #12
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mov r11, #13
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mov r12, #14
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mov r14, #15
38 29 Revanth
 
39 26 Revanth
// Restore them.
40
ldmfa sp!, {r0-r12, pc}^
41
 
42
// IRQ.
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IRQ:
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sub r14, r14, #4
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stmfd sp!, {r0-r12, r14}
46 29 Revanth
 
47 26 Revanth
mov r0, #1
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mov r1, #2
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mov r2, #3
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mov r3, #4
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mov r4, #5
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mov r5, #6
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mov r6, #7
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mov r7, #8
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mov r8, #9
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mov r9, #10
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mov r10, #12
58
mov r11, #13
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mov r12, #14
60
mov r14, #15
61 29 Revanth
 
62 43 Revanth
.set TIMER_BASE_ADDRESS, 0xFFFFFFC0
63
 
64 29 Revanth
# Restart timer
65 43 Revanth
ldr r0,=TIMER_BASE_ADDRESS    // Timer base address.
66 29 Revanth
add r0, r0, #12
67 43 Revanth
mov r1, #1
68
str r1, [r0]                  // Restart the timer.
69 29 Revanth
 
70 43 Revanth
.set VIC_BASE_ADDRESS,  0xFFFFFFA0
71
.set CLEAR_ALL_PENDING, 0xFFFFFFFF
72
 
73 29 Revanth
# Clear interrupt in VIC.
74 43 Revanth
ldr r0, =VIC_BASE_ADDRESS   // VIC base address
75 29 Revanth
add r0, r0, #8
76 43 Revanth
ldr r1, =CLEAR_ALL_PENDING
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str r1, [r0]                // Clear all interrupt pending status
78 29 Revanth
 
79 43 Revanth
# Restore
80 26 Revanth
ldmfd sp!, {r0-r12, pc}^
81
 
82
FIQ:
83 43 Revanth
# Return from FIQ after writing to FIQ registers - shouldn't affect other things.
84 26 Revanth
mov r8,  #9
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mov r9,  #10
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mov r10, #12
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mov r11, #13
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mov r12, #14
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subs pc, r14, #4
90
 
91
SWI:
92 43 Revanth
.set SWI_SP_VALUE,  2500
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.set SWI_R11_VALUE, 2004
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ldr sp,=SWI_SP_VALUE
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ldr r11,=SWI_R11_VALUE
96 26 Revanth
mov r0, #12
97
mov r1, #0
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mov r2, r0, lsr #32
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mov r3, r0, lsr r1
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mov r4, #-1
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mov r5, #-1
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muls r6, r5, r4
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umull r8,  r7, r5, r4
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smull r10, r9, r5, r4
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mov r2, r10
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str r10, [r11, #4]!
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str r9,  [r11, #4]!
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add r11, r11, #4
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str r8,  [r11], #4
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str r7,  [r11], #4
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str r6,  [r11]
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stmib r11, {r6-r10}
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stmfd sp!, {r0-r12, r14}
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mrs r1, spsr
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orr r1, r1, #0x80
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msr spsr_c, r1
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mov r4, #0
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mcr p15, 0, r4, c7, c15, 0
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mov r4, #-1
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ldmfd sp!, {r0-r12, pc}^
121
 
122
there:
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// Switch to IRQ mode.
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mrs r2, cpsr
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bic r2, r2, #31
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orr r2, r2, #18
127
msr cpsr_c, r2
128
 
129 43 Revanth
.set IRQ_SP_VALUE, 3000
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ldr sp,=IRQ_SP_VALUE
131
 
132 26 Revanth
// Switch to UND mode.
133
mrs r3, cpsr
134
bic r3, r3, #31
135
orr r3, r3, #27
136
msr cpsr_c, r3
137
mov r4, #1
138
 
139 43 Revanth
.set UND_SP_VALUE, 3500
140
ldr sp, =UND_SP_VALUE
141
 
142 26 Revanth
// Enable interrupts (FIQ and IRQ).
143
mrs r1, cpsr
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bic r1, r1, #0xC0
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msr cpsr_c, r1
146
 
147
// Enable cache (Uses a single bit to enable both caches).
148 43 Revanth
.set ENABLE_CACHE_CP_WORD, 4100
149
ldr r1, =ENABLE_CACHE_CP_WORD
150 26 Revanth
mcr p15, 0, r1, c1, c1, 0
151
 
152
// Write out identitiy section mapping. Write 16KB to register 2.
153
mov r1, #1
154
mov r1, r1, lsl #14
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mcr p15, 0, r1, c2, c0, 1
156
 
157
// Set domain access control to all 1s.
158
mvn r1, #0
159
mcr p15, 0, r1, c3, c0, 0
160
 
161
// Set up a section desctiptor for identity mapping that is Cachaeable.
162
mov r1, #1
163 29 Revanth
mov r1, r1, lsl #14     // 16KB
164
mov r2, #14             // Cacheable identity descriptor.
165
str r2, [r1]            // Write identity section desctiptor to 16KB location.
166
ldr r6, [r1]            // R6 holds the descriptor.
167
mov r7, r1              // R7 holds the address.
168
 
169
// Set up a section descriptor for upper 1MB of virtual address space.
170
// This is identity mapping. Uncacheable.
171
mov r1, #1
172
mov r1, r1, lsl #14     // 16KB. This is descriptor 0.
173 43 Revanth
 
174 29 Revanth
// Go to descriptor 4095. This is the address BASE + (#DESC * 4).
175 43 Revanth
.set DESCRIPTOR_IO_SECTION_OFFSET, 16380 // 4095 x 4
176
ldr r2,=DESCRIPTOR_IO_SECTION_OFFSET
177 29 Revanth
add r1, r1, r2
178 43 Revanth
 
179 29 Revanth
// Prepare a descriptor. Descriptor = 0xFFF00002 (Uncacheable section descriptor).
180 43 Revanth
.set DESCRIPTOR_IO_SECTION, 0xFFF00002
181
ldr r2 ,=DESCRIPTOR_IO_SECTION
182 29 Revanth
str r2, [r1]
183 26 Revanth
ldr r6, [r1]
184
mov r7, r1
185
 
186
// ENABLE MMU
187 43 Revanth
.set ENABLE_MMU_CP_WORD, 4101
188
ldr r1, =ENABLE_MMU_CP_WORD
189 26 Revanth
mcr p15, 0, r1, c1, c1, 0
190
 
191
// Switch mode.
192
mrs r2, cpsr
193
bic r2, r2, #31
194
orr r2, r2, #16
195
msr cpsr_c, r2
196
 
197 43 Revanth
.set USR_SP_VALUE, 4000
198
ldr sp,=USR_SP_VALUE
199
 
200 26 Revanth
// Run main loop.
201 29 Revanth
 
202
// Program VIC to allow timer interrupts.
203 43 Revanth
ldr r0, =VIC_BASE_ADDRESS // VIC base address.
204
add r0, r0, #4            // Move to INT_MASK
205
mov r1, #0                // Prepare mask value
206
str r1, [r0]              // Unmask all interrupt sources.
207 29 Revanth
 
208 38 Revanth
// Program timer peripheral to tick every 32 clock cycles.
209 43 Revanth
ldr r0 ,=TIMER_BASE_ADDRESS     // Timer base address.
210
mov r1 , #1
211
str r1, [r0]                    // Enable timer
212 29 Revanth
add r0, r0, #4
213 43 Revanth
mov r1, #32
214
str r1, [r0]                    // Program to 255 clocks.
215 29 Revanth
add r0, r0, #8
216 43 Revanth
mov r1, #0x1
217
str r1, [r0]                    // Start the timer.
218 29 Revanth
 
219 43 Revanth
// Call C code
220
bl main
221 29 Revanth
 
222 43 Revanth
// Do SWI 0x0
223 26 Revanth
swi #0x00
224 43 Revanth
 
225
// Loop forever
226 26 Revanth
here: b here
227
 

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