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[/] [zap/] [trunk/] [src/] [ts/] [uart/] [Config.cfg] - Blame information for rev 43

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1 43 Revanth
# TC config.
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%Config = (
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        # CPU configuration.
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        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
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        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
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        CODE_SECTION_TLB_ENTRIES    => 8,       # Instruction section TLB entries.
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        CODE_SPAGE_TLB_ENTRIES      => 32,      # Instruction small page TLB entries.
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        CODE_LPAGE_TLB_ENTRIES      => 16,      # Instruction large page TLB entries.
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        DATA_SECTION_TLB_ENTRIES    => 8,       # Data section TLB entries.
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        DATA_SPAGE_TLB_ENTRIES      => 32,      # Data small page TLB entries.
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        DATA_LPAGE_TLB_ENTRIES      => 16,      # Data large page TLB entries.
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        BP_DEPTH                    => 1024,    # Branch predictor depth.
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        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
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        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
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        SYNTHESIS                   => 0,       # 0 allows debug messages.
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        # Testbench configuration.
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        WAVES                       => 1,       # Generate waveform.
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        UART0_TX_TERMINAL           => 1,       # Show TX terminal.
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        UART0_RX_TERMINAL           => 1,       # Show RX terminal.
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        EXT_RAM_SIZE                => 32768,   # External RAM size.
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        SEED                        => -1,      # Seed. Use -1 to use random seed.
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        DUMP_START                  => 2000,    # Starting memory address from which to dump.
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        DUMP_SIZE                   => 200,     # Length of dump in bytes.
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        MAX_CLOCK_CYCLES            => 0,       # Clock cycles to run the simulation for. 0 is forever.
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        REG_CHECK                   => {},      # No registers to check.
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        FINAL_CHECK                 => {}       # No memory locations to check.
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);
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