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[/] [zet86/] [trunk/] [soc/] [aceusb/] [rtl/] [aceusb.v] - Blame information for rev 52

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1 52 zeus
/*
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 *  WISHBONE to SystemACE MPU + CY7C67300 bridge
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 *  Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net
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 *  Modified on Mar 2009 by Zeus Gomez Marmolejo <zeus@opencores.org>
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 *
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 *  This file is part of the Zet processor. This processor is free
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 *  hardware; you can redistribute it and/or modify it under the terms of
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 *  the GNU General Public License as published by the Free Software
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 *  Foundation; either version 3, or (at your option) any later version.
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 *
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 *  Zet is distrubuted in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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 *  or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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 *  License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with Zet; see the file COPYING. If not, see
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 *  <http://www.gnu.org/licenses/>.
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 */
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module aceusb (
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    /* WISHBONE slave interface */
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    input         wb_clk_i,
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    input         wb_rst_i,
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    input  [ 6:1] wb_adr_i,
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    input  [15:0] wb_dat_i,
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    output [15:0] wb_dat_o,
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    input         wb_cyc_i,
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    input         wb_stb_i,
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    input         wb_we_i,
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    output reg    wb_ack_o,
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    /* Signals shared between SystemACE and USB */
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    output [ 6:1] aceusb_a_,
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    inout  [15:0] aceusb_d_,
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    output        aceusb_oe_n_,
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    output        aceusb_we_n_,
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    /* SystemACE signals */
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    input         ace_clkin_,
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    output        ace_mpce_n_,
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    output        usb_cs_n_,
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    output        usb_hpi_reset_n_
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  );
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wire access_read1;
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wire access_write1;
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wire access_ack1;
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/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
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reg load_adr_dat;
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reg [5:0] address_reg;
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reg [15:0] data_reg;
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always @(posedge wb_clk_i) begin
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  if(load_adr_dat) begin
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    address_reg <= wb_adr_i;
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    data_reg <= wb_dat_i;
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  end
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end
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aceusb_access access(
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  .ace_clkin(ace_clkin_),
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  .rst(wb_rst_i),
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  .a(address_reg),
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  .di(data_reg),
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  .do(wb_dat_o),
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  .read(access_read1),
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  .write(access_write1),
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  .ack(access_ack1),
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  .aceusb_a(aceusb_a_),
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  .aceusb_d(aceusb_d_),
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  .aceusb_oe_n(aceusb_oe_n_),
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  .aceusb_we_n(aceusb_we_n_),
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  .ace_mpce_n(ace_mpce_n_),
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  .usb_cs_n(usb_cs_n_),
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  .usb_hpi_reset_n(usb_hpi_reset_n_)
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);
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/* Synchronize read, write and acknowledgement pulses */
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reg access_read;
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reg access_write;
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wire access_ack;
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wire op;
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aceusb_sync sync_read(
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  .clk0(wb_clk_i),
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  .flagi(access_read),
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  .clk1(ace_clkin_),
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  .flago(access_read1)
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);
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aceusb_sync sync_write(
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  .clk0(wb_clk_i),
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  .flagi(access_write),
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  .clk1(ace_clkin_),
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  .flago(access_write1)
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);
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aceusb_sync sync_ack(
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  .clk0(ace_clkin_),
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  .flagi(access_ack1),
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  .clk1(wb_clk_i),
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  .flago(access_ack)
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);
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/* Main FSM */
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reg [1:0] state;
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reg [1:0] next_state;
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localparam
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  IDLE = 2'd0,
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  WAIT = 2'd1,
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  ACK  = 2'd2;
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  assign op = wb_cyc_i & wb_stb_i;
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always @(posedge wb_clk_i) begin
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  if(wb_rst_i)
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    state <= IDLE;
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  else
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    state <= next_state;
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end
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always @(state or op or wb_we_i or access_ack) begin
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  load_adr_dat = 1'b0;
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  wb_ack_o = 1'b0;
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  access_read = 1'b0;
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  access_write = 1'b0;
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  next_state = state;
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  case(state)
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    IDLE: begin
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      if(op) begin
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        load_adr_dat = 1'b1;
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        if(wb_we_i)
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          access_write = 1'b1;
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        else
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          access_read = 1'b1;
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        next_state = WAIT;
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      end
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    end
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    WAIT: begin
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      if(access_ack) begin
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        wb_ack_o = 1'b1;
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        access_write = 1'b0;
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        load_adr_dat = 1'b0;
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        access_read = 1'b0;
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        next_state = ACK;
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      end
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    end
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    ACK: begin
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      if(!op) begin
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        wb_ack_o = 1'b0;
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        next_state = IDLE;
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      end
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    end
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  endcase
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end
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endmodule

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