OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [memsim.cpp] - Blame information for rev 197

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memsim.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU core
6
//
7
// Purpose:     This creates a memory like device to act on a WISHBONE bus.
8
//              It doesn't exercise the bus thoroughly, but does give some
9
//              exercise to the bus to see whether or not the bus master
10
//              can control it.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
////////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// You should have received a copy of the GNU General Public License along
31
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
32
// target there if the PDF file isn't present.)  If not, see
33
// <http://www.gnu.org/licenses/> for a copy.
34
//
35
// License:     GPL, v3, as defined and found on www.gnu.org,
36
//              http://www.gnu.org/licenses/gpl.html
37
//
38
//
39
////////////////////////////////////////////////////////////////////////////////
40
#include <stdio.h>
41
#include <assert.h>
42
#include "memsim.h"
43
 
44
MEMSIM::MEMSIM(const unsigned int nwords) {
45
        unsigned int    nxt;
46
        for(nxt=1; nxt < nwords; nxt<<=1)
47
                ;
48
        m_len = nxt; m_mask = nxt-1;
49
        m_mem = new BUSW[m_len];
50 197 dgisselq
        m_nxt_ack = 0;
51 2 dgisselq
}
52
 
53
MEMSIM::~MEMSIM(void) {
54
        delete[]        m_mem;
55
}
56
 
57
void    MEMSIM::load(const char *fname) {
58
        FILE    *fp;
59
        unsigned int    nr;
60
 
61
        fp = fopen(fname, "r");
62
        if (!fp) {
63
                fprintf(stderr, "Could not open/load file \'%s\'\n",
64
                        fname);
65
                perror("O/S Err:");
66
                fprintf(stderr, "\tInitializing memory with zero instead.\n");
67
                nr = 0;
68
        } else {
69
                nr = fread(m_mem, sizeof(BUSW), m_len, fp);
70
                fclose(fp);
71
 
72
                if (nr != m_len) {
73
                        fprintf(stderr, "Only read %d of %d words\n",
74
                                nr, m_len);
75
                        fprintf(stderr, "\tFilling the rest with zero.\n");
76
                }
77
        }
78
 
79
        for(; nr<m_len; nr++)
80
                m_mem[nr] = 0l;
81
}
82
 
83 36 dgisselq
void    MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc,
84 2 dgisselq
                        const unsigned char wb_stb, const unsigned char wb_we,
85
                        const BUSW wb_addr, const BUSW wb_data,
86
                        unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
87 197 dgisselq
        o_ack = m_nxt_ack;
88
        o_data= m_nxt_data;
89
        m_nxt_data = wb_data;
90
        o_stall= 0;
91 36 dgisselq
        if ((wb_cyc)&&(wb_stb)&&(clk)) {
92 2 dgisselq
                if (wb_we)
93
                        m_mem[wb_addr & m_mask] = wb_data;
94 197 dgisselq
                m_nxt_ack = 1;
95
                m_nxt_data = m_mem[wb_addr & m_mask];
96
                // o_ack  = 1;
97 2 dgisselq
 
98 197 dgisselq
                {
99
                        extern FILE *gbl_dbgfp;
100
                        if (gbl_dbgfp) {
101
                                if (wb_we) fprintf(gbl_dbgfp, "MEMSIM::MEM[%08x] = %08x\n", wb_addr&m_mask, wb_data);
102
                                else
103
                                        fprintf(gbl_dbgfp, "MEMSIM::BUS = MEM[%08x] = %08x\n", wb_addr&m_mask, m_nxt_data);
104
                        }
105
                }
106 2 dgisselq
                /*
107
                printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n",
108
                        (wb_we)?"WRITE":"READ",
109
                        wb_addr, o_data);
110
                */
111 36 dgisselq
        } else if (clk) {
112 197 dgisselq
                m_nxt_ack   = 0;
113 2 dgisselq
                o_stall = 0;
114
        }
115
}
116
 
117
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.