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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 197

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18 187 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
19 2 dgisselq
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 155 dgisselq
#include <sys/types.h>
42
#include <sys/stat.h>
43
#include <fcntl.h>
44 2 dgisselq
 
45
#include <ctype.h>
46
#include <ncurses.h>
47
 
48
#include "verilated.h"
49
#include "Vzipsystem.h"
50 39 dgisselq
#include "cpudefs.h"
51 2 dgisselq
 
52
#include "testb.h"
53
// #include "twoc.h"
54
// #include "qspiflashsim.h"
55
#include "memsim.h"
56
#include "zopcodes.h"
57
#include "zparser.h"
58
 
59
#define CMD_REG         0
60
#define CMD_DATA        1
61 155 dgisselq
#define CMD_GIE         (1<<13)
62
#define CMD_SLEEP       (1<<12)
63
#define CMD_CLEAR_CACHE (1<<11)
64 2 dgisselq
#define CMD_HALT        (1<<10)
65
#define CMD_STALL       (1<<9)
66
#define CMD_INT         (1<<7)
67
#define CMD_RESET       (1<<6)
68 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
69 2 dgisselq
 
70 34 dgisselq
#define KEY_ESCAPE      27
71
#define KEY_RETURN      10
72 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
73 2 dgisselq
 
74 57 dgisselq
#define MAXERR          10000
75
 
76 155 dgisselq
#define LGRAMLEN        20
77
#define RAMBASE         0x100000
78
#define MEMWORDS        (1<<LGRAMLEN)
79 76 dgisselq
 
80
class   SPARSEMEM {
81
public:
82
        bool    m_valid;
83
        unsigned int    m_a, m_d;
84
};
85
 
86
class   ZIPSTATE {
87
public:
88
        bool            m_valid, m_gie, m_last_pc_valid;
89
        unsigned int    m_sR[16], m_uR[16];
90
        unsigned int    m_p[20];
91
        unsigned int    m_last_pc, m_pc, m_sp;
92 148 dgisselq
        SPARSEMEM       m_smem[5]; // Nearby stack memory
93
        SPARSEMEM       m_imem[5]; // Nearby instruction memory
94 76 dgisselq
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
95
 
96
        void    step(void) {
97
                m_last_pc_valid = true;
98
                m_last_pc = m_pc;
99
        }
100
};
101
 
102 187 dgisselq
extern  FILE    *gbl_dbgfp;
103
FILE    *gbl_dbgfp = NULL;
104 76 dgisselq
 
105 2 dgisselq
// No particular "parameters" need definition or redefinition here.
106
class   ZIPPY_TB : public TESTB<Vzipsystem> {
107
public:
108 9 dgisselq
        unsigned long   m_mem_size;
109 2 dgisselq
        MEMSIM          m_mem;
110
        // QSPIFLASHSIM m_flash;
111 155 dgisselq
        FILE            *m_dbgfp, *m_profile_fp;
112 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
113 34 dgisselq
        int             m_cursor;
114 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
115 76 dgisselq
        ZIPSTATE        m_state;
116 2 dgisselq
 
117 155 dgisselq
        ZIPPY_TB(void) : m_mem_size(MEMWORDS), m_mem(m_mem_size) {
118 76 dgisselq
                if (false) {
119 155 dgisselq
                        m_dbgfp = fopen("dbg.txt", "w");
120 36 dgisselq
                        dbg_flag = true;
121 187 dgisselq
                        gbl_dbgfp = m_dbgfp;
122 36 dgisselq
                } else {
123 155 dgisselq
                        m_dbgfp = NULL;
124 36 dgisselq
                        dbg_flag = false;
125 187 dgisselq
                        gbl_dbgfp = NULL;
126 36 dgisselq
                }
127 2 dgisselq
                bomb = false;
128 34 dgisselq
                m_cursor = 0;
129 43 dgisselq
                m_show_user_timers = false;
130 58 dgisselq
 
131
                m_last_instruction_tickcount = 0l;
132
                if (true) {
133
                        m_profile_fp = fopen("pfile.bin","wb");
134
                } else {
135
                        m_profile_fp = NULL;
136
                }
137 2 dgisselq
        }
138
 
139 69 dgisselq
        ~ZIPPY_TB(void) {
140 155 dgisselq
                if (m_dbgfp)
141
                        fclose(m_dbgfp);
142 69 dgisselq
                if (m_profile_fp)
143
                        fclose(m_profile_fp);
144
        }
145
 
146 2 dgisselq
        void    reset(void) {
147
                // m_flash.debug(false);
148
                TESTB<Vzipsystem>::reset();
149
        }
150
 
151
        bool    on_tick(void) {
152
                tick();
153
                return true;
154
        }
155
 
156 76 dgisselq
        void    step(void) {
157
                wb_write(CMD_REG, CMD_STEP);
158
                m_state.step();
159
        }
160
 
161
        void    read_raw_state(void) {
162
                m_state.m_valid = false;
163
                for(int i=0; i<16; i++)
164
                        m_state.m_sR[i] = cmd_read(i);
165
                for(int i=0; i<16; i++)
166
                        m_state.m_uR[i] = cmd_read(i+16);
167
                for(int i=0; i<20; i++)
168
                        m_state.m_p[i]  = cmd_read(i+32);
169
 
170 155 dgisselq
                m_state.m_gie = wb_read(CMD_REG) & CMD_GIE;
171 76 dgisselq
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
172
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
173
 
174
                if (m_state.m_last_pc_valid)
175
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
176
                else
177
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
178
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
179
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
180
                m_state.m_imem[1].m_a = m_state.m_pc;
181
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
182
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
183
 
184
                for(int i=1; i<4; i++) {
185
                        if (!m_state.m_imem[i].m_valid) {
186
                                m_state.m_imem[i+1].m_valid = false;
187
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
188
                                continue;
189
                        }
190
                        m_state.m_imem[i+1].m_a = zop_early_branch(
191
                                        m_state.m_imem[i].m_a,
192
                                        m_state.m_imem[i].m_d);
193
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
194
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
195
                }
196
 
197
                m_state.m_smem[0].m_a = m_state.m_sp;
198
                for(int i=1; i<5; i++)
199
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
200
                for(int i=0; i<5; i++) {
201
                        m_state.m_smem[i].m_valid =
202
                                (m_state.m_imem[i].m_a > 0x10000);
203
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
204
                }
205
                m_state.m_valid = true;
206
        }
207
 
208
        void    read_raw_state_cheating(void) {
209
                m_state.m_valid = false;
210
                for(int i=0; i<16; i++)
211
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
212
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
213
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
214
                for(int i=0; i<16; i++)
215
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
216
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
217
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
218
 
219 155 dgisselq
                m_state.m_gie = m_core->v__DOT__thecpu__DOT__gie;
220 76 dgisselq
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
221
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
222
 
223
                m_state.m_p[0] = m_core->v__DOT__pic_data;
224
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
225
                if (!m_show_user_timers) {
226
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
227
                } else {
228
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
229
                }
230
 
231
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
232
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
233
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
234
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
235
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
236
 
237
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
238
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
239
                m_state.m_p[10] = m_core->v__DOT__upc_data;
240
                m_state.m_p[11] = m_core->v__DOT__uic_data;
241
 
242
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
243
                m_state.m_p[13] = m_core->v__DOT__moc_data;
244
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
245
                m_state.m_p[15] = m_core->v__DOT__mic_data;
246
 
247
        }
248
 
249 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
250
                if (c)
251
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
252
                else
253
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
254 2 dgisselq
        }
255
 
256 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
257 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
258 34 dgisselq
                if (c)
259
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
260
                else
261
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
262 2 dgisselq
        }
263
 
264 155 dgisselq
        void    dbgreg(FILE *fp, int id, const char *n, unsigned int v) {
265
                /*
266
                if ((id == 14)||(id == 14+16)) {
267
                        //char  buf[64];
268
                        //fprintf(fp, " %s:",
269
                        fprintf(fp, " %s: 0x%08x ", n, v);
270
                } else
271
                */
272
                        fprintf(fp, " %s: 0x%08x ", n, v);
273
        }
274
 
275 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
276 76 dgisselq
                if (r < 16)
277
                        dispreg(y, x, n, m_state.m_sR[r], c);
278 34 dgisselq
                else
279 76 dgisselq
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
280
                move(y,x+17);
281
 
282 69 dgisselq
#ifdef  OPT_PIPELINED
283 76 dgisselq
                addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
284 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
285 34 dgisselq
                        ?'a':((c)?'<':' '));
286 76 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
287 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
288 76 dgisselq
                        ?'b':' ');
289 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
290
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
291 76 dgisselq
                        ?'W':' ');
292
#else
293
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
294
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
295 34 dgisselq
                        ?'W':((c)?'<':' '));
296 76 dgisselq
#endif
297 2 dgisselq
        }
298
 
299
        void    showins(int y, const char *lbl, const int ce, const int valid,
300 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
301
                        const bool phase) {
302
                char    la[80], lb[80];
303 2 dgisselq
 
304
                if (ce)
305
                        mvprintw(y, 0, "Ck ");
306
                else
307
                        mvprintw(y, 0, "   ");
308
                if (stall)
309
                        printw("Stl ");
310
                else
311
                        printw("    ");
312
                printw("%s: 0x%08x", lbl, pc);
313
 
314
                if (valid) {
315
                        if (gie) attroff(A_BOLD);
316
                        else    attron(A_BOLD);
317 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
318
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
319
                                printw("  %-24s", la);
320
                        else
321
                                printw("  %-24s", lb);
322 2 dgisselq
                } else {
323
                        attroff(A_BOLD);
324
                        printw("  (0x%08x)%28s", m_mem[pc],"");
325
                }
326
                attroff(A_BOLD);
327
        }
328
 
329
        void    dbgins(const char *lbl, const int ce, const int valid,
330 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
331
                        const bool phase, const bool illegal) {
332
                char    la[80], lb[80];
333 2 dgisselq
 
334 155 dgisselq
                if (!m_dbgfp)
335 2 dgisselq
                        return;
336
 
337
                if (ce)
338 155 dgisselq
                        fprintf(m_dbgfp, "%s Ck ", lbl);
339 2 dgisselq
                else
340 155 dgisselq
                        fprintf(m_dbgfp, "%s    ", lbl);
341 2 dgisselq
                if (stall)
342 155 dgisselq
                        fprintf(m_dbgfp, "Stl ");
343 2 dgisselq
                else
344 155 dgisselq
                        fprintf(m_dbgfp, "    ");
345
                fprintf(m_dbgfp, "0x%08x:  ", pc);
346 2 dgisselq
 
347
                if (valid) {
348 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
349
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
350 155 dgisselq
                                fprintf(m_dbgfp, "  %-24s", la);
351 76 dgisselq
                        else
352 155 dgisselq
                                fprintf(m_dbgfp, "  %-24s", lb);
353 2 dgisselq
                } else {
354 155 dgisselq
                        fprintf(m_dbgfp, "  (0x%08x)", m_mem[pc]);
355 76 dgisselq
                } if (illegal)
356 155 dgisselq
                        fprintf(m_dbgfp, " (Illegal)");
357
                fprintf(m_dbgfp, "\n");
358 2 dgisselq
        }
359
 
360
        void    show_state(void) {
361
                int     ln= 0;
362
 
363 76 dgisselq
                read_raw_state_cheating();
364
 
365 2 dgisselq
                mvprintw(ln,0, "Peripherals-SS"); ln++;
366 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
367 36 dgisselq
                printw(" %s",
368
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
369
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
370
                        );
371 39 dgisselq
#endif
372
 
373
#ifdef  OPT_EARLY_BRANCHING
374 69 dgisselq
                printw(" %s",
375 105 dgisselq
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":"  ");
376
                if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
377
                        printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
378
                else    printw(" %10s", "");
379
                printw(" %s",
380
                        (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":"     ");
381 39 dgisselq
#endif
382 36 dgisselq
 
383
                /*
384 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
385
                        mvprintw(ln, 17, "%s%s",
386
                                ((m_core->v__DOT__sys_cyc)
387
                                &&(m_core->v__DOT__sys_we)
388
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
389
                                (m_core->v__DOT__trap_int)?"I":" ");
390
                */
391 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
392
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
393 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
394 57 dgisselq
 
395
                if (!m_show_user_timers) {
396
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
397
                } else {
398
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
399
                }
400
 
401 76 dgisselq
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
402 2 dgisselq
 
403
                ln++;
404 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
405
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
406
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
407
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
408 2 dgisselq
 
409 43 dgisselq
 
410
                if (!m_show_user_timers) {
411
                        ln++;
412 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
413
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
414
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
415
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
416 43 dgisselq
                } else {
417
                        ln++;
418 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
419
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
420
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
421
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
422 43 dgisselq
                }
423 2 dgisselq
 
424
                ln++;
425
                mvprintw(ln, 40, "%s %s",
426
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
427
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
428 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
429 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
430
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
431
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
432 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
433
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
434
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
435 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
436
                        attroff(A_BOLD);
437
                else
438
                        attron(A_BOLD);
439
                mvprintw(ln, 0, "Supervisor Registers");
440
                ln++;
441
 
442 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
443
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
444
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
445
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
446 2 dgisselq
 
447 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
448
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
449
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
450
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
451 2 dgisselq
 
452 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
453
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
454
                showreg(ln,40, "sR10", 10, (m_cursor==22));
455
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
456 2 dgisselq
 
457 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
458
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
459 76 dgisselq
 
460
                unsigned int cc = m_state.m_sR[14];
461 134 dgisselq
                if (false) {
462 76 dgisselq
                        mvprintw(ln,40, "%ssCC : 0x%08x",
463
                                (m_cursor==26)?">":" ", cc);
464
                } else {
465
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
466
                                (m_cursor==26)?">":" ",
467
                                (cc&0x01000)?"FE":"",
468
                                (cc&0x00800)?"DE":"",
469
                                (cc&0x00400)?"BE":"",
470
                                (cc&0x00200)?"TP":"",
471
                                (cc&0x00100)?"IL":"",
472
                                (cc&0x00080)?"BK":"",
473
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
474
                        mvprintw(ln, 54, "%s%s%s%s",
475
                                (cc&8)?"V":" ",
476
                                (cc&4)?"N":" ",
477
                                (cc&2)?"C":" ",
478
                                (cc&1)?"Z":" ");
479
                }
480
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
481 69 dgisselq
                mvprintw(ln,60,"%s",
482
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
483
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
484
                                ?"V"
485
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
486 187 dgisselq
                                &&(!m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
487 69 dgisselq
                        :" "));
488 2 dgisselq
                ln++;
489
 
490
                if (m_core->v__DOT__thecpu__DOT__gie)
491
                        attron(A_BOLD);
492
                else
493
                        attroff(A_BOLD);
494 69 dgisselq
                mvprintw(ln, 0, "User Registers");
495
                mvprintw(ln, 42, "DCDR=%02x %s%s",
496
                        dcdR(),
497
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
498
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
499
                mvprintw(ln, 62, "OPR =%02x %s%s",
500 187 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opR,
501 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
502
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
503
                ln++;
504 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
505
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
506
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
507
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
508 2 dgisselq
 
509 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
510
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
511
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
512
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
513 2 dgisselq
 
514 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
515
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
516
                showreg(ln,40, "uR10", 26, (m_cursor==38));
517
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
518 2 dgisselq
 
519 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
520
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
521 76 dgisselq
                cc = m_state.m_uR[14];
522
                if (false) {
523
                        mvprintw(ln,40, "%cuCC : 0x%08x",
524
                                (m_cursor == 42)?'>':' ', cc);
525
                } else {
526
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
527
                                (m_cursor == 42)?'>':' ',
528
                                (cc & 0x1000)?"FE":"",
529
                                (cc & 0x0800)?"DE":"",
530
                                (cc & 0x0400)?"BE":"",
531
                                (cc & 0x0200)?"TP":"",
532
                                (cc & 0x0100)?"IL":"",
533
                                (cc & 0x0040)?"ST":"",
534
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
535
                        mvprintw(ln, 54, "%s%s%s%s",
536
                                (cc&8)?"V":" ",
537
                                (cc&4)?"N":" ",
538
                                (cc&2)?"C":" ",
539
                                (cc&1)?"Z":" ");
540
                }
541
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
542 69 dgisselq
                mvprintw(ln,60,"%s",
543
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
544
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
545
                                ?"V"
546
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
547 187 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
548 69 dgisselq
                        :" "));
549 2 dgisselq
 
550
                attroff(A_BOLD);
551
                ln+=1;
552
 
553 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
554 69 dgisselq
                ln++;
555
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
556
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
557
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
558
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
559
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
560
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
561
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
562
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
563
                        (m_core->v__DOT__wb_data)); ln++;
564 39 dgisselq
#else
565 69 dgisselq
 
566 76 dgisselq
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
567 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
568
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
569 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
570 187 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__tagsrc)
571
                        ?(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvalipc)
572
                        :(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvallst),
573 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_pc,
574
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
575
 
576 2 dgisselq
                ln++;
577
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
578
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
579
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
580
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
581
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
582
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
583
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
584 69 dgisselq
                        (pfstall())?"STL":"   ",
585 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
586 39 dgisselq
#endif
587 2 dgisselq
 
588
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
589 187 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GCY"
590
                                :((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LCY":"   "),
591 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
592
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
593 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
594
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
595
                        (m_core->v__DOT__thecpu__DOT__mem_data),
596
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
597 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
598 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
599
// #define      OPT_PIPELINED_BUS_ACCESS
600
#ifdef  OPT_PIPELINED_BUS_ACCESS
601
                printw(" %x%x%c%c",
602
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
603
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
604 134 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
605 39 dgisselq
                        (mem_pipe_stalled())?'S':'-'); ln++;
606
#else
607
                ln++;
608
#endif
609 2 dgisselq
 
610 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
611 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
612 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
613
                        (m_core->o_wb_stb)?"STB":"   ",
614
                        (m_core->o_wb_we )?"WE":"  ",
615
                        (m_core->o_wb_addr),
616
                        (m_core->o_wb_data),
617
                        (m_core->i_wb_ack)?"ACK":"   ",
618
                        (m_core->i_wb_stall)?"STL":"   ",
619 69 dgisselq
                        (m_core->i_wb_data),
620
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
621 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
622
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
623
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
624 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
625
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
626 187 dgisselq
                        (!m_core->v__DOT__thecpu__DOT__new_pc), //1
627
                        // (!m_core->v__DOT__thecpu__DOT__clear_pipeline),      //1
628 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
629 58 dgisselq
                        (!mem_stalled()),       //1
630 2 dgisselq
 
631 58 dgisselq
                        (mem_stalled()),
632 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
633
                        (m_core->v__DOT__thecpu__DOT__master_ce),
634
                        (mem_pipe_stalled()),
635 134 dgisselq
                        (!m_core->v__DOT__thecpu__DOT__r_op_pipe),
636 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
637
                        );
638 140 dgisselq
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_pipe);
639 76 dgisselq
                // mvprintw(4,4,"r_dcdI = 0x%06x",
640
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
641 39 dgisselq
#endif
642
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
643 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
644
                printw(" A:%c%c B:%c%c",
645 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
646
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
647 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
648
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
649 69 dgisselq
#else
650
                printw(" A:xx B:xx");
651 57 dgisselq
#endif
652 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
653 39 dgisselq
 
654
 
655 2 dgisselq
                showins(ln, "I ",
656 69 dgisselq
#ifdef  OPT_PIPELINED
657 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
658 69 dgisselq
#else
659
                        1,
660
#endif
661 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
662
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
663
                        m_core->v__DOT__thecpu__DOT__gie,
664
                        0,
665 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
666
                        true); ln++;
667 36 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
668 2 dgisselq
 
669
                showins(ln, "Dc",
670 69 dgisselq
                        dcd_ce(), dcdvalid(),
671 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
672 69 dgisselq
#ifdef  OPT_PIPELINED
673 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
674 69 dgisselq
#else
675
                        0,
676
#endif
677 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
678
#ifdef  OPT_VLIW
679
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
680
#else
681
                        false
682
#endif
683
                        ); ln++;
684 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
685
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
686
                        mvprintw(ln-1,10,"I");
687
                else
688
#endif
689
                if (m_core->v__DOT__thecpu__DOT__dcdM)
690
                        mvprintw(ln-1,10,"M");
691 2 dgisselq
 
692
                showins(ln, "Op",
693 69 dgisselq
                        op_ce(),
694 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
695 187 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
696 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__op_stall,
697 76 dgisselq
                        op_pc(),
698
#ifdef  OPT_VLIW
699
                        m_core->v__DOT__thecpu__DOT__r_op_phase
700
#else
701
                        false
702
#endif
703
                        ); ln++;
704 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
705
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
706
                        mvprintw(ln-1,10,"I");
707
                else
708
#endif
709
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
710
                        mvprintw(ln-1,10,"M");
711
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
712
                        mvprintw(ln-1,10,"A");
713 2 dgisselq
 
714 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
715
                        showins(ln, "Mm",
716
                                m_core->v__DOT__thecpu__DOT__mem_ce,
717
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
718 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
719 69 dgisselq
#ifdef  OPT_PIPELINED
720 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
721 69 dgisselq
#else
722 148 dgisselq
                                0,
723 69 dgisselq
#endif
724 148 dgisselq
                                alu_pc(),
725 76 dgisselq
#ifdef  OPT_VLIW
726 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
727 76 dgisselq
#else
728 148 dgisselq
                                false
729 76 dgisselq
#endif
730 148 dgisselq
                        );
731
                } else {
732
                        showins(ln, "Al",
733
                                m_core->v__DOT__thecpu__DOT__alu_ce,
734
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
735 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
736 148 dgisselq
#ifdef  OPT_PIPELINED
737
                                m_core->v__DOT__thecpu__DOT__alu_stall,
738
#else
739
                                0,
740
#endif
741
                                alu_pc(),
742
#ifdef  OPT_VLIW
743
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
744
#else
745
                                false
746
#endif
747
                        );
748
                } ln++;
749 39 dgisselq
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
750
                        mvprintw(ln-1,10,"W");
751 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
752
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
753
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
754
                        mvprintw(ln-1,10,"v");
755 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
756 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
757
                        mvprintw(ln-1,10,"I");
758 58 dgisselq
#endif
759 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
760
                        // mvprintw(ln-1,10,"i");
761 2 dgisselq
 
762 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
763 187 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_break)?"OB":"  ",
764
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"CLRP":"    ");
765 2 dgisselq
                mvprintw(ln-4, 48,
766
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
767
                printw("(%s:%02x,%x)",
768
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
769
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
770 187 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_gie)
771 2 dgisselq
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
772
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
773
 
774
                printw("(%s%s%s:%02x)",
775
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
776
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
777
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
778
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
779
                /*
780
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
781
                        m_core->v__DOT__thecpu__DOT__dcdI);
782
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
783
                        m_core->v__DOT__thecpu__DOT__opB);
784
                */
785 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
786 187 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opn,
787 87 dgisselq
                        m_core->v__DOT__thecpu__DOT__opA,
788
                        m_core->v__DOT__thecpu__DOT__opB);
789 27 dgisselq
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
790
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
791
                else
792
                        printw("%8s","");
793 76 dgisselq
                mvprintw(ln-1, 48, "%s%s%s ",
794
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
795 197 dgisselq
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__r_busy)?"a":" "),
796 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
797
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
798
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
799
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
800
                printw("MEM: %s%s %s%s %s %-5s",
801 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
802 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
803
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
804 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
805 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
806 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
807
        }
808
 
809 43 dgisselq
        void    show_user_timers(bool v) {
810
                m_show_user_timers = v;
811
        }
812
 
813 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
814 57 dgisselq
                int     errcount = 0;
815 155 dgisselq
                if (m_dbgfp) {
816 2 dgisselq
                        dbg_flag= true;
817 155 dgisselq
                        fprintf(m_dbgfp, "CMD-READ(%d)\n", a);
818 2 dgisselq
                }
819
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
820 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
821
                        errcount++;
822
                if (errcount >= MAXERR) {
823
                        endwin();
824
 
825
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
826 187 dgisselq
                        // printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
827
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__thecpu__DOT__r_halted);
828 57 dgisselq
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
829 187 dgisselq
                        printf("mem_cyc_gbl    = %d\n", (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl));
830
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl);
831 57 dgisselq
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
832 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
833
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
834
#ifdef  OPT_PIPELINED
835 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
836 69 dgisselq
#endif
837 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
838 105 dgisselq
// #ifdef       OPT_EARLY_BRANCHING
839 69 dgisselq
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
840 105 dgisselq
// #endif
841 57 dgisselq
 
842
                        exit(-2);
843
                }
844
 
845
                assert(errcount < MAXERR);
846 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
847
 
848
                if (dbg_flag)
849 155 dgisselq
                        fprintf(m_dbgfp, "CMD-READ(%d) = 0x%08x\n", a, v);
850 2 dgisselq
                dbg_flag = false;
851
                return v;
852
        }
853
 
854 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
855 57 dgisselq
                int     errcount = 0;
856 34 dgisselq
                if ((a&0x0f)==0x0f)
857
                        dbg_flag = true;
858
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
859 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
860
                        errcount++;
861
                assert(errcount < MAXERR);
862 34 dgisselq
                if (dbg_flag)
863 155 dgisselq
                        fprintf(m_dbgfp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
864 34 dgisselq
                wb_write(CMD_DATA, v);
865
        }
866
 
867 27 dgisselq
        bool    halted(void) {
868
                return (m_core->v__DOT__cmd_halt != 0);
869
        }
870
 
871 2 dgisselq
        void    read_state(void) {
872
                int     ln= 0;
873 34 dgisselq
                bool    gie;
874 2 dgisselq
 
875 76 dgisselq
                read_raw_state();
876 34 dgisselq
                if (m_cursor < 0)
877
                        m_cursor = 0;
878
                else if (m_cursor >= 44)
879
                        m_cursor = 43;
880
 
881
                mvprintw(ln,0, "Peripherals-RS");
882
                mvprintw(ln,40,"%-40s", "CPU State: ");
883
                {
884
                        unsigned int v = wb_read(CMD_REG);
885
                        mvprintw(ln,51, "");
886
                        if (v & 0x010000)
887
                                printw("EXT-INT ");
888
                        if ((v & 0x003000) == 0x03000)
889
                                printw("Halted ");
890
                        else if (v & 0x001000)
891
                                printw("Sleeping ");
892
                        else if (v & 0x002000)
893 76 dgisselq
                                printw("User Mod ");
894 34 dgisselq
                        if (v & 0x008000)
895
                                printw("Break-Enabled ");
896
                        if (v & 0x000080)
897
                                printw("PIC Enabled ");
898
                } ln++;
899 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
900
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
901
                showval(ln,40, "WBUS", m_state.m_p[2], false);
902
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
903 2 dgisselq
                ln++;
904 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
905
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
906
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
907
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
908 2 dgisselq
 
909
                ln++;
910 43 dgisselq
                if (!m_show_user_timers) {
911 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
912
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
913
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
914
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
915 43 dgisselq
                } else {
916 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
917
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
918
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
919
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
920 43 dgisselq
                }
921 2 dgisselq
 
922
                ln++;
923
                ln++;
924 76 dgisselq
                unsigned int cc = m_state.m_sR[14];
925 155 dgisselq
                if (m_dbgfp) fprintf(m_dbgfp, "CC = %08x, gie = %d\n", cc,
926 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__gie);
927 34 dgisselq
                gie = (cc & 0x020);
928
                if (gie)
929 2 dgisselq
                        attroff(A_BOLD);
930
                else
931
                        attron(A_BOLD);
932
                mvprintw(ln, 0, "Supervisor Registers");
933
                ln++;
934
 
935 76 dgisselq
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
936
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
937
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
938
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
939 2 dgisselq
 
940 76 dgisselq
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
941
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
942
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
943
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
944 2 dgisselq
 
945 76 dgisselq
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
946
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
947
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
948
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
949 2 dgisselq
 
950 76 dgisselq
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
951
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
952 2 dgisselq
 
953 76 dgisselq
                if (true) {
954
                        mvprintw(ln,40, "%ssCC : 0x%08x",
955
                                (m_cursor==26)?">":" ", cc);
956
                } else {
957
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
958
                                (m_cursor==26)?">":" ",
959
                                (cc&0x01000)?"FE":"",
960
                                (cc&0x00800)?"DE":"",
961
                                (cc&0x00400)?"BE":"",
962
                                (cc&0x00200)?"TP":"",
963
                                (cc&0x00100)?"IL":"",
964
                                (cc&0x00080)?"BK":"",
965
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
966
                        mvprintw(ln, 54, "%s%s%s%s",
967
                                (cc&8)?"V":" ",
968
                                (cc&4)?"N":" ",
969
                                (cc&2)?"C":" ",
970
                                (cc&1)?"Z":" ");
971
                }
972 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
973 2 dgisselq
                ln++;
974
 
975 34 dgisselq
                if (gie)
976 2 dgisselq
                        attron(A_BOLD);
977
                else
978
                        attroff(A_BOLD);
979 69 dgisselq
                mvprintw(ln, 0, "User Registers");
980
                mvprintw(ln, 42, "DCDR=%02x %s",
981
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
982
                mvprintw(ln, 62, "OPR =%02x %s%s",
983 187 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opR,
984 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
985
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
986
                ln++;
987 76 dgisselq
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
988
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
989
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
990
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
991 2 dgisselq
 
992 76 dgisselq
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
993
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
994
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
995
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
996 2 dgisselq
 
997 76 dgisselq
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
998
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
999
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
1000
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
1001 2 dgisselq
 
1002 76 dgisselq
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
1003
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
1004
                cc = m_state.m_uR[14];
1005
                if (false) {
1006
                        mvprintw(ln,40, "%cuCC : 0x%08x",
1007
                                (m_cursor == 42)?'>':' ', cc);
1008
                } else {
1009
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
1010
                                (m_cursor == 42)?'>':' ',
1011
                                (cc & 0x1000)?"FE":"",
1012
                                (cc & 0x0800)?"DE":"",
1013
                                (cc & 0x0400)?"BE":"",
1014
                                (cc & 0x0200)?"TP":"",
1015
                                (cc & 0x0100)?"IL":"",
1016
                                (cc & 0x0040)?"ST":"",
1017
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
1018
                        mvprintw(ln, 54, "%s%s%s%s",
1019
                                (cc&8)?"V":" ",
1020
                                (cc&4)?"N":" ",
1021
                                (cc&2)?"C":" ",
1022
                                (cc&1)?"Z":" ");
1023
                }
1024
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
1025 2 dgisselq
 
1026
                attroff(A_BOLD);
1027
                ln+=2;
1028
 
1029
                ln+=3;
1030
 
1031
                showins(ln, "I ",
1032 69 dgisselq
#ifdef  OPT_PIPELINED
1033 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
1034 69 dgisselq
#else
1035
                        1,
1036
#endif
1037 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
1038
                        m_core->v__DOT__thecpu__DOT__gie,
1039
                        0,
1040 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
1041
                        true); ln++;
1042 57 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
1043 2 dgisselq
 
1044
                showins(ln, "Dc",
1045 69 dgisselq
                        dcd_ce(), dcdvalid(),
1046 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
1047 69 dgisselq
#ifdef  OPT_PIPELINED
1048 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
1049 69 dgisselq
#else
1050
                        0,
1051
#endif
1052 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1053
#ifdef  OPT_VLIW
1054
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
1055
#else
1056
                        false
1057
#endif
1058
                        ); ln++;
1059 2 dgisselq
 
1060
                showins(ln, "Op",
1061 69 dgisselq
                        op_ce(),
1062 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
1063 187 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
1064 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__op_stall,
1065 76 dgisselq
                        op_pc(),
1066
#ifdef  OPT_VLIW
1067
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1068
#else
1069
                        false
1070
#endif
1071
                        ); ln++;
1072 2 dgisselq
 
1073 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
1074
                        showins(ln, "Mm",
1075
                                m_core->v__DOT__thecpu__DOT__mem_ce,
1076
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
1077 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1078 69 dgisselq
#ifdef  OPT_PIPELINED
1079 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
1080 69 dgisselq
#else
1081 148 dgisselq
                                0,
1082 69 dgisselq
#endif
1083 148 dgisselq
                                alu_pc(),
1084 76 dgisselq
#ifdef  OPT_VLIW
1085 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1086 76 dgisselq
#else
1087 148 dgisselq
                                false
1088 76 dgisselq
#endif
1089 148 dgisselq
                        );
1090
                } else {
1091
                        showins(ln, "Al",
1092
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1093
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1094 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1095 148 dgisselq
#ifdef  OPT_PIPELINED
1096
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1097
#else
1098
                                0,
1099
#endif
1100
                                alu_pc(),
1101
#ifdef  OPT_VLIW
1102
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1103
#else
1104
                                false
1105
#endif
1106
                        );
1107
                } ln++;
1108 2 dgisselq
        }
1109 69 dgisselq
 
1110 2 dgisselq
        void    tick(void) {
1111
                int gie = m_core->v__DOT__thecpu__DOT__gie;
1112
                /*
1113
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1114
                                                m_core->o_qspi_sck,
1115
                                                m_core->o_qspi_dat);
1116
                */
1117
 
1118 11 dgisselq
                int stb = m_core->o_wb_stb;
1119 187 dgisselq
                m_core->i_wb_err = 0;
1120
                if ((m_core->o_wb_addr & (-1<<20))!=(1<<20))
1121 11 dgisselq
                        stb = 0;
1122 187 dgisselq
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb)) {
1123 11 dgisselq
                        m_core->i_wb_ack = 1;
1124 187 dgisselq
                        m_core->i_wb_err = 1;
1125
                        bomb = true;
1126
                        if (m_dbgfp) fprintf(m_dbgfp, "BOMB!! (Attempting to access %08x/%08x->%08x)\n", m_core->o_wb_addr,
1127
                                (-1<<20), ((m_core->o_wb_addr)&(-1<<20)));
1128
                }
1129 2 dgisselq
 
1130 155 dgisselq
                if ((dbg_flag)&&(m_dbgfp)) {
1131
                        fprintf(m_dbgfp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1132 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1133
                                (m_core->i_dbg_stb)?"STB":
1134
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1135
                                ((m_core->i_dbg_we)?"WE":"  "),
1136
                                (m_core->i_dbg_addr),0,
1137
                                m_core->i_dbg_data,
1138
                                (m_core->o_dbg_ack)?"ACK":"   ",
1139
                                (m_core->o_dbg_stall)?"STALL":"     ",
1140
                                (m_core->o_dbg_data),
1141
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1142 187 dgisselq
                                (m_core->v__DOT__thecpu__DOT__r_halted)?"CPU-DBG_STALL":"",
1143 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
1144 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
1145
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1146 187 dgisselq
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GC":"  ",
1147
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LC":"  ",
1148 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
1149
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1150
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1151
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1152 155 dgisselq
                        fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1153 2 dgisselq
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1154
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1155
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1156
                                (m_core->v__DOT__sys_addr),
1157
                                (m_core->v__DOT__dbg_addr),
1158
                                (m_core->v__DOT__sys_data),
1159
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1160
                                (m_core->v__DOT__wb_data));
1161
                }
1162
 
1163 155 dgisselq
                if (m_dbgfp)
1164
                        fprintf(m_dbgfp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1165 69 dgisselq
                                dcd_ce(),
1166 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1167 69 dgisselq
                                op_ce(),
1168 39 dgisselq
                                op_pc(),
1169 69 dgisselq
                                dcdA()&0x01f,
1170 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_opR,
1171 2 dgisselq
                                m_core->v__DOT__cmd_halt,
1172
                                m_core->v__DOT__cpu_halt,
1173
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1174
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1175
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1176
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1177
                                m_core->v__DOT__thecpu__DOT__ipc,
1178
                                m_core->v__DOT__thecpu__DOT__upc);
1179
 
1180 155 dgisselq
                if ((m_dbgfp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1181
                        fprintf(m_dbgfp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1182 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1183 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1184
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1185 155 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1186 2 dgisselq
                                m_core->v__DOT__cmd_addr,
1187
                                m_core->v__DOT__dbg_idata,
1188
                                m_core->v__DOT__thecpu__DOT__master_ce,
1189
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1190
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1191
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1192 155 dgisselq
                } else if ((m_dbgfp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1193
                        fprintf(m_dbgfp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1194 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1195
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1196 155 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1197 2 dgisselq
                                m_core->v__DOT__cmd_addr,
1198
                                m_core->v__DOT__dbg_idata,
1199
                                m_core->v__DOT__thecpu__DOT__master_ce,
1200
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1201
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1202
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1203
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1204
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1205 155 dgisselq
                        fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
1206 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1207 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
1208 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_op_break);
1209 155 dgisselq
                } else if ((m_dbgfp)&&
1210 187 dgisselq
                                ((m_core->v__DOT__thecpu__DOT__r_op_break)
1211 76 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1212 36 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1213 155 dgisselq
                        fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1214
                        fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1215 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1216
                                m_core->v__DOT__thecpu__DOT__break_en,
1217
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1218 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_op_break,
1219 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1220 2 dgisselq
                }
1221
 
1222 155 dgisselq
                if (m_dbgfp) {
1223 187 dgisselq
                        // if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1224
                                // fprintf(m_dbgfp, "\tClear Pipeline\n");
1225 34 dgisselq
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1226 155 dgisselq
                                fprintf(m_dbgfp, "\tNew PC\n");
1227 34 dgisselq
                }
1228
 
1229 155 dgisselq
                if (m_dbgfp)
1230 187 dgisselq
                        fprintf(m_dbgfp, "-----------  TICK (%08x) ----------%s\n",
1231
                                m_core->v__DOT__jiffies__DOT__r_counter,
1232
                                (bomb)?" BOMBED!!":"");
1233 36 dgisselq
                if (false) {
1234
                        m_core->i_clk = 1;
1235
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1236
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1237
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1238
                        eval();
1239
                        m_core->i_clk = 0;
1240
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1241
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1242
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1243
                        eval();
1244
                        m_tickcount++;
1245
                } else {
1246
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1247
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1248
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1249 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
1250
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
1251
                                m_core->i_wb_err = 1;
1252
                        else
1253
                                m_core->i_wb_err = 0;
1254 36 dgisselq
                        TESTB<Vzipsystem>::tick();
1255
                }
1256 155 dgisselq
                if ((m_dbgfp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
1257
                        fprintf(m_dbgfp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1258 2 dgisselq
                                (gie)?"User":"Supervisor",
1259
                                (gie)?"Supervisor":"User",
1260
                                m_core->v__DOT__thecpu__DOT__ipc,
1261
                                m_core->v__DOT__thecpu__DOT__upc,
1262
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1263 155 dgisselq
                } if (m_dbgfp) {
1264 76 dgisselq
#ifdef  OPT_TRADITIONAL_PFCACHE
1265 155 dgisselq
                        fprintf(m_dbgfp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1266 69 dgisselq
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1267
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1268 105 dgisselq
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
1269
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
1270 69 dgisselq
                                &&(dcdvalid())
1271
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1272
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1273
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
1274
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1275 76 dgisselq
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1276
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1277 69 dgisselq
#endif
1278
                        dbgins("Dc - ",
1279
                                dcd_ce(), dcdvalid(),
1280 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1281 69 dgisselq
#ifdef  OPT_PIPELINED
1282 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1283 69 dgisselq
#else
1284
                                0,
1285
#endif
1286 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1287
#ifdef  OPT_VLIW
1288
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1289
#else
1290
                                false,
1291
#endif
1292
#ifdef  OPT_ILLEGAL_INSTRUCTION
1293
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1294
#else
1295
                                false
1296
#endif
1297
                                );
1298 69 dgisselq
                        dbgins("Op - ",
1299
                                op_ce(),
1300 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1301 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_op_gie,
1302 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__op_stall,
1303 76 dgisselq
                                op_pc(),
1304
#ifdef  OPT_VLIW
1305
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1306
#else
1307
                                false,
1308 57 dgisselq
#endif
1309 76 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
1310
                                m_core->v__DOT__thecpu__DOT__op_illegal
1311
#else
1312
                                false
1313
#endif
1314
                                );
1315 2 dgisselq
                        dbgins("Al - ",
1316
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1317
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1318 187 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1319 69 dgisselq
#ifdef  OPT_PIPELINED
1320 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1321 69 dgisselq
#else
1322
                                0,
1323
#endif
1324 76 dgisselq
                                alu_pc(),
1325
#ifdef  OPT_VLIW
1326
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1327
#else
1328
                                false,
1329
#endif
1330
#ifdef  OPT_ILLEGAL_INSTRUCTION
1331
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1332
#else
1333
                                false
1334
#endif
1335
                                );
1336 187 dgisselq
                        if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1337
                                fprintf(m_dbgfp, "WB::Reg[%2x] <= %08x\n",
1338
                                        m_core->v__DOT__thecpu__DOT__wr_reg_id,
1339
                                        m_core->v__DOT__thecpu__DOT__wr_gpreg_vl);
1340 2 dgisselq
 
1341
                }
1342 58 dgisselq
 
1343 155 dgisselq
                if ((m_dbgfp)&&((m_core->v__DOT__thecpu__DOT__div_valid)
1344
                        ||(m_core->v__DOT__thecpu__DOT__div_ce)
1345
                        ||(m_core->v__DOT__thecpu__DOT__div_busy)
1346
                        )) {
1347
                        fprintf(m_dbgfp, "DIV: %s %s %s %s[%2x] GP:%08x/SP:%08x %s:0x%08x\n",
1348
                                (m_core->v__DOT__thecpu__DOT__div_ce)?"CE":"  ",
1349
                                (m_core->v__DOT__thecpu__DOT__div_busy)?"BUSY":"    ",
1350
                                (m_core->v__DOT__thecpu__DOT__div_valid)?"VALID":"     ",
1351
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"REG-CE":"      ",
1352
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1353
                                m_core->v__DOT__thecpu__DOT__wr_gpreg_vl,
1354
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1355
                                (m_core->v__DOT__thecpu__DOT__alu_pc_valid)?"PCV":"   ",
1356 187 dgisselq
                                alu_pc());
1357 155 dgisselq
 
1358
                        fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
1359 187 dgisselq
                                alu_pc(),
1360 155 dgisselq
                                (m_core->v__DOT__thecpu__DOT__r_alu_pc_valid)?"VALID":"",
1361 187 dgisselq
                                (m_core->v__DOT__thecpu__DOT__r_alu_gie)?"ALU-GIE":"");
1362 155 dgisselq
                }
1363
 
1364 187 dgisselq
                if (m_core->v__DOT__dma_controller__DOT__dma_state) {
1365
                        fprintf(m_dbgfp, "DMA[%d]%s%s%s%s@%08x,%08x [%d%d/%4d/%4d] -> [%d%d/%04d/%04d]\n",
1366
                                m_core->v__DOT__dma_controller__DOT__dma_state,
1367
                                (m_core->v__DOT__dc_cyc)?"C":" ",
1368
                                (m_core->v__DOT__dc_stb)?"S":" ",
1369
                                (m_core->v__DOT__dc_ack)?"A":" ",
1370
                                (m_core->v__DOT__dc_err)?"E":" ",
1371
                                m_core->v__DOT__dc_addr,
1372
                                (m_core->v__DOT__dc_data),
1373
                                m_core->v__DOT__dma_controller__DOT__last_read_request,
1374
                                m_core->v__DOT__dma_controller__DOT__last_read_ack,
1375
                                m_core->v__DOT__dma_controller__DOT__nracks,
1376
                                m_core->v__DOT__dma_controller__DOT__nread,
1377
                                m_core->v__DOT__dma_controller__DOT__last_write_request,
1378
                                m_core->v__DOT__dma_controller__DOT__last_write_ack,
1379
                                m_core->v__DOT__dma_controller__DOT__nwacks,
1380
                                m_core->v__DOT__dma_controller__DOT__nwritten);
1381
                }
1382
                if (((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1383
                        ||(m_core->v__DOT__thecpu__DOT__mem_pc_valid))
1384
                        &&(!m_core->v__DOT__thecpu__DOT__new_pc)) {
1385 58 dgisselq
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1386
                        if (m_profile_fp) {
1387
                                unsigned buf[2];
1388 187 dgisselq
                                buf[0] = alu_pc();
1389 58 dgisselq
                                buf[1] = iticks;
1390
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1391
                        }
1392
                        m_last_instruction_tickcount = m_tickcount;
1393
                }
1394 2 dgisselq
        }
1395
 
1396
        bool    test_success(void) {
1397
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1398
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1399
        }
1400
 
1401 39 dgisselq
        unsigned        op_pc(void) {
1402
                /*
1403
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1404
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1405
                        r--;
1406
                return r;
1407
                */
1408
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1409
        }
1410
 
1411 69 dgisselq
        bool    dcd_ce(void) {
1412
#ifdef  OPT_PIPELINED
1413 187 dgisselq
                // return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1414
                return ((!m_core->v__DOT__thecpu__DOT__r_dcdvalid)
1415
                        ||(!m_core->v__DOT__thecpu__DOT__dcd_stalled))
1416
                        &&(m_core->v__DOT__thecpu__DOT__new_pc);
1417 69 dgisselq
#else
1418
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1419
#endif
1420
        } bool  dcdvalid(void) {
1421
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1422
        }
1423
        bool    pfstall(void) {
1424
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1425
                        ||(m_core->v__DOT__cpu_stall));
1426
        }
1427
        unsigned        dcdR(void) {
1428
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1429
        }
1430
        unsigned        dcdA(void) {
1431
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1432
        }
1433
        unsigned        dcdB(void) {
1434
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1435
        }
1436
 
1437
        bool    op_ce(void) {
1438
#ifdef  OPT_PIPELINED
1439
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1440
#else
1441
                // return (dcdvalid())&&(opvalid())
1442
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1443
                return  dcdvalid();
1444
#endif
1445
        } bool  opvalid(void) {
1446
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1447
        }
1448
 
1449 58 dgisselq
        bool    mem_busy(void) {
1450
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1451 69 dgisselq
#ifdef  OPT_PIPELINED
1452 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1453 69 dgisselq
#else
1454
                return 0;
1455
#endif
1456 58 dgisselq
        }
1457
 
1458
        bool    mem_stalled(void) {
1459
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1460
 
1461
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1462
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1463 187 dgisselq
                op_gie = m_core->v__DOT__thecpu__DOT__r_op_gie;
1464 58 dgisselq
 
1465 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1466
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1467
                a = mem_pipe_stalled();
1468 134 dgisselq
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
1469 69 dgisselq
#else
1470
                a = false;
1471
                b = false;
1472
#endif
1473 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1474
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1475 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1476 58 dgisselq
                        &&d);
1477
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1478
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1479
        }
1480
 
1481 39 dgisselq
        unsigned        alu_pc(void) {
1482
                /*
1483
                unsigned        r = op_pc();
1484
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1485
                        r--;
1486
                return r;
1487
                */
1488 187 dgisselq
                return m_core->v__DOT__thecpu__DOT__r_alu_pc-1;
1489 39 dgisselq
        }
1490
 
1491
#ifdef  OPT_PIPELINED_BUS_ACCESS
1492 69 dgisselq
        bool    mem_pipe_stalled(void) {
1493 39 dgisselq
                int     r = 0;
1494 187 dgisselq
                r = ((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)
1495
                 ||(m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl));
1496 39 dgisselq
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1497
                        ||(
1498
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1499
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1500
                return r;
1501
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1502
        }
1503
#endif
1504
 
1505 2 dgisselq
        bool    test_failure(void) {
1506 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1507
                        return 0;
1508
                else if (m_core->v__DOT__thecpu__DOT__gie)
1509 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
1510 134 dgisselq
                else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
1511
                        return true; // ADD to PC instruction
1512
                else // MOV to PC instruction
1513 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1514 43 dgisselq
                /*
1515 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1516 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1517 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1518 43 dgisselq
                */
1519 2 dgisselq
        }
1520
 
1521
        void    wb_write(unsigned a, unsigned int v) {
1522 36 dgisselq
                int     errcount = 0;
1523 2 dgisselq
                mvprintw(0,35, "%40s", "");
1524
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1525
                m_core->i_dbg_cyc = 1;
1526
                m_core->i_dbg_stb = 1;
1527
                m_core->i_dbg_we  = 1;
1528
                m_core->i_dbg_addr = a & 1;
1529
                m_core->i_dbg_data = v;
1530
 
1531
                tick();
1532 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1533 2 dgisselq
                        tick();
1534
 
1535
                m_core->i_dbg_stb = 0;
1536 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1537 2 dgisselq
                        tick();
1538
 
1539
                // Release the bus
1540
                m_core->i_dbg_cyc = 0;
1541
                m_core->i_dbg_stb = 0;
1542
                tick();
1543
                mvprintw(0,35, "%40s", "");
1544
                mvprintw(0,40, "wb_write -- complete");
1545 36 dgisselq
 
1546
 
1547 187 dgisselq
                if (errcount >= 100) {
1548
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
1549 36 dgisselq
                        bomb = true;
1550 187 dgisselq
                }
1551 2 dgisselq
        }
1552
 
1553
        unsigned long   wb_read(unsigned a) {
1554
                unsigned int    v;
1555 36 dgisselq
                int     errcount = 0;
1556 2 dgisselq
                mvprintw(0,35, "%40s", "");
1557
                mvprintw(0,40, "wb_read(0x%08x)", a);
1558
                m_core->i_dbg_cyc = 1;
1559
                m_core->i_dbg_stb = 1;
1560
                m_core->i_dbg_we  = 0;
1561
                m_core->i_dbg_addr = a & 1;
1562
 
1563
                tick();
1564 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1565 2 dgisselq
                        tick();
1566
 
1567
                m_core->i_dbg_stb = 0;
1568 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1569 2 dgisselq
                        tick();
1570
                v = m_core->o_dbg_data;
1571
 
1572
                // Release the bus
1573
                m_core->i_dbg_cyc = 0;
1574
                m_core->i_dbg_stb = 0;
1575
                tick();
1576
 
1577
                mvprintw(0,35, "%40s", "");
1578
                mvprintw(0,40, "wb_read = 0x%08x", v);
1579
 
1580 187 dgisselq
                if (errcount >= 100) {
1581
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
1582 36 dgisselq
                        bomb = true;
1583 187 dgisselq
                }
1584 2 dgisselq
                return v;
1585
        }
1586
 
1587 34 dgisselq
        void    cursor_up(void) {
1588
                if (m_cursor > 3)
1589
                        m_cursor -= 4;
1590
        } void  cursor_down(void) {
1591
                if (m_cursor < 40)
1592
                        m_cursor += 4;
1593
        } void  cursor_left(void) {
1594
                if (m_cursor > 0)
1595
                        m_cursor--;
1596
                else    m_cursor = 43;
1597
        } void  cursor_right(void) {
1598
                if (m_cursor < 43)
1599
                        m_cursor++;
1600
                else    m_cursor = 0;
1601
        }
1602
 
1603
        int     cursor(void) { return m_cursor; }
1604 155 dgisselq
 
1605
        void    jump_to(ZIPI address) {
1606
                m_core->v__DOT__thecpu__DOT__pf_pc = address;
1607 187 dgisselq
                // m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1608 155 dgisselq
                m_core->v__DOT__thecpu__DOT__new_pc = 1;
1609
        }
1610
 
1611
        void    dump_state(void) {
1612
                if (m_dbgfp)
1613
                        dump_state(m_dbgfp);
1614
        }
1615
 
1616
        void    dump_state(FILE *fp) {
1617
                if (!fp)
1618
                        return;
1619
                fprintf(fp, "FINAL STATE: %s\n",
1620
                        (m_state.m_gie)?"GIE(User-Mode)":"Supervisor-mode");
1621
                fprintf(fp, "Supervisor Registers\n");
1622
                for(int i=0; i<16; i++) {
1623
                        char str[16];
1624
                        if (i==13)
1625
                                sprintf(str, "sSP");
1626
                        else if (i==14)
1627
                                sprintf(str, "sCC");
1628
                        else if (i==15)
1629
                                sprintf(str, "sPC");
1630
                        else // if (i<=12)
1631
                                sprintf(str, "s-%2d", i);
1632
                        dbgreg(fp, i, str, m_state.m_sR[i]);
1633
                        if ((i&3)==3)
1634
                                fprintf(fp, "\n");
1635
                }
1636
                fprintf(fp, "User Registers\n");
1637
                for(int i=0; i<16; i++) {
1638
                        char str[16];
1639
                        if (i==13)
1640
                                sprintf(str, "uSP");
1641
                        else if (i==14)
1642
                                sprintf(str, "uCC");
1643
                        else if (i==15)
1644
                                sprintf(str, "uPC");
1645
                        else // if (i<=12)
1646
                                sprintf(str, "u-%2d", i);
1647
                        dbgreg(fp, i, str, m_state.m_uR[i]);
1648
                        if ((i&3)==3)
1649
                                fprintf(fp, "\n");
1650
                }
1651
        }
1652 2 dgisselq
};
1653
 
1654 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1655
        int     wy, wx, ra;
1656
        int     c = tb->cursor();
1657
 
1658
        wx = (c & 0x03) * 20 + 9;
1659
        wy = (c>>2);
1660
        if (wy >= 3+4)
1661
                wy++;
1662
        if (wy > 3)
1663
                wy += 2;
1664
        wy++;
1665
 
1666
        if (c >= 12)
1667
                ra = c - 12;
1668
        else
1669
                ra = c + 32;
1670
 
1671
        bool    done = false;
1672
        char    str[16];
1673
        int     pos = 0; str[pos] = '\0';
1674
        while(!done) {
1675
                int     chv = getch();
1676
                switch(chv) {
1677
                case KEY_ESCAPE:
1678
                        pos = 0; str[pos] = '\0'; done = true;
1679
                        break;
1680
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1681
                        done = true;
1682
                        break;
1683
                case KEY_LEFT: case KEY_BACKSPACE:
1684
                        if (pos > 0) pos--;
1685
                        break;
1686 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1687 34 dgisselq
                case KEY_CLEAR:
1688
                        pos = 0;
1689
                        break;
1690
                case '0': case ' ': str[pos++] = '0'; break;
1691
                case '1': str[pos++] = '1'; break;
1692
                case '2': str[pos++] = '2'; break;
1693
                case '3': str[pos++] = '3'; break;
1694
                case '4': str[pos++] = '4'; break;
1695
                case '5': str[pos++] = '5'; break;
1696
                case '6': str[pos++] = '6'; break;
1697
                case '7': str[pos++] = '7'; break;
1698
                case '8': str[pos++] = '8'; break;
1699
                case '9': str[pos++] = '9'; break;
1700
                case 'A': case 'a': str[pos++] = 'A'; break;
1701
                case 'B': case 'b': str[pos++] = 'B'; break;
1702
                case 'C': case 'c': str[pos++] = 'C'; break;
1703
                case 'D': case 'd': str[pos++] = 'D'; break;
1704
                case 'E': case 'e': str[pos++] = 'E'; break;
1705
                case 'F': case 'f': str[pos++] = 'F'; break;
1706
                }
1707
 
1708
                if (pos > 8)
1709
                        pos = 8;
1710
                str[pos] = '\0';
1711
 
1712
                attron(A_NORMAL | A_UNDERLINE);
1713
                mvprintw(wy, wx, "%-8s", str);
1714
                if (pos > 0) {
1715
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1716
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1717
                }
1718
                attrset(A_NORMAL);
1719
        }
1720
 
1721
        if (pos > 0) {
1722
                int     v;
1723
                v = strtoul(str, NULL, 16);
1724
                if (!tb->halted()) {
1725
                        switch(ra) {
1726
                        case 15:
1727
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1728
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1729
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1730
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1731 187 dgisselq
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1732 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1733 69 dgisselq
#ifdef  OPT_PIPELINED
1734 187 dgisselq
                                        // tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1735 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1736
#endif
1737 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1738
                                }
1739
                                break;
1740
                        case 31:
1741
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1742
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1743
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1744
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1745 187 dgisselq
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1746 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1747 69 dgisselq
#ifdef  OPT_PIPELINED
1748 187 dgisselq
                                        // tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1749 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1750
#endif
1751 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1752
                                }
1753
                                break;
1754
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1755
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1756 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1757 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1758 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1759
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1760
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1761
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1762
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1763
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1764
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1765
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1766
                        default:
1767
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1768
                                break;
1769
                        }
1770
                } else
1771
                        tb->cmd_write(ra, v);
1772
        }
1773
}
1774
 
1775 155 dgisselq
 
1776
bool    iself(const char *fname) {
1777
        FILE    *fp;
1778
        bool    ret = true;
1779
        fp = fopen(fname, "rb");
1780
 
1781
        if (!fp)        return false;
1782
        if (0x7f != fgetc(fp))  ret = false;
1783
        if ('E'  != fgetc(fp))  ret = false;
1784
        if ('L'  != fgetc(fp))  ret = false;
1785
        if ('F'  != fgetc(fp))  ret = false;
1786
        fclose(fp);
1787
        return  ret;
1788
}
1789
 
1790
long    fgetwords(FILE *fp) {
1791
        // Return the number of words in the current file, and return the 
1792
        // file as though it had never been adjusted
1793
        long    fpos, flen;
1794
        fpos = ftell(fp);
1795
        if (0 != fseek(fp, 0l, SEEK_END)) {
1796
                fprintf(stderr, "ERR: Could not determine file size\n");
1797
                perror("O/S Err:");
1798
                exit(-2);
1799
        } flen = ftell(fp);
1800
        if (0 != fseek(fp, fpos, SEEK_SET)) {
1801
                fprintf(stderr, "ERR: Could not seek on file\n");
1802
                perror("O/S Err:");
1803
                exit(-2);
1804
        } flen /= sizeof(ZIPI);
1805
        return flen;
1806
}
1807
 
1808
class   SECTION {
1809
public:
1810
        unsigned        m_start, m_len;
1811
        ZIPI            m_data[1];
1812
};
1813
 
1814
SECTION **singlesection(int nwords) {
1815
        fprintf(stderr, "NWORDS = %d\n", nwords);
1816
        size_t  sz = (2*(sizeof(SECTION)+sizeof(SECTION *))
1817
                +(nwords-1)*(sizeof(ZIPI)));
1818
        char    *d = (char *)malloc(sz);
1819
        SECTION **r = (SECTION **)d;
1820
        memset(r, 0, sz);
1821
        r[0] = (SECTION *)(&d[2*sizeof(SECTION *)]);
1822
        r[0]->m_len   = nwords;
1823
        r[1] = (SECTION *)(&r[0]->m_data[r[0]->m_len]);
1824
        r[0]->m_start = 0;
1825
        r[1]->m_start = 0;
1826
        r[1]->m_len   = 0;
1827
 
1828
        return r;
1829
}
1830
 
1831
SECTION **rawsection(const char *fname) {
1832
        SECTION         **secpp, *secp;
1833
        unsigned        num_words;
1834
        FILE            *fp;
1835
        int             nr;
1836
 
1837
        fp = fopen(fname, "r");
1838
        if (fp == NULL) {
1839
                fprintf(stderr, "Could not open: %s\n", fname);
1840
                exit(-1);
1841
        }
1842
 
1843
        if ((num_words=fgetwords(fp)) > MEMWORDS) {
1844
                fprintf(stderr, "File overruns Block RAM\n");
1845
                exit(-1);
1846
        }
1847
        secpp = singlesection(num_words);
1848
        secp = secpp[0];
1849
        secp->m_start = RAMBASE;
1850
        secp->m_len = num_words;
1851
        nr= fread(secp->m_data, sizeof(ZIPI), num_words, fp);
1852
        if (nr != (int)num_words) {
1853
                fprintf(stderr, "Could not read entire file\n");
1854
                perror("O/S Err:");
1855
                exit(-2);
1856
        } assert(secpp[1]->m_len == 0);
1857
 
1858
        return secpp;
1859
}
1860
 
1861
unsigned        byteswap(unsigned n) {
1862
        unsigned        r;
1863
 
1864
        r = (n&0x0ff); n>>= 8;
1865
        r = (r<<8) | (n&0x0ff); n>>= 8;
1866
        r = (r<<8) | (n&0x0ff); n>>= 8;
1867
        r = (r<<8) | (n&0x0ff); n>>= 8;
1868
 
1869
        return r;
1870
}
1871
 
1872
#include <libelf.h>
1873
#include <gelf.h>
1874
 
1875
void    elfread(const char *fname, unsigned &entry, SECTION **&sections) {
1876
        Elf     *e;
1877
        int     fd, i;
1878
        size_t  n;
1879
        char    *id;
1880
        Elf_Kind        ek;
1881
        GElf_Ehdr       ehdr;
1882
        GElf_Phdr       phdr;
1883
        const   bool    dbg = false;
1884
 
1885
        if (elf_version(EV_CURRENT) == EV_NONE) {
1886
                fprintf(stderr, "ELF library initialization err, %s\n", elf_errmsg(-1));
1887
                perror("O/S Err:");
1888
                exit(EXIT_FAILURE);
1889
        } if ((fd = open(fname, O_RDONLY, 0)) < 0) {
1890
                fprintf(stderr, "Could not open %s\n", fname);
1891
                perror("O/S Err:");
1892
                exit(EXIT_FAILURE);
1893
        } if ((e = elf_begin(fd, ELF_C_READ, NULL))==NULL) {
1894
                fprintf(stderr, "Could not run elf_begin, %s\n", elf_errmsg(-1));
1895
                exit(EXIT_FAILURE);
1896
        }
1897
 
1898
        ek = elf_kind(e);
1899
        if (ek == ELF_K_ELF) {
1900
                ; // This is the kind of file we should expect
1901
        } else if (ek == ELF_K_AR) {
1902
                fprintf(stderr, "Cannot run an archive!\n");
1903
                exit(EXIT_FAILURE);
1904
        } else if (ek == ELF_K_NONE) {
1905
                ;
1906
        } else {
1907
                fprintf(stderr, "Unexpected ELF file kind!\n");
1908
                exit(EXIT_FAILURE);
1909
        }
1910
 
1911
        if (gelf_getehdr(e, &ehdr) == NULL) {
1912
                fprintf(stderr, "getehdr() failed: %s\n", elf_errmsg(-1));
1913
                exit(EXIT_FAILURE);
1914
        } if ((i=gelf_getclass(e)) == ELFCLASSNONE) {
1915
                fprintf(stderr, "getclass() failed: %s\n", elf_errmsg(-1));
1916
                exit(EXIT_FAILURE);
1917
        } if ((id = elf_getident(e, NULL)) == NULL) {
1918
                fprintf(stderr, "getident() failed: %s\n", elf_errmsg(-1));
1919
                exit(EXIT_FAILURE);
1920
        } if (i != ELFCLASS32) {
1921
                fprintf(stderr, "This is a 64-bit ELF file, ZipCPU ELF files are all 32-bit\n");
1922
                exit(EXIT_FAILURE);
1923
        }
1924
 
1925
        if (dbg) {
1926
        printf("    %-20s 0x%jx\n", "e_type", (uintmax_t)ehdr.e_type);
1927
        printf("    %-20s 0x%jx\n", "e_machine", (uintmax_t)ehdr.e_machine);
1928
        printf("    %-20s 0x%jx\n", "e_version", (uintmax_t)ehdr.e_version);
1929
        printf("    %-20s 0x%jx\n", "e_entry", (uintmax_t)ehdr.e_entry);
1930
        printf("    %-20s 0x%jx\n", "e_phoff", (uintmax_t)ehdr.e_phoff);
1931
        printf("    %-20s 0x%jx\n", "e_shoff", (uintmax_t)ehdr.e_shoff);
1932
        printf("    %-20s 0x%jx\n", "e_flags", (uintmax_t)ehdr.e_flags);
1933
        printf("    %-20s 0x%jx\n", "e_ehsize", (uintmax_t)ehdr.e_ehsize);
1934
        printf("    %-20s 0x%jx\n", "e_phentsize", (uintmax_t)ehdr.e_phentsize);
1935
        printf("    %-20s 0x%jx\n", "e_shentsize", (uintmax_t)ehdr.e_shentsize);
1936
        printf("\n");
1937
        }
1938
 
1939
 
1940
        // Check whether or not this is an ELF file for the ZipCPU ...
1941
        if (ehdr.e_machine != 0x0dadd) {
1942
                fprintf(stderr, "This is not a ZipCPU ELF file\n");
1943
                exit(EXIT_FAILURE);
1944
        }
1945
 
1946
        // Get our entry address
1947
        entry = ehdr.e_entry;
1948
 
1949
 
1950
        // Now, let's go look at the program header
1951
        if (elf_getphdrnum(e, &n) != 0) {
1952
                fprintf(stderr, "elf_getphdrnum() failed: %s\n", elf_errmsg(-1));
1953
                exit(EXIT_FAILURE);
1954
        }
1955
 
1956
        unsigned total_octets = 0, current_offset=0, current_section=0;
1957
        for(i=0; i<(int)n; i++) {
1958
                total_octets += sizeof(SECTION *)+sizeof(SECTION);
1959
 
1960
                if (gelf_getphdr(e, i, &phdr) != &phdr) {
1961
                        fprintf(stderr, "getphdr() failed: %s\n", elf_errmsg(-1));
1962
                        exit(EXIT_FAILURE);
1963
                }
1964
 
1965
                if (dbg) {
1966
                printf("    %-20s 0x%x\n", "p_type",   phdr.p_type);
1967
                printf("    %-20s 0x%jx\n", "p_offset", phdr.p_offset);
1968
                printf("    %-20s 0x%jx\n", "p_vaddr",  phdr.p_vaddr);
1969
                printf("    %-20s 0x%jx\n", "p_paddr",  phdr.p_paddr);
1970
                printf("    %-20s 0x%jx\n", "p_filesz", phdr.p_filesz);
1971
                printf("    %-20s 0x%jx\n", "p_memsz",  phdr.p_memsz);
1972
                printf("    %-20s 0x%x [", "p_flags",  phdr.p_flags);
1973
 
1974
                if (phdr.p_flags & PF_X)        printf(" Execute");
1975
                if (phdr.p_flags & PF_R)        printf(" Read");
1976
                if (phdr.p_flags & PF_W)        printf(" Write");
1977
                printf("]\n");
1978
                printf("    %-20s 0x%jx\n", "p_align", phdr.p_align);
1979
                }
1980
 
1981
                total_octets += phdr.p_memsz;
1982
        }
1983
 
1984
        char    *d = (char *)malloc(total_octets + sizeof(SECTION)+sizeof(SECTION *));
1985
        memset(d, 0, total_octets);
1986
 
1987
        SECTION **r = sections = (SECTION **)d;
1988
        current_offset = (n+1)*sizeof(SECTION *);
1989
        current_section = 0;
1990
 
1991
        for(i=0; i<(int)n; i++) {
1992
                r[i] = (SECTION *)(&d[current_offset]);
1993
 
1994
                if (gelf_getphdr(e, i, &phdr) != &phdr) {
1995
                        fprintf(stderr, "getphdr() failed: %s\n", elf_errmsg(-1));
1996
                        exit(EXIT_FAILURE);
1997
                }
1998
 
1999
                if (dbg) {
2000
                printf("    %-20s 0x%jx\n", "p_offset", phdr.p_offset);
2001
                printf("    %-20s 0x%jx\n", "p_vaddr",  phdr.p_vaddr);
2002
                printf("    %-20s 0x%jx\n", "p_paddr",  phdr.p_paddr);
2003
                printf("    %-20s 0x%jx\n", "p_filesz", phdr.p_filesz);
2004
                printf("    %-20s 0x%jx\n", "p_memsz",  phdr.p_memsz);
2005
                printf("    %-20s 0x%x [", "p_flags",  phdr.p_flags);
2006
 
2007
                if (phdr.p_flags & PF_X)        printf(" Execute");
2008
                if (phdr.p_flags & PF_R)        printf(" Read");
2009
                if (phdr.p_flags & PF_W)        printf(" Write");
2010
                printf("]\n");
2011
 
2012
                printf("    %-20s 0x%jx\n", "p_align", phdr.p_align);
2013
                }
2014
 
2015
                current_section++;
2016
 
2017
                r[i]->m_start = phdr.p_vaddr;
2018
                r[i]->m_len   = phdr.p_filesz/ sizeof(ZIPI);
2019
 
2020
                current_offset += phdr.p_memsz + sizeof(SECTION);
2021
 
2022
                // Now, let's read in our section ...
2023
                if (lseek(fd, phdr.p_offset, SEEK_SET) < 0) {
2024
                        fprintf(stderr, "Could not seek to file position %08lx\n", phdr.p_offset);
2025
                        perror("O/S Err:");
2026
                        exit(EXIT_FAILURE);
2027
                } if (phdr.p_filesz > phdr.p_memsz)
2028
                        phdr.p_filesz = 0;
2029
                if (read(fd, r[i]->m_data, phdr.p_filesz) != (int)phdr.p_filesz) {
2030
                        fprintf(stderr, "Didnt read entire section\n");
2031
                        perror("O/S Err:");
2032
                        exit(EXIT_FAILURE);
2033
                }
2034
 
2035
                // Next, we need to byte swap it from big to little endian
2036
                for(unsigned j=0; j<r[i]->m_len; j++)
2037
                        r[i]->m_data[j] = byteswap(r[i]->m_data[j]);
2038
 
2039
                if (dbg) for(unsigned j=0; j<r[i]->m_len; j++)
2040
                        fprintf(stderr, "ADR[%04x] = %08x\n", r[i]->m_start+j,
2041
                        r[i]->m_data[j]);
2042
        }
2043
 
2044
        r[i] = (SECTION *)(&d[current_offset]);
2045
        r[current_section]->m_start = 0;
2046
        r[current_section]->m_len   = 0;
2047
 
2048
        elf_end(e);
2049
        close(fd);
2050
}
2051
 
2052 27 dgisselq
void    usage(void) {
2053
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
2054
        printf("\n");
2055
        printf("\tWhere testfile.out is an output file from the assembler.\n");
2056 148 dgisselq
        printf("\tThis file needs to be in a raw format and not an ELF\n");
2057
        printf("\texecutable.  It will be inserted into memory at a memory\n");
2058
        printf("\taddress of 0x0100000.  The memory device itself, the only\n");
2059
        printf("\tdevice supported by this simulator, occupies addresses from\n");
2060
        printf("\t0x0100000 to 0x01fffff.\n");
2061
        printf("\n");
2062 27 dgisselq
        printf("\t-a\tSets the testbench to run automatically without any\n");
2063
        printf("\t\tuser interaction.\n");
2064
        printf("\n");
2065
        printf("\tUser Commands:\n");
2066
        printf("\t\tWhen the test bench is run interactively, the following\n");
2067
        printf("\t\tkey strokes are recognized:\n");
2068
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
2069
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
2070
        printf("\t\t\tuser intervention.\n");
2071
        printf("\t\t\'q\'\tQuit the simulation.\n");
2072
        printf("\t\t\'r\'\tReset the processor.\n");
2073
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
2074
        printf("\t\t\tThis may consume more than one tick.\n");
2075
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
2076
}
2077 2 dgisselq
 
2078 43 dgisselq
bool    signalled = false;
2079
 
2080
void    sigint(int v) {
2081
        signalled = true;
2082
}
2083
 
2084 2 dgisselq
int     main(int argc, char **argv) {
2085
        Verilated::commandArgs(argc, argv);
2086
        ZIPPY_TB        *tb = new ZIPPY_TB();
2087 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
2088 155 dgisselq
        ZIPI            entry = RAMBASE;
2089 2 dgisselq
 
2090
        // mem[0x00000] = 0xbe000010; // Halt instruction
2091
        unsigned int mptr = 0;
2092
 
2093 43 dgisselq
        signal(SIGINT, sigint);
2094
 
2095 9 dgisselq
        if (argc <= 1) {
2096 27 dgisselq
                usage();
2097
                exit(-1);
2098 9 dgisselq
        } else {
2099
                for(int argn=1; argn<argc; argn++) {
2100 27 dgisselq
                        if (argv[argn][0] == '-') {
2101
                                switch(argv[argn][1]) {
2102
                                case 'a':
2103
                                        autorun = true;
2104
                                        break;
2105
                                case 'e':
2106
                                        exit_on_done = true;
2107
                                        break;
2108
                                case 'h':
2109
                                        usage();
2110
                                        exit(0);
2111
                                        break;
2112 36 dgisselq
                                case 's':
2113
                                        autostep = true;
2114
                                        break;
2115 27 dgisselq
                                default:
2116
                                        usage();
2117
                                        exit(-1);
2118
                                        break;
2119
                                }
2120
                        } else if (access(argv[argn], R_OK)==0) {
2121 155 dgisselq
                                if (iself(argv[argn])) {
2122
                                        SECTION **secpp = NULL, *secp;
2123
                                        elfread(argv[argn], entry, secpp);
2124
                                        for(int i=0; secpp[i]->m_len; i++) {
2125
                                                secp = secpp[i];
2126
                                                assert(secp->m_start >= RAMBASE);
2127
                                                assert(secp->m_start+secp->m_len <= RAMBASE+MEMWORDS);
2128
                                                memcpy(&tb->m_mem[secp->m_start-RAMBASE],
2129
                                                        &secp->m_data,
2130
                                                        secp->m_len*sizeof(ZIPI));
2131
                                                mptr = secp->m_start+secp->m_len;
2132
                                        }
2133
                                } else {
2134 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
2135 58 dgisselq
                                int     nr, nv = 0;
2136 9 dgisselq
                                if (fp == NULL) {
2137
                                        printf("Cannot open %s\n", argv[argn]);
2138
                                        perror("O/S Err: ");
2139
                                        exit(-1);
2140 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
2141 9 dgisselq
                                fclose(fp);
2142 58 dgisselq
                                mptr+= nr;
2143
                                if (nr == 0) {
2144
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
2145
                                        perror("O/S  Err?:");
2146
                                        exit(-2);
2147
                                } for(int i=0; i<nr; i++) {
2148
                                        if (tb->m_mem[mptr-nr+i])
2149
                                                nv++;
2150
                                } if (nv == 0) {
2151
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
2152
                                        perror("O/S  Err?:");
2153
                                        exit(-2);
2154
                                }
2155 155 dgisselq
                                }
2156 58 dgisselq
                        } else {
2157
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
2158
                                exit(-2);
2159 9 dgisselq
                        }
2160
                }
2161
        }
2162
 
2163 58 dgisselq
 
2164
        assert(mptr > 0);
2165
 
2166 27 dgisselq
        if (autorun) {
2167
                bool    done = false;
2168 2 dgisselq
 
2169 27 dgisselq
                printf("Running in non-interactive mode\n");
2170
                tb->reset();
2171
                for(int i=0; i<2; i++)
2172
                        tb->tick();
2173
                tb->m_core->v__DOT__cmd_halt = 0;
2174 155 dgisselq
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
2175
                tb->wb_write(CMD_DATA, entry);
2176
                tb->wb_write(CMD_REG, 15);
2177 27 dgisselq
                while(!done) {
2178
                        tb->tick();
2179
 
2180
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
2181
                                // tb->m_core->v__DOT__cmd_halt = 0;
2182
                                // tb->m_core->v__DOT__cmd_step = 0;
2183
 
2184 34 dgisselq
                        /*
2185 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
2186
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
2187
                                tb->m_core->v__DOT__thecpu__DOT__upc,
2188
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
2189 34 dgisselq
                        */
2190 27 dgisselq
 
2191
                        done = (tb->test_success())||(tb->test_failure());
2192 43 dgisselq
                        done = done || signalled;
2193 27 dgisselq
                }
2194 36 dgisselq
        } else if (autostep) {
2195
                bool    done = false;
2196
 
2197
                printf("Running in non-interactive mode, via step commands\n");
2198 155 dgisselq
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
2199
                tb->wb_write(CMD_DATA, entry);
2200
                tb->wb_write(CMD_REG, 15);
2201 36 dgisselq
                while(!done) {
2202
                        tb->wb_write(CMD_REG, CMD_STEP);
2203
                        done = (tb->test_success())||(tb->test_failure());
2204 43 dgisselq
                        done = done || signalled;
2205 36 dgisselq
                }
2206 27 dgisselq
        } else { // Interactive
2207
                initscr();
2208
                raw();
2209
                noecho();
2210
                keypad(stdscr, true);
2211
 
2212 69 dgisselq
                // tb->reset();
2213
                // for(int i=0; i<2; i++)
2214
                        // tb->tick();
2215
                tb->m_core->v__DOT__cmd_reset = 1;
2216 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
2217
 
2218 155 dgisselq
                tb->jump_to(entry);
2219
 
2220 76 dgisselq
                // For debugging purposes: do we wish to skip some number of
2221
                // instructions to fast forward to a time of interest??
2222 187 dgisselq
                for(int i=0; i<0; i++) {
2223 76 dgisselq
                        tb->m_core->v__DOT__cmd_halt = 0;
2224
                        tb->tick();
2225
                }
2226
 
2227 27 dgisselq
                int     chv = 'q';
2228
 
2229 43 dgisselq
                bool    done = false, halted = true, manual = true,
2230
                        high_speed = false;
2231 2 dgisselq
 
2232
                halfdelay(1);
2233 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
2234 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
2235
                        // tb->show_state();
2236
 
2237
                while(!done) {
2238 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
2239 87 dgisselq
                                // chv = getch();
2240
 
2241 43 dgisselq
                                struct  pollfd  fds[1];
2242
                                fds[0].fd = STDIN_FILENO;
2243
                                fds[0].events = POLLIN;
2244 87 dgisselq
 
2245 43 dgisselq
                                if (poll(fds, 1, 0) > 0)
2246
                                        chv = getch();
2247
                                else
2248
                                        chv = ERR;
2249 87 dgisselq
 
2250 43 dgisselq
                        } else {
2251
                                chv = getch();
2252
                        }
2253 2 dgisselq
                        switch(chv) {
2254
                        case 'h': case 'H':
2255
                                tb->wb_write(CMD_REG, CMD_HALT);
2256
                                if (!halted)
2257
                                        erase();
2258
                                halted = true;
2259
                                break;
2260 43 dgisselq
                        case 'G':
2261
                                high_speed = true;
2262 87 dgisselq
                                // cbreak();
2263 43 dgisselq
                        case 'g'