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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 151

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 76 dgisselq
 
71
class   SPARSEMEM {
72
public:
73
        bool    m_valid;
74
        unsigned int    m_a, m_d;
75
};
76
 
77
class   ZIPSTATE {
78
public:
79
        bool            m_valid, m_gie, m_last_pc_valid;
80
        unsigned int    m_sR[16], m_uR[16];
81
        unsigned int    m_p[20];
82
        unsigned int    m_last_pc, m_pc, m_sp;
83 148 dgisselq
        SPARSEMEM       m_smem[5]; // Nearby stack memory
84
        SPARSEMEM       m_imem[5]; // Nearby instruction memory
85 76 dgisselq
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
86
 
87
        void    step(void) {
88
                m_last_pc_valid = true;
89
                m_last_pc = m_pc;
90
        }
91
};
92
 
93
 
94 2 dgisselq
// No particular "parameters" need definition or redefinition here.
95
class   ZIPPY_TB : public TESTB<Vzipsystem> {
96
public:
97 9 dgisselq
        unsigned long   m_mem_size;
98 2 dgisselq
        MEMSIM          m_mem;
99
        // QSPIFLASHSIM m_flash;
100 58 dgisselq
        FILE            *dbg_fp, *m_profile_fp;
101 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
102 34 dgisselq
        int             m_cursor;
103 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
104 76 dgisselq
        ZIPSTATE        m_state;
105 2 dgisselq
 
106 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
107 76 dgisselq
                if (false) {
108 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
109
                        dbg_flag = true;
110
                } else {
111
                        dbg_fp = NULL;
112
                        dbg_flag = false;
113
                }
114 2 dgisselq
                bomb = false;
115 34 dgisselq
                m_cursor = 0;
116 43 dgisselq
                m_show_user_timers = false;
117 58 dgisselq
 
118
                m_last_instruction_tickcount = 0l;
119
                if (true) {
120
                        m_profile_fp = fopen("pfile.bin","wb");
121
                } else {
122
                        m_profile_fp = NULL;
123
                }
124 2 dgisselq
        }
125
 
126 69 dgisselq
        ~ZIPPY_TB(void) {
127
                if (dbg_fp)
128
                        fclose(dbg_fp);
129
                if (m_profile_fp)
130
                        fclose(m_profile_fp);
131
        }
132
 
133 2 dgisselq
        void    reset(void) {
134
                // m_flash.debug(false);
135
                TESTB<Vzipsystem>::reset();
136
        }
137
 
138
        bool    on_tick(void) {
139
                tick();
140
                return true;
141
        }
142
 
143 76 dgisselq
        void    step(void) {
144
                wb_write(CMD_REG, CMD_STEP);
145
                m_state.step();
146
        }
147
 
148
        void    read_raw_state(void) {
149
                m_state.m_valid = false;
150
                for(int i=0; i<16; i++)
151
                        m_state.m_sR[i] = cmd_read(i);
152
                for(int i=0; i<16; i++)
153
                        m_state.m_uR[i] = cmd_read(i+16);
154
                for(int i=0; i<20; i++)
155
                        m_state.m_p[i]  = cmd_read(i+32);
156
 
157
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
158
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
159
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
160
 
161
                if (m_state.m_last_pc_valid)
162
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
163
                else
164
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
165
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
166
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
167
                m_state.m_imem[1].m_a = m_state.m_pc;
168
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
169
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
170
 
171
                for(int i=1; i<4; i++) {
172
                        if (!m_state.m_imem[i].m_valid) {
173
                                m_state.m_imem[i+1].m_valid = false;
174
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
175
                                continue;
176
                        }
177
                        m_state.m_imem[i+1].m_a = zop_early_branch(
178
                                        m_state.m_imem[i].m_a,
179
                                        m_state.m_imem[i].m_d);
180
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
181
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
182
                }
183
 
184
                m_state.m_smem[0].m_a = m_state.m_sp;
185
                for(int i=1; i<5; i++)
186
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
187
                for(int i=0; i<5; i++) {
188
                        m_state.m_smem[i].m_valid =
189
                                (m_state.m_imem[i].m_a > 0x10000);
190
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
191
                }
192
                m_state.m_valid = true;
193
        }
194
 
195
        void    read_raw_state_cheating(void) {
196
                m_state.m_valid = false;
197
                for(int i=0; i<16; i++)
198
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
199
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
200
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
201
                for(int i=0; i<16; i++)
202
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
203
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
204
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
205
 
206
                m_state.m_gie = (m_state.m_sR[14] & 0x020);
207
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
208
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
209
 
210
                m_state.m_p[0] = m_core->v__DOT__pic_data;
211
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
212
                if (!m_show_user_timers) {
213
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
214
                } else {
215
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
216
                }
217
 
218
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
219
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
220
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
221
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
222
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
223
 
224
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
225
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
226
                m_state.m_p[10] = m_core->v__DOT__upc_data;
227
                m_state.m_p[11] = m_core->v__DOT__uic_data;
228
 
229
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
230
                m_state.m_p[13] = m_core->v__DOT__moc_data;
231
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
232
                m_state.m_p[15] = m_core->v__DOT__mic_data;
233
 
234
        }
235
 
236 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
237
                if (c)
238
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
239
                else
240
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
241 2 dgisselq
        }
242
 
243 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
244 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
245 34 dgisselq
                if (c)
246
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
247
                else
248
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
249 2 dgisselq
        }
250
 
251 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
252 76 dgisselq
                if (r < 16)
253
                        dispreg(y, x, n, m_state.m_sR[r], c);
254 34 dgisselq
                else
255 76 dgisselq
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
256
                move(y,x+17);
257
 
258 69 dgisselq
#ifdef  OPT_PIPELINED
259 76 dgisselq
                addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
260 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
261 34 dgisselq
                        ?'a':((c)?'<':' '));
262 76 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
263 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
264 76 dgisselq
                        ?'b':' ');
265 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
266
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
267 76 dgisselq
                        ?'W':' ');
268
#else
269
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
270
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
271 34 dgisselq
                        ?'W':((c)?'<':' '));
272 76 dgisselq
#endif
273 2 dgisselq
        }
274
 
275
        void    showins(int y, const char *lbl, const int ce, const int valid,
276 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
277
                        const bool phase) {
278
                char    la[80], lb[80];
279 2 dgisselq
 
280
                if (ce)
281
                        mvprintw(y, 0, "Ck ");
282
                else
283
                        mvprintw(y, 0, "   ");
284
                if (stall)
285
                        printw("Stl ");
286
                else
287
                        printw("    ");
288
                printw("%s: 0x%08x", lbl, pc);
289
 
290
                if (valid) {
291
                        if (gie) attroff(A_BOLD);
292
                        else    attron(A_BOLD);
293 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
294
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
295
                                printw("  %-24s", la);
296
                        else
297
                                printw("  %-24s", lb);
298 2 dgisselq
                } else {
299
                        attroff(A_BOLD);
300
                        printw("  (0x%08x)%28s", m_mem[pc],"");
301
                }
302
                attroff(A_BOLD);
303
        }
304
 
305
        void    dbgins(const char *lbl, const int ce, const int valid,
306 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
307
                        const bool phase, const bool illegal) {
308
                char    la[80], lb[80];
309 2 dgisselq
 
310
                if (!dbg_fp)
311
                        return;
312
 
313
                if (ce)
314
                        fprintf(dbg_fp, "%s Ck ", lbl);
315
                else
316
                        fprintf(dbg_fp, "%s    ", lbl);
317
                if (stall)
318
                        fprintf(dbg_fp, "Stl ");
319
                else
320
                        fprintf(dbg_fp, "    ");
321
                fprintf(dbg_fp, "0x%08x:  ", pc);
322
 
323
                if (valid) {
324 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
325
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
326
                                fprintf(dbg_fp, "  %-24s", la);
327
                        else
328
                                fprintf(dbg_fp, "  %-24s", lb);
329 2 dgisselq
                } else {
330 76 dgisselq
                        fprintf(dbg_fp, "  (0x%08x)", m_mem[pc]);
331
                } if (illegal)
332
                        fprintf(dbg_fp, " (Illegal)");
333
                fprintf(dbg_fp, "\n");
334 2 dgisselq
        }
335
 
336
        void    show_state(void) {
337
                int     ln= 0;
338
 
339 76 dgisselq
                read_raw_state_cheating();
340
 
341 2 dgisselq
                mvprintw(ln,0, "Peripherals-SS"); ln++;
342 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
343 36 dgisselq
                printw(" %s",
344
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
345
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
346
                        );
347 39 dgisselq
#endif
348
 
349
#ifdef  OPT_EARLY_BRANCHING
350 69 dgisselq
                printw(" %s",
351 105 dgisselq
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":"  ");
352
                if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
353
                        printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
354
                else    printw(" %10s", "");
355
                printw(" %s",
356
                        (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":"     ");
357 39 dgisselq
#endif
358 36 dgisselq
 
359
                /*
360 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
361
                        mvprintw(ln, 17, "%s%s",
362
                                ((m_core->v__DOT__sys_cyc)
363
                                &&(m_core->v__DOT__sys_we)
364
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
365
                                (m_core->v__DOT__trap_int)?"I":" ");
366
                */
367 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
368
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
369 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
370 57 dgisselq
 
371
                if (!m_show_user_timers) {
372
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
373
                } else {
374
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
375
                }
376
 
377 76 dgisselq
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
378 2 dgisselq
 
379
                ln++;
380 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
381
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
382
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
383
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
384 2 dgisselq
 
385 43 dgisselq
 
386
                if (!m_show_user_timers) {
387
                        ln++;
388 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
389
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
390
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
391
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
392 43 dgisselq
                } else {
393
                        ln++;
394 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
395
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
396
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
397
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
398 43 dgisselq
                }
399 2 dgisselq
 
400
                ln++;
401
                mvprintw(ln, 40, "%s %s",
402
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
403
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
404 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
405 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
406
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
407
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
408 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
409
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
410
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
411 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
412
                        attroff(A_BOLD);
413
                else
414
                        attron(A_BOLD);
415
                mvprintw(ln, 0, "Supervisor Registers");
416
                ln++;
417
 
418 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
419
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
420
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
421
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
422 2 dgisselq
 
423 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
424
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
425
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
426
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
427 2 dgisselq
 
428 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
429
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
430
                showreg(ln,40, "sR10", 10, (m_cursor==22));
431
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
432 2 dgisselq
 
433 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
434
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
435 76 dgisselq
 
436
                unsigned int cc = m_state.m_sR[14];
437 134 dgisselq
                if (false) {
438 76 dgisselq
                        mvprintw(ln,40, "%ssCC : 0x%08x",
439
                                (m_cursor==26)?">":" ", cc);
440
                } else {
441
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
442
                                (m_cursor==26)?">":" ",
443
                                (cc&0x01000)?"FE":"",
444
                                (cc&0x00800)?"DE":"",
445
                                (cc&0x00400)?"BE":"",
446
                                (cc&0x00200)?"TP":"",
447
                                (cc&0x00100)?"IL":"",
448
                                (cc&0x00080)?"BK":"",
449
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
450
                        mvprintw(ln, 54, "%s%s%s%s",
451
                                (cc&8)?"V":" ",
452
                                (cc&4)?"N":" ",
453
                                (cc&2)?"C":" ",
454
                                (cc&1)?"Z":" ");
455
                }
456
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
457 69 dgisselq
                mvprintw(ln,60,"%s",
458
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
459
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
460
                                ?"V"
461
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
462
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
463
                        :" "));
464 2 dgisselq
                ln++;
465
 
466
                if (m_core->v__DOT__thecpu__DOT__gie)
467
                        attron(A_BOLD);
468
                else
469
                        attroff(A_BOLD);
470 69 dgisselq
                mvprintw(ln, 0, "User Registers");
471
                mvprintw(ln, 42, "DCDR=%02x %s%s",
472
                        dcdR(),
473
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
474
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
475
                mvprintw(ln, 62, "OPR =%02x %s%s",
476
                        m_core->v__DOT__thecpu__DOT__opR,
477
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
478
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
479
                ln++;
480 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
481
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
482
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
483
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
484 2 dgisselq
 
485 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
486
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
487
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
488
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
489 2 dgisselq
 
490 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
491
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
492
                showreg(ln,40, "uR10", 26, (m_cursor==38));
493
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
494 2 dgisselq
 
495 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
496
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
497 76 dgisselq
                cc = m_state.m_uR[14];
498
                if (false) {
499
                        mvprintw(ln,40, "%cuCC : 0x%08x",
500
                                (m_cursor == 42)?'>':' ', cc);
501
                } else {
502
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
503
                                (m_cursor == 42)?'>':' ',
504
                                (cc & 0x1000)?"FE":"",
505
                                (cc & 0x0800)?"DE":"",
506
                                (cc & 0x0400)?"BE":"",
507
                                (cc & 0x0200)?"TP":"",
508
                                (cc & 0x0100)?"IL":"",
509
                                (cc & 0x0040)?"ST":"",
510
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
511
                        mvprintw(ln, 54, "%s%s%s%s",
512
                                (cc&8)?"V":" ",
513
                                (cc&4)?"N":" ",
514
                                (cc&2)?"C":" ",
515
                                (cc&1)?"Z":" ");
516
                }
517
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
518 69 dgisselq
                mvprintw(ln,60,"%s",
519
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
520
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
521
                                ?"V"
522
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
523
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
524
                        :" "));
525 2 dgisselq
 
526
                attroff(A_BOLD);
527
                ln+=1;
528
 
529 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
530 69 dgisselq
                ln++;
531
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
532
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
533
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
534
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
535
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
536
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
537
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
538
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
539
                        (m_core->v__DOT__wb_data)); ln++;
540 39 dgisselq
#else
541 69 dgisselq
 
542 76 dgisselq
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
543 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
544
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
545 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
546 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
547
                        m_core->v__DOT__thecpu__DOT__pf_pc,
548
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
549
 
550 2 dgisselq
                ln++;
551
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
552
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
553
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
554
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
555
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
556
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
557
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
558 69 dgisselq
                        (pfstall())?"STL":"   ",
559 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
560 39 dgisselq
#endif
561 2 dgisselq
 
562
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
563 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
564
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
565
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
566
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
567 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
568
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
569
                        (m_core->v__DOT__thecpu__DOT__mem_data),
570
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
571 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
572 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
573
// #define      OPT_PIPELINED_BUS_ACCESS
574
#ifdef  OPT_PIPELINED_BUS_ACCESS
575
                printw(" %x%x%c%c",
576
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
577
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
578 134 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
579 39 dgisselq
                        (mem_pipe_stalled())?'S':'-'); ln++;
580
#else
581
                ln++;
582
#endif
583 2 dgisselq
 
584 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
585 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
586 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
587
                        (m_core->o_wb_stb)?"STB":"   ",
588
                        (m_core->o_wb_we )?"WE":"  ",
589
                        (m_core->o_wb_addr),
590
                        (m_core->o_wb_data),
591
                        (m_core->i_wb_ack)?"ACK":"   ",
592
                        (m_core->i_wb_stall)?"STL":"   ",
593 69 dgisselq
                        (m_core->i_wb_data),
594
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
595 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
596
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
597
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
598 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
599
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
600
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
601
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
602 58 dgisselq
                        (!mem_stalled()),       //1
603 2 dgisselq
 
604 58 dgisselq
                        (mem_stalled()),
605 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
606
                        (m_core->v__DOT__thecpu__DOT__master_ce),
607
                        (mem_pipe_stalled()),
608 134 dgisselq
                        (!m_core->v__DOT__thecpu__DOT__r_op_pipe),
609 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
610
                        );
611 140 dgisselq
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_pipe);
612 76 dgisselq
                // mvprintw(4,4,"r_dcdI = 0x%06x",
613
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
614 39 dgisselq
#endif
615
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
616 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
617
                printw(" A:%c%c B:%c%c",
618 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
619
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
620 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
621
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
622 69 dgisselq
#else
623
                printw(" A:xx B:xx");
624 57 dgisselq
#endif
625 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
626 39 dgisselq
 
627
 
628 2 dgisselq
                showins(ln, "I ",
629 69 dgisselq
#ifdef  OPT_PIPELINED
630 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
631 69 dgisselq
#else
632
                        1,
633
#endif
634 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
635
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
636
                        m_core->v__DOT__thecpu__DOT__gie,
637
                        0,
638 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
639
                        true); ln++;
640 36 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
641 2 dgisselq
 
642
                showins(ln, "Dc",
643 69 dgisselq
                        dcd_ce(), dcdvalid(),
644 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
645 69 dgisselq
#ifdef  OPT_PIPELINED
646 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
647 69 dgisselq
#else
648
                        0,
649
#endif
650 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
651
#ifdef  OPT_VLIW
652
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
653
#else
654
                        false
655
#endif
656
                        ); ln++;
657 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
658
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
659
                        mvprintw(ln-1,10,"I");
660
                else
661
#endif
662
                if (m_core->v__DOT__thecpu__DOT__dcdM)
663
                        mvprintw(ln-1,10,"M");
664 2 dgisselq
 
665
                showins(ln, "Op",
666 69 dgisselq
                        op_ce(),
667 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
668
                        m_core->v__DOT__thecpu__DOT__op_gie,
669
                        m_core->v__DOT__thecpu__DOT__op_stall,
670 76 dgisselq
                        op_pc(),
671
#ifdef  OPT_VLIW
672
                        m_core->v__DOT__thecpu__DOT__r_op_phase
673
#else
674
                        false
675
#endif
676
                        ); ln++;
677 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
678
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
679
                        mvprintw(ln-1,10,"I");
680
                else
681
#endif
682
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
683
                        mvprintw(ln-1,10,"M");
684
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
685
                        mvprintw(ln-1,10,"A");
686 2 dgisselq
 
687 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
688
                        showins(ln, "Mm",
689
                                m_core->v__DOT__thecpu__DOT__mem_ce,
690
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
691
                                m_core->v__DOT__thecpu__DOT__alu_gie,
692 69 dgisselq
#ifdef  OPT_PIPELINED
693 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
694 69 dgisselq
#else
695 148 dgisselq
                                0,
696 69 dgisselq
#endif
697 148 dgisselq
                                alu_pc(),
698 76 dgisselq
#ifdef  OPT_VLIW
699 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
700 76 dgisselq
#else
701 148 dgisselq
                                false
702 76 dgisselq
#endif
703 148 dgisselq
                        );
704
                } else {
705
                        showins(ln, "Al",
706
                                m_core->v__DOT__thecpu__DOT__alu_ce,
707
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
708
                                m_core->v__DOT__thecpu__DOT__alu_gie,
709
#ifdef  OPT_PIPELINED
710
                                m_core->v__DOT__thecpu__DOT__alu_stall,
711
#else
712
                                0,
713
#endif
714
                                alu_pc(),
715
#ifdef  OPT_VLIW
716
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
717
#else
718
                                false
719
#endif
720
                        );
721
                } ln++;
722 39 dgisselq
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
723
                        mvprintw(ln-1,10,"W");
724 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
725
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
726
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
727
                        mvprintw(ln-1,10,"v");
728 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
729 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
730
                        mvprintw(ln-1,10,"I");
731 58 dgisselq
#endif
732 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
733
                        // mvprintw(ln-1,10,"i");
734 2 dgisselq
 
735 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
736 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
737
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
738 2 dgisselq
                mvprintw(ln-4, 48,
739
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
740
                printw("(%s:%02x,%x)",
741
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
742
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
743
                        (m_core->v__DOT__thecpu__DOT__op_gie)
744
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
745
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
746
 
747
                printw("(%s%s%s:%02x)",
748
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
749
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
750
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
751
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
752
                /*
753
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
754
                        m_core->v__DOT__thecpu__DOT__dcdI);
755
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
756
                        m_core->v__DOT__thecpu__DOT__opB);
757
                */
758 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
759 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
760 87 dgisselq
                        m_core->v__DOT__thecpu__DOT__opA,
761
                        m_core->v__DOT__thecpu__DOT__opB);
762 27 dgisselq
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
763
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
764
                else
765
                        printw("%8s","");
766 76 dgisselq
                mvprintw(ln-1, 48, "%s%s%s ",
767
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
768 87 dgisselq
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__genblk2__DOT__r_busy)?"a":" "),
769 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
770
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
771
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
772
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
773
                printw("MEM: %s%s %s%s %s %-5s",
774 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
775 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
776
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
777 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
778 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
779 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
780
        }
781
 
782 43 dgisselq
        void    show_user_timers(bool v) {
783
                m_show_user_timers = v;
784
        }
785
 
786 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
787 57 dgisselq
                int     errcount = 0;
788 2 dgisselq
                if (dbg_fp) {
789
                        dbg_flag= true;
790
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
791
                }
792
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
793 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
794
                        errcount++;
795
                if (errcount >= MAXERR) {
796
                        endwin();
797
 
798
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
799
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
800
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
801
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
802
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
803
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
804
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
805 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
806
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
807
#ifdef  OPT_PIPELINED
808 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
809 69 dgisselq
#endif
810 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
811 105 dgisselq
// #ifdef       OPT_EARLY_BRANCHING
812 69 dgisselq
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
813 105 dgisselq
// #endif
814 57 dgisselq
 
815
                        exit(-2);
816
                }
817
 
818
                assert(errcount < MAXERR);
819 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
820
 
821
                if (dbg_flag)
822 76 dgisselq
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a, v);
823 2 dgisselq
                dbg_flag = false;
824
                return v;
825
        }
826
 
827 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
828 57 dgisselq
                int     errcount = 0;
829 34 dgisselq
                if ((a&0x0f)==0x0f)
830
                        dbg_flag = true;
831
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
832 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
833
                        errcount++;
834
                assert(errcount < MAXERR);
835 34 dgisselq
                if (dbg_flag)
836
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
837
                wb_write(CMD_DATA, v);
838
        }
839
 
840 27 dgisselq
        bool    halted(void) {
841
                return (m_core->v__DOT__cmd_halt != 0);
842
        }
843
 
844 2 dgisselq
        void    read_state(void) {
845
                int     ln= 0;
846 34 dgisselq
                bool    gie;
847 2 dgisselq
 
848 76 dgisselq
                read_raw_state();
849 34 dgisselq
                if (m_cursor < 0)
850
                        m_cursor = 0;
851
                else if (m_cursor >= 44)
852
                        m_cursor = 43;
853
 
854
                mvprintw(ln,0, "Peripherals-RS");
855
                mvprintw(ln,40,"%-40s", "CPU State: ");
856
                {
857
                        unsigned int v = wb_read(CMD_REG);
858
                        mvprintw(ln,51, "");
859
                        if (v & 0x010000)
860
                                printw("EXT-INT ");
861
                        if ((v & 0x003000) == 0x03000)
862
                                printw("Halted ");
863
                        else if (v & 0x001000)
864
                                printw("Sleeping ");
865
                        else if (v & 0x002000)
866 76 dgisselq
                                printw("User Mod ");
867 34 dgisselq
                        if (v & 0x008000)
868
                                printw("Break-Enabled ");
869
                        if (v & 0x000080)
870
                                printw("PIC Enabled ");
871
                } ln++;
872 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
873
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
874
                showval(ln,40, "WBUS", m_state.m_p[2], false);
875
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
876 2 dgisselq
                ln++;
877 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
878
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
879
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
880
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
881 2 dgisselq
 
882
                ln++;
883 43 dgisselq
                if (!m_show_user_timers) {
884 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
885
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
886
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
887
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
888 43 dgisselq
                } else {
889 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
890
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
891
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
892
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
893 43 dgisselq
                }
894 2 dgisselq
 
895
                ln++;
896
                ln++;
897 76 dgisselq
                unsigned int cc = m_state.m_sR[14];
898 2 dgisselq
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
899
                        m_core->v__DOT__thecpu__DOT__gie);
900 34 dgisselq
                gie = (cc & 0x020);
901
                if (gie)
902 2 dgisselq
                        attroff(A_BOLD);
903
                else
904
                        attron(A_BOLD);
905
                mvprintw(ln, 0, "Supervisor Registers");
906
                ln++;
907
 
908 76 dgisselq
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
909
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
910
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
911
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
912 2 dgisselq
 
913 76 dgisselq
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
914
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
915
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
916
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
917 2 dgisselq
 
918 76 dgisselq
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
919
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
920
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
921
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
922 2 dgisselq
 
923 76 dgisselq
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
924
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
925 2 dgisselq
 
926 76 dgisselq
                if (true) {
927
                        mvprintw(ln,40, "%ssCC : 0x%08x",
928
                                (m_cursor==26)?">":" ", cc);
929
                } else {
930
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
931
                                (m_cursor==26)?">":" ",
932
                                (cc&0x01000)?"FE":"",
933
                                (cc&0x00800)?"DE":"",
934
                                (cc&0x00400)?"BE":"",
935
                                (cc&0x00200)?"TP":"",
936
                                (cc&0x00100)?"IL":"",
937
                                (cc&0x00080)?"BK":"",
938
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
939
                        mvprintw(ln, 54, "%s%s%s%s",
940
                                (cc&8)?"V":" ",
941
                                (cc&4)?"N":" ",
942
                                (cc&2)?"C":" ",
943
                                (cc&1)?"Z":" ");
944
                }
945 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
946 2 dgisselq
                ln++;
947
 
948 34 dgisselq
                if (gie)
949 2 dgisselq
                        attron(A_BOLD);
950
                else
951
                        attroff(A_BOLD);
952 69 dgisselq
                mvprintw(ln, 0, "User Registers");
953
                mvprintw(ln, 42, "DCDR=%02x %s",
954
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
955
                mvprintw(ln, 62, "OPR =%02x %s%s",
956
                        m_core->v__DOT__thecpu__DOT__opR,
957
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
958
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
959
                ln++;
960 76 dgisselq
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
961
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
962
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
963
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
964 2 dgisselq
 
965 76 dgisselq
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
966
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
967
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
968
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
969 2 dgisselq
 
970 76 dgisselq
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
971
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
972
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
973
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
974 2 dgisselq
 
975 76 dgisselq
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
976
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
977
                cc = m_state.m_uR[14];
978
                if (false) {
979
                        mvprintw(ln,40, "%cuCC : 0x%08x",
980
                                (m_cursor == 42)?'>':' ', cc);
981
                } else {
982
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
983
                                (m_cursor == 42)?'>':' ',
984
                                (cc & 0x1000)?"FE":"",
985
                                (cc & 0x0800)?"DE":"",
986
                                (cc & 0x0400)?"BE":"",
987
                                (cc & 0x0200)?"TP":"",
988
                                (cc & 0x0100)?"IL":"",
989
                                (cc & 0x0040)?"ST":"",
990
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
991
                        mvprintw(ln, 54, "%s%s%s%s",
992
                                (cc&8)?"V":" ",
993
                                (cc&4)?"N":" ",
994
                                (cc&2)?"C":" ",
995
                                (cc&1)?"Z":" ");
996
                }
997
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
998 2 dgisselq
 
999
                attroff(A_BOLD);
1000
                ln+=2;
1001
 
1002
                ln+=3;
1003
 
1004
                showins(ln, "I ",
1005 69 dgisselq
#ifdef  OPT_PIPELINED
1006 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
1007 69 dgisselq
#else
1008
                        1,
1009
#endif
1010 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
1011
                        m_core->v__DOT__thecpu__DOT__gie,
1012
                        0,
1013 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
1014
                        true); ln++;
1015 57 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
1016 2 dgisselq
 
1017
                showins(ln, "Dc",
1018 69 dgisselq
                        dcd_ce(), dcdvalid(),
1019 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
1020 69 dgisselq
#ifdef  OPT_PIPELINED
1021 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
1022 69 dgisselq
#else
1023
                        0,
1024
#endif
1025 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1026
#ifdef  OPT_VLIW
1027
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
1028
#else
1029
                        false
1030
#endif
1031
                        ); ln++;
1032 2 dgisselq
 
1033
                showins(ln, "Op",
1034 69 dgisselq
                        op_ce(),
1035 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
1036
                        m_core->v__DOT__thecpu__DOT__op_gie,
1037
                        m_core->v__DOT__thecpu__DOT__op_stall,
1038 76 dgisselq
                        op_pc(),
1039
#ifdef  OPT_VLIW
1040
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1041
#else
1042
                        false
1043
#endif
1044
                        ); ln++;
1045 2 dgisselq
 
1046 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
1047
                        showins(ln, "Mm",
1048
                                m_core->v__DOT__thecpu__DOT__mem_ce,
1049
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
1050
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1051 69 dgisselq
#ifdef  OPT_PIPELINED
1052 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
1053 69 dgisselq
#else
1054 148 dgisselq
                                0,
1055 69 dgisselq
#endif
1056 148 dgisselq
                                alu_pc(),
1057 76 dgisselq
#ifdef  OPT_VLIW
1058 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1059 76 dgisselq
#else
1060 148 dgisselq
                                false
1061 76 dgisselq
#endif
1062 148 dgisselq
                        );
1063
                } else {
1064
                        showins(ln, "Al",
1065
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1066
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1067
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1068
#ifdef  OPT_PIPELINED
1069
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1070
#else
1071
                                0,
1072
#endif
1073
                                alu_pc(),
1074
#ifdef  OPT_VLIW
1075
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1076
#else
1077
                                false
1078
#endif
1079
                        );
1080
                } ln++;
1081 2 dgisselq
        }
1082 69 dgisselq
 
1083 2 dgisselq
        void    tick(void) {
1084
                int gie = m_core->v__DOT__thecpu__DOT__gie;
1085
                /*
1086
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1087
                                                m_core->o_qspi_sck,
1088
                                                m_core->o_qspi_dat);
1089
                */
1090
 
1091 11 dgisselq
                int stb = m_core->o_wb_stb;
1092
                if ((m_core->o_wb_addr & (-1<<20))!=1)
1093
                        stb = 0;
1094
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
1095
                        m_core->i_wb_ack = 1;
1096 2 dgisselq
 
1097
                if ((dbg_flag)&&(dbg_fp)) {
1098 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1099 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1100
                                (m_core->i_dbg_stb)?"STB":
1101
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1102
                                ((m_core->i_dbg_we)?"WE":"  "),
1103
                                (m_core->i_dbg_addr),0,
1104
                                m_core->i_dbg_data,
1105
                                (m_core->o_dbg_ack)?"ACK":"   ",
1106
                                (m_core->o_dbg_stall)?"STALL":"     ",
1107
                                (m_core->o_dbg_data),
1108
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1109
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
1110 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
1111 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
1112
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1113 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
1114
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
1115 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
1116
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1117
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1118
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1119
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1120
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1121
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1122
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1123
                                (m_core->v__DOT__sys_addr),
1124
                                (m_core->v__DOT__dbg_addr),
1125
                                (m_core->v__DOT__sys_data),
1126
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1127
                                (m_core->v__DOT__wb_data));
1128
                }
1129
 
1130
                if (dbg_fp)
1131
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1132 69 dgisselq
                                dcd_ce(),
1133 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1134 69 dgisselq
                                op_ce(),
1135 39 dgisselq
                                op_pc(),
1136 69 dgisselq
                                dcdA()&0x01f,
1137 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opR,
1138
                                m_core->v__DOT__cmd_halt,
1139
                                m_core->v__DOT__cpu_halt,
1140
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1141
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1142
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1143
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1144
                                m_core->v__DOT__thecpu__DOT__ipc,
1145
                                m_core->v__DOT__thecpu__DOT__upc);
1146
 
1147
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1148
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1149 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1150 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1151
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1152
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1153
                                m_core->v__DOT__cmd_addr,
1154
                                m_core->v__DOT__dbg_idata,
1155
                                m_core->v__DOT__thecpu__DOT__master_ce,
1156
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1157
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1158
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1159
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1160
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1161
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1162
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1163
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
1164
                                m_core->v__DOT__cmd_addr,
1165
                                m_core->v__DOT__dbg_idata,
1166
                                m_core->v__DOT__thecpu__DOT__master_ce,
1167
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1168
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1169
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1170
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1171
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1172 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
1173
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1174 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
1175
                                m_core->v__DOT__thecpu__DOT__op_break);
1176 36 dgisselq
                } else if ((dbg_fp)&&
1177
                                ((m_core->v__DOT__thecpu__DOT__op_break)
1178 76 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1179 36 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1180
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1181 76 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1182 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1183
                                m_core->v__DOT__thecpu__DOT__break_en,
1184
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1185 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__op_break,
1186
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1187 2 dgisselq
                }
1188
 
1189 34 dgisselq
                if (dbg_fp) {
1190
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1191
                                fprintf(dbg_fp, "\tClear Pipeline\n");
1192
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1193
                                fprintf(dbg_fp, "\tNew PC\n");
1194
                }
1195
 
1196 36 dgisselq
                if (dbg_fp)
1197
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
1198
                if (false) {
1199
                        m_core->i_clk = 1;
1200
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1201
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1202
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1203
                        eval();
1204
                        m_core->i_clk = 0;
1205
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1206
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1207
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1208
                        eval();
1209
                        m_tickcount++;
1210
                } else {
1211
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1212
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1213
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1214 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
1215
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
1216
                                m_core->i_wb_err = 1;
1217
                        else
1218
                                m_core->i_wb_err = 0;
1219 36 dgisselq
                        TESTB<Vzipsystem>::tick();
1220
                }
1221 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
1222
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1223
                                (gie)?"User":"Supervisor",
1224
                                (gie)?"Supervisor":"User",
1225
                                m_core->v__DOT__thecpu__DOT__ipc,
1226
                                m_core->v__DOT__thecpu__DOT__upc,
1227
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1228
                } if (dbg_fp) {
1229 76 dgisselq
#ifdef  OPT_TRADITIONAL_PFCACHE
1230
                        fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1231 69 dgisselq
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1232
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1233 105 dgisselq
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
1234
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
1235 69 dgisselq
                                &&(dcdvalid())
1236
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1237
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1238
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
1239
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1240 76 dgisselq
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1241
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1242 69 dgisselq
#endif
1243
                        dbgins("Dc - ",
1244
                                dcd_ce(), dcdvalid(),
1245 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1246 69 dgisselq
#ifdef  OPT_PIPELINED
1247 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1248 69 dgisselq
#else
1249
                                0,
1250
#endif
1251 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1252
#ifdef  OPT_VLIW
1253
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1254
#else
1255
                                false,
1256
#endif
1257
#ifdef  OPT_ILLEGAL_INSTRUCTION
1258
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1259
#else
1260
                                false
1261
#endif
1262
                                );
1263 69 dgisselq
                        dbgins("Op - ",
1264
                                op_ce(),
1265 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1266
                                m_core->v__DOT__thecpu__DOT__op_gie,
1267
                                m_core->v__DOT__thecpu__DOT__op_stall,
1268 76 dgisselq
                                op_pc(),
1269
#ifdef  OPT_VLIW
1270
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1271
#else
1272
                                false,
1273 57 dgisselq
#endif
1274 76 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
1275
                                m_core->v__DOT__thecpu__DOT__op_illegal
1276
#else
1277
                                false
1278
#endif
1279
                                );
1280 2 dgisselq
                        dbgins("Al - ",
1281
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1282
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1283
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1284 69 dgisselq
#ifdef  OPT_PIPELINED
1285 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1286 69 dgisselq
#else
1287
                                0,
1288
#endif
1289 76 dgisselq
                                alu_pc(),
1290
#ifdef  OPT_VLIW
1291
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1292
#else
1293
                                false,
1294
#endif
1295
#ifdef  OPT_ILLEGAL_INSTRUCTION
1296
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1297
#else
1298
                                false
1299
#endif
1300
                                );
1301 2 dgisselq
 
1302
                }
1303 58 dgisselq
 
1304
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1305
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
1306
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1307
                        if (m_profile_fp) {
1308
                                unsigned buf[2];
1309
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
1310
                                buf[1] = iticks;
1311
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1312
                        }
1313
                        m_last_instruction_tickcount = m_tickcount;
1314
                }
1315 2 dgisselq
        }
1316
 
1317
        bool    test_success(void) {
1318
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1319
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1320
        }
1321
 
1322 39 dgisselq
        unsigned        op_pc(void) {
1323
                /*
1324
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1325
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1326
                        r--;
1327
                return r;
1328
                */
1329
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1330
        }
1331
 
1332 69 dgisselq
        bool    dcd_ce(void) {
1333
#ifdef  OPT_PIPELINED
1334
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1335
#else
1336
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1337
#endif
1338
        } bool  dcdvalid(void) {
1339
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1340
        }
1341
        bool    pfstall(void) {
1342
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1343
                        ||(m_core->v__DOT__cpu_stall));
1344
        }
1345
        unsigned        dcdR(void) {
1346
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1347
        }
1348
        unsigned        dcdA(void) {
1349
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1350
        }
1351
        unsigned        dcdB(void) {
1352
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1353
        }
1354
 
1355
        bool    op_ce(void) {
1356
#ifdef  OPT_PIPELINED
1357
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1358
#else
1359
                // return (dcdvalid())&&(opvalid())
1360
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1361
                return  dcdvalid();
1362
#endif
1363
        } bool  opvalid(void) {
1364
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1365
        }
1366
 
1367 58 dgisselq
        bool    mem_busy(void) {
1368
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1369 69 dgisselq
#ifdef  OPT_PIPELINED
1370 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1371 69 dgisselq
#else
1372
                return 0;
1373
#endif
1374 58 dgisselq
        }
1375
 
1376
        bool    mem_stalled(void) {
1377
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1378
 
1379
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1380
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1381
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
1382
 
1383 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1384
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1385
                a = mem_pipe_stalled();
1386 134 dgisselq
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
1387 69 dgisselq
#else
1388
                a = false;
1389
                b = false;
1390
#endif
1391 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1392
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1393 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1394 58 dgisselq
                        &&d);
1395
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1396
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1397
        }
1398
 
1399 39 dgisselq
        unsigned        alu_pc(void) {
1400
                /*
1401
                unsigned        r = op_pc();
1402
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1403
                        r--;
1404
                return r;
1405
                */
1406
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1407
        }
1408
 
1409
#ifdef  OPT_PIPELINED_BUS_ACCESS
1410 69 dgisselq
        bool    mem_pipe_stalled(void) {
1411 39 dgisselq
                int     r = 0;
1412
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1413
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1414
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1415
                        ||(
1416
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1417
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1418
                return r;
1419
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1420
        }
1421
#endif
1422
 
1423 2 dgisselq
        bool    test_failure(void) {
1424 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1425
                        return 0;
1426
                else if (m_core->v__DOT__thecpu__DOT__gie)
1427 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
1428 134 dgisselq
                else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
1429
                        return true; // ADD to PC instruction
1430
                else // MOV to PC instruction
1431 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1432 43 dgisselq
                /*
1433 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1434 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1435 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1436 43 dgisselq
                */
1437 2 dgisselq
        }
1438
 
1439
        void    wb_write(unsigned a, unsigned int v) {
1440 36 dgisselq
                int     errcount = 0;
1441 2 dgisselq
                mvprintw(0,35, "%40s", "");
1442
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1443
                m_core->i_dbg_cyc = 1;
1444
                m_core->i_dbg_stb = 1;
1445
                m_core->i_dbg_we  = 1;
1446
                m_core->i_dbg_addr = a & 1;
1447
                m_core->i_dbg_data = v;
1448
 
1449
                tick();
1450 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1451 2 dgisselq
                        tick();
1452
 
1453
                m_core->i_dbg_stb = 0;
1454 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1455 2 dgisselq
                        tick();
1456
 
1457
                // Release the bus
1458
                m_core->i_dbg_cyc = 0;
1459
                m_core->i_dbg_stb = 0;
1460
                tick();
1461
                mvprintw(0,35, "%40s", "");
1462
                mvprintw(0,40, "wb_write -- complete");
1463 36 dgisselq
 
1464
 
1465
                if (errcount >= 100)
1466
                        bomb = true;
1467 2 dgisselq
        }
1468
 
1469
        unsigned long   wb_read(unsigned a) {
1470
                unsigned int    v;
1471 36 dgisselq
                int     errcount = 0;
1472 2 dgisselq
                mvprintw(0,35, "%40s", "");
1473
                mvprintw(0,40, "wb_read(0x%08x)", a);
1474
                m_core->i_dbg_cyc = 1;
1475
                m_core->i_dbg_stb = 1;
1476
                m_core->i_dbg_we  = 0;
1477
                m_core->i_dbg_addr = a & 1;
1478
 
1479
                tick();
1480 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1481 2 dgisselq
                        tick();
1482
 
1483
                m_core->i_dbg_stb = 0;
1484 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1485 2 dgisselq
                        tick();
1486
                v = m_core->o_dbg_data;
1487
 
1488
                // Release the bus
1489
                m_core->i_dbg_cyc = 0;
1490
                m_core->i_dbg_stb = 0;
1491
                tick();
1492
 
1493
                mvprintw(0,35, "%40s", "");
1494
                mvprintw(0,40, "wb_read = 0x%08x", v);
1495
 
1496 36 dgisselq
                if (errcount >= 100)
1497
                        bomb = true;
1498 2 dgisselq
                return v;
1499
        }
1500
 
1501 34 dgisselq
        void    cursor_up(void) {
1502
                if (m_cursor > 3)
1503
                        m_cursor -= 4;
1504
        } void  cursor_down(void) {
1505
                if (m_cursor < 40)
1506
                        m_cursor += 4;
1507
        } void  cursor_left(void) {
1508
                if (m_cursor > 0)
1509
                        m_cursor--;
1510
                else    m_cursor = 43;
1511
        } void  cursor_right(void) {
1512
                if (m_cursor < 43)
1513
                        m_cursor++;
1514
                else    m_cursor = 0;
1515
        }
1516
 
1517
        int     cursor(void) { return m_cursor; }
1518 2 dgisselq
};
1519
 
1520 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1521
        int     wy, wx, ra;
1522
        int     c = tb->cursor();
1523
 
1524
        wx = (c & 0x03) * 20 + 9;
1525
        wy = (c>>2);
1526
        if (wy >= 3+4)
1527
                wy++;
1528
        if (wy > 3)
1529
                wy += 2;
1530
        wy++;
1531
 
1532
        if (c >= 12)
1533
                ra = c - 12;
1534
        else
1535
                ra = c + 32;
1536
 
1537
        bool    done = false;
1538
        char    str[16];
1539
        int     pos = 0; str[pos] = '\0';
1540
        while(!done) {
1541
                int     chv = getch();
1542
                switch(chv) {
1543
                case KEY_ESCAPE:
1544
                        pos = 0; str[pos] = '\0'; done = true;
1545
                        break;
1546
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1547
                        done = true;
1548
                        break;
1549
                case KEY_LEFT: case KEY_BACKSPACE:
1550
                        if (pos > 0) pos--;
1551
                        break;
1552 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1553 34 dgisselq
                case KEY_CLEAR:
1554
                        pos = 0;
1555
                        break;
1556
                case '0': case ' ': str[pos++] = '0'; break;
1557
                case '1': str[pos++] = '1'; break;
1558
                case '2': str[pos++] = '2'; break;
1559
                case '3': str[pos++] = '3'; break;
1560
                case '4': str[pos++] = '4'; break;
1561
                case '5': str[pos++] = '5'; break;
1562
                case '6': str[pos++] = '6'; break;
1563
                case '7': str[pos++] = '7'; break;
1564
                case '8': str[pos++] = '8'; break;
1565
                case '9': str[pos++] = '9'; break;
1566
                case 'A': case 'a': str[pos++] = 'A'; break;
1567
                case 'B': case 'b': str[pos++] = 'B'; break;
1568
                case 'C': case 'c': str[pos++] = 'C'; break;
1569
                case 'D': case 'd': str[pos++] = 'D'; break;
1570
                case 'E': case 'e': str[pos++] = 'E'; break;
1571
                case 'F': case 'f': str[pos++] = 'F'; break;
1572
                }
1573
 
1574
                if (pos > 8)
1575
                        pos = 8;
1576
                str[pos] = '\0';
1577
 
1578
                attron(A_NORMAL | A_UNDERLINE);
1579
                mvprintw(wy, wx, "%-8s", str);
1580
                if (pos > 0) {
1581
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1582
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1583
                }
1584
                attrset(A_NORMAL);
1585
        }
1586
 
1587
        if (pos > 0) {
1588
                int     v;
1589
                v = strtoul(str, NULL, 16);
1590
                if (!tb->halted()) {
1591
                        switch(ra) {
1592
                        case 15:
1593
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1594
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1595
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1596
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1597
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1598
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1599 69 dgisselq
#ifdef  OPT_PIPELINED
1600 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1601 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1602
#endif
1603 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1604
                                }
1605
                                break;
1606
                        case 31:
1607
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1608
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1609
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1610
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1611
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1612
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1613 69 dgisselq
#ifdef  OPT_PIPELINED
1614 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1615 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1616
#endif
1617 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1618
                                }
1619
                                break;
1620
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1621
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1622 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1623 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1624 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1625
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1626
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1627
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1628
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1629
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1630
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1631
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1632
                        default:
1633
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1634
                                break;
1635
                        }
1636
                } else
1637
                        tb->cmd_write(ra, v);
1638
        }
1639
}
1640
 
1641 27 dgisselq
void    usage(void) {
1642
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1643
        printf("\n");
1644
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1645 148 dgisselq
        printf("\tThis file needs to be in a raw format and not an ELF\n");
1646
        printf("\texecutable.  It will be inserted into memory at a memory\n");
1647
        printf("\taddress of 0x0100000.  The memory device itself, the only\n");
1648
        printf("\tdevice supported by this simulator, occupies addresses from\n");
1649
        printf("\t0x0100000 to 0x01fffff.\n");
1650
        printf("\n");
1651 27 dgisselq
        printf("\t-a\tSets the testbench to run automatically without any\n");
1652
        printf("\t\tuser interaction.\n");
1653
        printf("\n");
1654
        printf("\tUser Commands:\n");
1655
        printf("\t\tWhen the test bench is run interactively, the following\n");
1656
        printf("\t\tkey strokes are recognized:\n");
1657
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1658
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1659
        printf("\t\t\tuser intervention.\n");
1660
        printf("\t\t\'q\'\tQuit the simulation.\n");
1661
        printf("\t\t\'r\'\tReset the processor.\n");
1662
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1663
        printf("\t\t\tThis may consume more than one tick.\n");
1664
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1665
}
1666 2 dgisselq
 
1667 43 dgisselq
bool    signalled = false;
1668
 
1669
void    sigint(int v) {
1670
        signalled = true;
1671
}
1672
 
1673 2 dgisselq
int     main(int argc, char **argv) {
1674
        Verilated::commandArgs(argc, argv);
1675
        ZIPPY_TB        *tb = new ZIPPY_TB();
1676 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1677 2 dgisselq
 
1678
        // mem[0x00000] = 0xbe000010; // Halt instruction
1679
        unsigned int mptr = 0;
1680
 
1681 43 dgisselq
        signal(SIGINT, sigint);
1682
 
1683 9 dgisselq
        if (argc <= 1) {
1684 27 dgisselq
                usage();
1685
                exit(-1);
1686 9 dgisselq
        } else {
1687
                for(int argn=1; argn<argc; argn++) {
1688 27 dgisselq
                        if (argv[argn][0] == '-') {
1689
                                switch(argv[argn][1]) {
1690
                                case 'a':
1691
                                        autorun = true;
1692
                                        break;
1693
                                case 'e':
1694
                                        exit_on_done = true;
1695
                                        break;
1696
                                case 'h':
1697
                                        usage();
1698
                                        exit(0);
1699
                                        break;
1700 36 dgisselq
                                case 's':
1701
                                        autostep = true;
1702
                                        break;
1703 27 dgisselq
                                default:
1704
                                        usage();
1705
                                        exit(-1);
1706
                                        break;
1707
                                }
1708
                        } else if (access(argv[argn], R_OK)==0) {
1709 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1710 58 dgisselq
                                int     nr, nv = 0;
1711 9 dgisselq
                                if (fp == NULL) {
1712
                                        printf("Cannot open %s\n", argv[argn]);
1713
                                        perror("O/S Err: ");
1714
                                        exit(-1);
1715 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1716 9 dgisselq
                                fclose(fp);
1717 58 dgisselq
                                mptr+= nr;
1718
                                if (nr == 0) {
1719
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
1720
                                        perror("O/S  Err?:");
1721
                                        exit(-2);
1722
                                } for(int i=0; i<nr; i++) {
1723
                                        if (tb->m_mem[mptr-nr+i])
1724
                                                nv++;
1725
                                } if (nv == 0) {
1726
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
1727
                                        perror("O/S  Err?:");
1728
                                        exit(-2);
1729
                                }
1730
                        } else {
1731
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1732
                                exit(-2);
1733 9 dgisselq
                        }
1734
                }
1735
        }
1736
 
1737 58 dgisselq
 
1738
        assert(mptr > 0);
1739
 
1740 27 dgisselq
        if (autorun) {
1741
                bool    done = false;
1742 2 dgisselq
 
1743 27 dgisselq
                printf("Running in non-interactive mode\n");
1744
                tb->reset();
1745
                for(int i=0; i<2; i++)
1746
                        tb->tick();
1747
                tb->m_core->v__DOT__cmd_halt = 0;
1748
                while(!done) {
1749
                        tb->tick();
1750
 
1751
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1752
                                // tb->m_core->v__DOT__cmd_halt = 0;
1753
                                // tb->m_core->v__DOT__cmd_step = 0;
1754
 
1755 34 dgisselq
                        /*
1756 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1757
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1758
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1759
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1760 34 dgisselq
                        */
1761 27 dgisselq
 
1762
                        done = (tb->test_success())||(tb->test_failure());
1763 43 dgisselq
                        done = done || signalled;
1764 27 dgisselq
                }
1765 36 dgisselq
        } else if (autostep) {
1766
                bool    done = false;
1767
 
1768
                printf("Running in non-interactive mode, via step commands\n");
1769
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1770
                while(!done) {
1771
                        tb->wb_write(CMD_REG, CMD_STEP);
1772
                        done = (tb->test_success())||(tb->test_failure());
1773 43 dgisselq
                        done = done || signalled;
1774 36 dgisselq
                }
1775 27 dgisselq
        } else { // Interactive
1776
                initscr();
1777
                raw();
1778
                noecho();
1779
                keypad(stdscr, true);
1780
 
1781 69 dgisselq
                // tb->reset();
1782
                // for(int i=0; i<2; i++)
1783
                        // tb->tick();
1784
                tb->m_core->v__DOT__cmd_reset = 1;
1785 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
1786
 
1787 76 dgisselq
                /*
1788
                // For debugging purposes: do we wish to skip some number of
1789
                // instructions to fast forward to a time of interest??
1790
                for(int i=0; i<0x4d0; i++) {
1791
                        tb->m_core->v__DOT__cmd_halt = 0;
1792
                        tb->tick();
1793
                }
1794
                */
1795
 
1796 27 dgisselq
                int     chv = 'q';
1797
 
1798 43 dgisselq
                bool    done = false, halted = true, manual = true,
1799
                        high_speed = false;
1800 2 dgisselq
 
1801
                halfdelay(1);
1802 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1803 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1804
                        // tb->show_state();
1805
 
1806
                while(!done) {
1807 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1808 87 dgisselq
                                // chv = getch();
1809
 
1810 43 dgisselq
                                struct  pollfd  fds[1];
1811
                                fds[0].fd = STDIN_FILENO;
1812
                                fds[0].events = POLLIN;
1813 87 dgisselq
 
1814 43 dgisselq
                                if (poll(fds, 1, 0) > 0)
1815
                                        chv = getch();
1816
                                else
1817
                                        chv = ERR;
1818 87 dgisselq
 
1819 43 dgisselq
                        } else {
1820
                                chv = getch();
1821
                        }
1822 2 dgisselq
                        switch(chv) {
1823
                        case 'h': case 'H':
1824
                                tb->wb_write(CMD_REG, CMD_HALT);
1825
                                if (!halted)
1826
                                        erase();
1827
                                halted = true;
1828
                                break;
1829 43 dgisselq
                        case 'G':
1830
                                high_speed = true;
1831 87 dgisselq
                                // cbreak();
1832 43 dgisselq
                        case 'g':
1833 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1834
                                if (halted)
1835
                                        erase();
1836
                                halted = false;
1837
                                manual = false;
1838
                                break;
1839 43 dgisselq
                        case 'm':
1840
                                tb->show_user_timers(false);
1841
                                break;
1842 2 dgisselq
                        case 'q': case 'Q':
1843
                                done = true;
1844
                                break;
1845
                        case 'r': case 'R':
1846 36 dgisselq
                                if (manual)
1847
                                        tb->reset();
1848
                                else
1849
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1850 2 dgisselq
                                halted = true;
1851
                                erase();
1852
                                break;
1853 39 dgisselq
                        case 's':
1854 34 dgisselq
                                if (!halted)
1855 27 dgisselq
                                        erase();
1856 76 dgisselq
                                tb->step();
1857 2 dgisselq
                                manual = false;
1858 34 dgisselq
                                halted = true;
1859 87 dgisselq
                                // if (high_speed)
1860
                                        // halfdelay(1);
1861 43 dgisselq
                                high_speed = false;
1862 2 dgisselq
                                break;
1863 39 dgisselq
                        case 'S':
1864 34 dgisselq
                                if ((!manual)||(halted))
1865 27 dgisselq
                                        erase();
1866 2 dgisselq
                                manual = true;
1867 39 dgisselq
                                halted = true;
1868 87 dgisselq
                                // if (high_speed)
1869
                                        // halfdelay(1);
1870 43 dgisselq
                                high_speed = false;
1871 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1872
                                tb->m_core->v__DOT__cmd_step = 1;
1873
                                tb->eval();
1874
                                tb->tick();
1875
                                break;
1876
                        case 'T': // 
1877
                                if ((!manual)||(halted))
1878
                                        erase();
1879
                                manual = true;
1880
                                halted = true;
1881 87 dgisselq
                                // if (high_speed)
1882
                                        // halfdelay(1);
1883 43 dgisselq
                                high_speed = false;
1884 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1885
                                tb->m_core->v__DOT__cmd_step = 0;
1886
                                tb->eval();
1887
                                tb->tick();
1888
                                break;
1889
                        case 't':
1890
                                if ((!manual)||(halted))
1891
                                        erase();
1892
                                manual = true;
1893 34 dgisselq
                                halted = false;
1894 87 dgisselq
                                // if (high_speed)
1895
                                        // halfdelay(1);
1896 43 dgisselq
                                high_speed = false;
1897 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1898 76 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1899 27 dgisselq
                //              tb->m_core->v__DOT__cmd_step = 0;
1900 2 dgisselq
                                tb->tick();
1901
                                break;
1902 43 dgisselq
                        case 'u':
1903
                                tb->show_user_timers(true);
1904
                                break;
1905 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1906
                                get_value(tb);
1907
                                break;
1908
                        case    KEY_UP:         tb->cursor_up();        break;
1909
                        case    KEY_DOWN:       tb->cursor_down();      break;
1910
                        case    KEY_LEFT:       tb->cursor_left();      break;
1911
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1912 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1913 34 dgisselq
                        case ERR: case KEY_CLEAR:
1914 2 dgisselq
                        default:
1915
                                if (!manual)
1916
                                        tb->tick();
1917
                        }
1918
 
1919
                        if (manual) {
1920
                                tb->show_state();
1921
                        } else if (halted) {
1922
                                if (tb->dbg_fp)
1923
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1924
                                tb->read_state();
1925
                        } else
1926
                                tb->show_state();
1927
 
1928
                        if (tb->m_core->i_rst)
1929
                                done =true;
1930 43 dgisselq
                        if ((tb->bomb)||(signalled))
1931 2 dgisselq
                                done = true;
1932 27 dgisselq
 
1933
                        if (exit_on_done) {
1934
                                if (tb->test_success())
1935
                                        done = true;
1936
                                if (tb->test_failure())
1937
                                        done = true;
1938
                        }
1939 2 dgisselq
                }
1940 27 dgisselq
                endwin();
1941
        }
1942
#ifdef  MANUAL_STEPPING_MODE
1943
         else { // Manual stepping mode
1944 2 dgisselq
                tb->show_state();
1945
 
1946
                while('q' != tolower(chv = getch())) {
1947
                        tb->tick();
1948
                        tb->show_state();
1949
 
1950
                        if (tb->test_success())
1951
                                break;
1952
                        else if (tb->test_failure())
1953
                                break;
1954 43 dgisselq
                        else if (signalled)
1955
                                break;
1956 2 dgisselq
                }
1957
        }
1958 27 dgisselq
#endif
1959 2 dgisselq
 
1960 43 dgisselq
        printf("\n");
1961 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1962
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1963 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1964 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1965
                printf("Instructions / Clock: %.2f\n",
1966
                        (double)tb->m_core->v__DOT__mic_data
1967
                        / (double)tb->m_core->v__DOT__mtc_data);
1968 36 dgisselq
 
1969
        int     rcode = 0;
1970
        if (tb->bomb) {
1971
                printf("TEST BOMBED\n");
1972
                rcode = -1;
1973
        } else if (tb->test_success()) {
1974 2 dgisselq
                printf("SUCCESS!\n");
1975 36 dgisselq
        } else if (tb->test_failure()) {
1976
                rcode = -2;
1977 2 dgisselq
                printf("TEST FAILED!\n");
1978 36 dgisselq
        } else
1979 27 dgisselq
                printf("User quit\n");
1980 43 dgisselq
        delete tb;
1981 36 dgisselq
        exit(rcode);
1982 2 dgisselq
}
1983
 

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