OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 155

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 155 dgisselq
#include <sys/types.h>
42
#include <sys/stat.h>
43
#include <fcntl.h>
44 2 dgisselq
 
45
#include <ctype.h>
46
#include <ncurses.h>
47
 
48
#include "verilated.h"
49
#include "Vzipsystem.h"
50 39 dgisselq
#include "cpudefs.h"
51 2 dgisselq
 
52
#include "testb.h"
53
// #include "twoc.h"
54
// #include "qspiflashsim.h"
55
#include "memsim.h"
56
#include "zopcodes.h"
57
#include "zparser.h"
58
 
59
#define CMD_REG         0
60
#define CMD_DATA        1
61 155 dgisselq
#define CMD_GIE         (1<<13)
62
#define CMD_SLEEP       (1<<12)
63
#define CMD_CLEAR_CACHE (1<<11)
64 2 dgisselq
#define CMD_HALT        (1<<10)
65
#define CMD_STALL       (1<<9)
66
#define CMD_INT         (1<<7)
67
#define CMD_RESET       (1<<6)
68 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
69 2 dgisselq
 
70 34 dgisselq
#define KEY_ESCAPE      27
71
#define KEY_RETURN      10
72 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
73 2 dgisselq
 
74 57 dgisselq
#define MAXERR          10000
75
 
76 155 dgisselq
#define LGRAMLEN        20
77
#define RAMBASE         0x100000
78
#define MEMWORDS        (1<<LGRAMLEN)
79 76 dgisselq
 
80
class   SPARSEMEM {
81
public:
82
        bool    m_valid;
83
        unsigned int    m_a, m_d;
84
};
85
 
86
class   ZIPSTATE {
87
public:
88
        bool            m_valid, m_gie, m_last_pc_valid;
89
        unsigned int    m_sR[16], m_uR[16];
90
        unsigned int    m_p[20];
91
        unsigned int    m_last_pc, m_pc, m_sp;
92 148 dgisselq
        SPARSEMEM       m_smem[5]; // Nearby stack memory
93
        SPARSEMEM       m_imem[5]; // Nearby instruction memory
94 76 dgisselq
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
95
 
96
        void    step(void) {
97
                m_last_pc_valid = true;
98
                m_last_pc = m_pc;
99
        }
100
};
101
 
102
 
103 2 dgisselq
// No particular "parameters" need definition or redefinition here.
104
class   ZIPPY_TB : public TESTB<Vzipsystem> {
105
public:
106 9 dgisselq
        unsigned long   m_mem_size;
107 2 dgisselq
        MEMSIM          m_mem;
108
        // QSPIFLASHSIM m_flash;
109 155 dgisselq
        FILE            *m_dbgfp, *m_profile_fp;
110 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
111 34 dgisselq
        int             m_cursor;
112 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
113 76 dgisselq
        ZIPSTATE        m_state;
114 2 dgisselq
 
115 155 dgisselq
        ZIPPY_TB(void) : m_mem_size(MEMWORDS), m_mem(m_mem_size) {
116 76 dgisselq
                if (false) {
117 155 dgisselq
                        m_dbgfp = fopen("dbg.txt", "w");
118 36 dgisselq
                        dbg_flag = true;
119
                } else {
120 155 dgisselq
                        m_dbgfp = NULL;
121 36 dgisselq
                        dbg_flag = false;
122
                }
123 2 dgisselq
                bomb = false;
124 34 dgisselq
                m_cursor = 0;
125 43 dgisselq
                m_show_user_timers = false;
126 58 dgisselq
 
127
                m_last_instruction_tickcount = 0l;
128
                if (true) {
129
                        m_profile_fp = fopen("pfile.bin","wb");
130
                } else {
131
                        m_profile_fp = NULL;
132
                }
133 2 dgisselq
        }
134
 
135 69 dgisselq
        ~ZIPPY_TB(void) {
136 155 dgisselq
                if (m_dbgfp)
137
                        fclose(m_dbgfp);
138 69 dgisselq
                if (m_profile_fp)
139
                        fclose(m_profile_fp);
140
        }
141
 
142 2 dgisselq
        void    reset(void) {
143
                // m_flash.debug(false);
144
                TESTB<Vzipsystem>::reset();
145
        }
146
 
147
        bool    on_tick(void) {
148
                tick();
149
                return true;
150
        }
151
 
152 76 dgisselq
        void    step(void) {
153
                wb_write(CMD_REG, CMD_STEP);
154
                m_state.step();
155
        }
156
 
157
        void    read_raw_state(void) {
158
                m_state.m_valid = false;
159
                for(int i=0; i<16; i++)
160
                        m_state.m_sR[i] = cmd_read(i);
161
                for(int i=0; i<16; i++)
162
                        m_state.m_uR[i] = cmd_read(i+16);
163
                for(int i=0; i<20; i++)
164
                        m_state.m_p[i]  = cmd_read(i+32);
165
 
166 155 dgisselq
                m_state.m_gie = wb_read(CMD_REG) & CMD_GIE;
167 76 dgisselq
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
168
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
169
 
170
                if (m_state.m_last_pc_valid)
171
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
172
                else
173
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
174
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
175
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
176
                m_state.m_imem[1].m_a = m_state.m_pc;
177
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
178
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
179
 
180
                for(int i=1; i<4; i++) {
181
                        if (!m_state.m_imem[i].m_valid) {
182
                                m_state.m_imem[i+1].m_valid = false;
183
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
184
                                continue;
185
                        }
186
                        m_state.m_imem[i+1].m_a = zop_early_branch(
187
                                        m_state.m_imem[i].m_a,
188
                                        m_state.m_imem[i].m_d);
189
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
190
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
191
                }
192
 
193
                m_state.m_smem[0].m_a = m_state.m_sp;
194
                for(int i=1; i<5; i++)
195
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
196
                for(int i=0; i<5; i++) {
197
                        m_state.m_smem[i].m_valid =
198
                                (m_state.m_imem[i].m_a > 0x10000);
199
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
200
                }
201
                m_state.m_valid = true;
202
        }
203
 
204
        void    read_raw_state_cheating(void) {
205
                m_state.m_valid = false;
206
                for(int i=0; i<16; i++)
207
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
208
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
209
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
210
                for(int i=0; i<16; i++)
211
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
212
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
213
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
214
 
215 155 dgisselq
                m_state.m_gie = m_core->v__DOT__thecpu__DOT__gie;
216 76 dgisselq
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
217
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
218
 
219
                m_state.m_p[0] = m_core->v__DOT__pic_data;
220
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
221
                if (!m_show_user_timers) {
222
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
223
                } else {
224
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
225
                }
226
 
227
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
228
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
229
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
230
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
231
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
232
 
233
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
234
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
235
                m_state.m_p[10] = m_core->v__DOT__upc_data;
236
                m_state.m_p[11] = m_core->v__DOT__uic_data;
237
 
238
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
239
                m_state.m_p[13] = m_core->v__DOT__moc_data;
240
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
241
                m_state.m_p[15] = m_core->v__DOT__mic_data;
242
 
243
        }
244
 
245 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
246
                if (c)
247
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
248
                else
249
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
250 2 dgisselq
        }
251
 
252 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
253 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
254 34 dgisselq
                if (c)
255
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
256
                else
257
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
258 2 dgisselq
        }
259
 
260 155 dgisselq
        void    dbgreg(FILE *fp, int id, const char *n, unsigned int v) {
261
                /*
262
                if ((id == 14)||(id == 14+16)) {
263
                        //char  buf[64];
264
                        //fprintf(fp, " %s:",
265
                        fprintf(fp, " %s: 0x%08x ", n, v);
266
                } else
267
                */
268
                        fprintf(fp, " %s: 0x%08x ", n, v);
269
        }
270
 
271 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
272 76 dgisselq
                if (r < 16)
273
                        dispreg(y, x, n, m_state.m_sR[r], c);
274 34 dgisselq
                else
275 76 dgisselq
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
276
                move(y,x+17);
277
 
278 69 dgisselq
#ifdef  OPT_PIPELINED
279 76 dgisselq
                addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
280 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
281 34 dgisselq
                        ?'a':((c)?'<':' '));
282 76 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
283 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
284 76 dgisselq
                        ?'b':' ');
285 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
286
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
287 76 dgisselq
                        ?'W':' ');
288
#else
289
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
290
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
291 34 dgisselq
                        ?'W':((c)?'<':' '));
292 76 dgisselq
#endif
293 2 dgisselq
        }
294
 
295
        void    showins(int y, const char *lbl, const int ce, const int valid,
296 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
297
                        const bool phase) {
298
                char    la[80], lb[80];
299 2 dgisselq
 
300
                if (ce)
301
                        mvprintw(y, 0, "Ck ");
302
                else
303
                        mvprintw(y, 0, "   ");
304
                if (stall)
305
                        printw("Stl ");
306
                else
307
                        printw("    ");
308
                printw("%s: 0x%08x", lbl, pc);
309
 
310
                if (valid) {
311
                        if (gie) attroff(A_BOLD);
312
                        else    attron(A_BOLD);
313 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
314
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
315
                                printw("  %-24s", la);
316
                        else
317
                                printw("  %-24s", lb);
318 2 dgisselq
                } else {
319
                        attroff(A_BOLD);
320
                        printw("  (0x%08x)%28s", m_mem[pc],"");
321
                }
322
                attroff(A_BOLD);
323
        }
324
 
325
        void    dbgins(const char *lbl, const int ce, const int valid,
326 76 dgisselq
                        const int gie, const int stall, const unsigned int pc,
327
                        const bool phase, const bool illegal) {
328
                char    la[80], lb[80];
329 2 dgisselq
 
330 155 dgisselq
                if (!m_dbgfp)
331 2 dgisselq
                        return;
332
 
333
                if (ce)
334 155 dgisselq
                        fprintf(m_dbgfp, "%s Ck ", lbl);
335 2 dgisselq
                else
336 155 dgisselq
                        fprintf(m_dbgfp, "%s    ", lbl);
337 2 dgisselq
                if (stall)
338 155 dgisselq
                        fprintf(m_dbgfp, "Stl ");
339 2 dgisselq
                else
340 155 dgisselq
                        fprintf(m_dbgfp, "    ");
341
                fprintf(m_dbgfp, "0x%08x:  ", pc);
342 2 dgisselq
 
343
                if (valid) {
344 76 dgisselq
                        zipi_to_string(m_mem[pc], la, lb);
345
                        if ((phase)||((m_mem[pc]&0x80000000)==0))
346 155 dgisselq
                                fprintf(m_dbgfp, "  %-24s", la);
347 76 dgisselq
                        else
348 155 dgisselq
                                fprintf(m_dbgfp, "  %-24s", lb);
349 2 dgisselq
                } else {
350 155 dgisselq
                        fprintf(m_dbgfp, "  (0x%08x)", m_mem[pc]);
351 76 dgisselq
                } if (illegal)
352 155 dgisselq
                        fprintf(m_dbgfp, " (Illegal)");
353
                fprintf(m_dbgfp, "\n");
354 2 dgisselq
        }
355
 
356
        void    show_state(void) {
357
                int     ln= 0;
358
 
359 76 dgisselq
                read_raw_state_cheating();
360
 
361 2 dgisselq
                mvprintw(ln,0, "Peripherals-SS"); ln++;
362 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
363 36 dgisselq
                printw(" %s",
364
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
365
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
366
                        );
367 39 dgisselq
#endif
368
 
369
#ifdef  OPT_EARLY_BRANCHING
370 69 dgisselq
                printw(" %s",
371 105 dgisselq
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":"  ");
372
                if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
373
                        printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
374
                else    printw(" %10s", "");
375
                printw(" %s",
376
                        (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":"     ");
377 39 dgisselq
#endif
378 36 dgisselq
 
379
                /*
380 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
381
                        mvprintw(ln, 17, "%s%s",
382
                                ((m_core->v__DOT__sys_cyc)
383
                                &&(m_core->v__DOT__sys_we)
384
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
385
                                (m_core->v__DOT__trap_int)?"I":" ");
386
                */
387 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
388
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
389 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
390 57 dgisselq
 
391
                if (!m_show_user_timers) {
392
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
393
                } else {
394
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
395
                }
396
 
397 76 dgisselq
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
398 2 dgisselq
 
399
                ln++;
400 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
401
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
402
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
403
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
404 2 dgisselq
 
405 43 dgisselq
 
406
                if (!m_show_user_timers) {
407
                        ln++;
408 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
409
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
410
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
411
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
412 43 dgisselq
                } else {
413
                        ln++;
414 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
415
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
416
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
417
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
418 43 dgisselq
                }
419 2 dgisselq
 
420
                ln++;
421
                mvprintw(ln, 40, "%s %s",
422
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
423
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
424 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
425 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
426
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
427
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
428 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
429
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
430
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
431 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
432
                        attroff(A_BOLD);
433
                else
434
                        attron(A_BOLD);
435
                mvprintw(ln, 0, "Supervisor Registers");
436
                ln++;
437
 
438 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
439
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
440
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
441
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
442 2 dgisselq
 
443 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
444
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
445
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
446
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
447 2 dgisselq
 
448 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
449
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
450
                showreg(ln,40, "sR10", 10, (m_cursor==22));
451
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
452 2 dgisselq
 
453 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
454
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
455 76 dgisselq
 
456
                unsigned int cc = m_state.m_sR[14];
457 134 dgisselq
                if (false) {
458 76 dgisselq
                        mvprintw(ln,40, "%ssCC : 0x%08x",
459
                                (m_cursor==26)?">":" ", cc);
460
                } else {
461
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
462
                                (m_cursor==26)?">":" ",
463
                                (cc&0x01000)?"FE":"",
464
                                (cc&0x00800)?"DE":"",
465
                                (cc&0x00400)?"BE":"",
466
                                (cc&0x00200)?"TP":"",
467
                                (cc&0x00100)?"IL":"",
468
                                (cc&0x00080)?"BK":"",
469
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
470
                        mvprintw(ln, 54, "%s%s%s%s",
471
                                (cc&8)?"V":" ",
472
                                (cc&4)?"N":" ",
473
                                (cc&2)?"C":" ",
474
                                (cc&1)?"Z":" ");
475
                }
476
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
477 69 dgisselq
                mvprintw(ln,60,"%s",
478
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
479
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
480
                                ?"V"
481
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
482
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
483
                        :" "));
484 2 dgisselq
                ln++;
485
 
486
                if (m_core->v__DOT__thecpu__DOT__gie)
487
                        attron(A_BOLD);
488
                else
489
                        attroff(A_BOLD);
490 69 dgisselq
                mvprintw(ln, 0, "User Registers");
491
                mvprintw(ln, 42, "DCDR=%02x %s%s",
492
                        dcdR(),
493
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
494
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
495
                mvprintw(ln, 62, "OPR =%02x %s%s",
496
                        m_core->v__DOT__thecpu__DOT__opR,
497
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
498
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
499
                ln++;
500 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
501
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
502
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
503
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
504 2 dgisselq
 
505 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
506
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
507
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
508
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
509 2 dgisselq
 
510 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
511
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
512
                showreg(ln,40, "uR10", 26, (m_cursor==38));
513
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
514 2 dgisselq
 
515 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
516
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
517 76 dgisselq
                cc = m_state.m_uR[14];
518
                if (false) {
519
                        mvprintw(ln,40, "%cuCC : 0x%08x",
520
                                (m_cursor == 42)?'>':' ', cc);
521
                } else {
522
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
523
                                (m_cursor == 42)?'>':' ',
524
                                (cc & 0x1000)?"FE":"",
525
                                (cc & 0x0800)?"DE":"",
526
                                (cc & 0x0400)?"BE":"",
527
                                (cc & 0x0200)?"TP":"",
528
                                (cc & 0x0100)?"IL":"",
529
                                (cc & 0x0040)?"ST":"",
530
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
531
                        mvprintw(ln, 54, "%s%s%s%s",
532
                                (cc&8)?"V":" ",
533
                                (cc&4)?"N":" ",
534
                                (cc&2)?"C":" ",
535
                                (cc&1)?"Z":" ");
536
                }
537
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
538 69 dgisselq
                mvprintw(ln,60,"%s",
539
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
540
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
541
                                ?"V"
542
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
543
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
544
                        :" "));
545 2 dgisselq
 
546
                attroff(A_BOLD);
547
                ln+=1;
548
 
549 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
550 69 dgisselq
                ln++;
551
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
552
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
553
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
554
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
555
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
556
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
557
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
558
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
559
                        (m_core->v__DOT__wb_data)); ln++;
560 39 dgisselq
#else
561 69 dgisselq
 
562 76 dgisselq
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
563 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
564
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
565 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
566 69 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
567
                        m_core->v__DOT__thecpu__DOT__pf_pc,
568
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
569
 
570 2 dgisselq
                ln++;
571
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
572
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
573
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
574
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
575
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
576
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
577
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
578 69 dgisselq
                        (pfstall())?"STL":"   ",
579 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
580 39 dgisselq
#endif
581 2 dgisselq
 
582
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
583 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
584
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
585
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
586
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
587 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
588
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
589
                        (m_core->v__DOT__thecpu__DOT__mem_data),
590
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
591 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
592 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
593
// #define      OPT_PIPELINED_BUS_ACCESS
594
#ifdef  OPT_PIPELINED_BUS_ACCESS
595
                printw(" %x%x%c%c",
596
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
597
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
598 134 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
599 39 dgisselq
                        (mem_pipe_stalled())?'S':'-'); ln++;
600
#else
601
                ln++;
602
#endif
603 2 dgisselq
 
604 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
605 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
606 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
607
                        (m_core->o_wb_stb)?"STB":"   ",
608
                        (m_core->o_wb_we )?"WE":"  ",
609
                        (m_core->o_wb_addr),
610
                        (m_core->o_wb_data),
611
                        (m_core->i_wb_ack)?"ACK":"   ",
612
                        (m_core->i_wb_stall)?"STL":"   ",
613 69 dgisselq
                        (m_core->i_wb_data),
614
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
615 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
616
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
617
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
618 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
619
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
620
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
621
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
622 58 dgisselq
                        (!mem_stalled()),       //1
623 2 dgisselq
 
624 58 dgisselq
                        (mem_stalled()),
625 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
626
                        (m_core->v__DOT__thecpu__DOT__master_ce),
627
                        (mem_pipe_stalled()),
628 134 dgisselq
                        (!m_core->v__DOT__thecpu__DOT__r_op_pipe),
629 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
630
                        );
631 140 dgisselq
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_pipe);
632 76 dgisselq
                // mvprintw(4,4,"r_dcdI = 0x%06x",
633
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
634 39 dgisselq
#endif
635
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
636 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
637
                printw(" A:%c%c B:%c%c",
638 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
639
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
640 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
641
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
642 69 dgisselq
#else
643
                printw(" A:xx B:xx");
644 57 dgisselq
#endif
645 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
646 39 dgisselq
 
647
 
648 2 dgisselq
                showins(ln, "I ",
649 69 dgisselq
#ifdef  OPT_PIPELINED
650 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
651 69 dgisselq
#else
652
                        1,
653
#endif
654 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
655
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
656
                        m_core->v__DOT__thecpu__DOT__gie,
657
                        0,
658 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
659
                        true); ln++;
660 36 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
661 2 dgisselq
 
662
                showins(ln, "Dc",
663 69 dgisselq
                        dcd_ce(), dcdvalid(),
664 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
665 69 dgisselq
#ifdef  OPT_PIPELINED
666 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
667 69 dgisselq
#else
668
                        0,
669
#endif
670 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
671
#ifdef  OPT_VLIW
672
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
673
#else
674
                        false
675
#endif
676
                        ); ln++;
677 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
678
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
679
                        mvprintw(ln-1,10,"I");
680
                else
681
#endif
682
                if (m_core->v__DOT__thecpu__DOT__dcdM)
683
                        mvprintw(ln-1,10,"M");
684 2 dgisselq
 
685
                showins(ln, "Op",
686 69 dgisselq
                        op_ce(),
687 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
688
                        m_core->v__DOT__thecpu__DOT__op_gie,
689
                        m_core->v__DOT__thecpu__DOT__op_stall,
690 76 dgisselq
                        op_pc(),
691
#ifdef  OPT_VLIW
692
                        m_core->v__DOT__thecpu__DOT__r_op_phase
693
#else
694
                        false
695
#endif
696
                        ); ln++;
697 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
698
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
699
                        mvprintw(ln-1,10,"I");
700
                else
701
#endif
702
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
703
                        mvprintw(ln-1,10,"M");
704
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
705
                        mvprintw(ln-1,10,"A");
706 2 dgisselq
 
707 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
708
                        showins(ln, "Mm",
709
                                m_core->v__DOT__thecpu__DOT__mem_ce,
710
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
711
                                m_core->v__DOT__thecpu__DOT__alu_gie,
712 69 dgisselq
#ifdef  OPT_PIPELINED
713 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
714 69 dgisselq
#else
715 148 dgisselq
                                0,
716 69 dgisselq
#endif
717 148 dgisselq
                                alu_pc(),
718 76 dgisselq
#ifdef  OPT_VLIW
719 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
720 76 dgisselq
#else
721 148 dgisselq
                                false
722 76 dgisselq
#endif
723 148 dgisselq
                        );
724
                } else {
725
                        showins(ln, "Al",
726
                                m_core->v__DOT__thecpu__DOT__alu_ce,
727
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
728
                                m_core->v__DOT__thecpu__DOT__alu_gie,
729
#ifdef  OPT_PIPELINED
730
                                m_core->v__DOT__thecpu__DOT__alu_stall,
731
#else
732
                                0,
733
#endif
734
                                alu_pc(),
735
#ifdef  OPT_VLIW
736
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
737
#else
738
                                false
739
#endif
740
                        );
741
                } ln++;
742 39 dgisselq
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
743
                        mvprintw(ln-1,10,"W");
744 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
745
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
746
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
747
                        mvprintw(ln-1,10,"v");
748 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
749 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
750
                        mvprintw(ln-1,10,"I");
751 58 dgisselq
#endif
752 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
753
                        // mvprintw(ln-1,10,"i");
754 2 dgisselq
 
755 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
756 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
757
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
758 2 dgisselq
                mvprintw(ln-4, 48,
759
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
760
                printw("(%s:%02x,%x)",
761
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
762
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
763
                        (m_core->v__DOT__thecpu__DOT__op_gie)
764
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
765
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
766
 
767
                printw("(%s%s%s:%02x)",
768
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
769
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
770
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
771
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
772
                /*
773
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
774
                        m_core->v__DOT__thecpu__DOT__dcdI);
775
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
776
                        m_core->v__DOT__thecpu__DOT__opB);
777
                */
778 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
779 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
780 87 dgisselq
                        m_core->v__DOT__thecpu__DOT__opA,
781
                        m_core->v__DOT__thecpu__DOT__opB);
782 27 dgisselq
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
783
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
784
                else
785
                        printw("%8s","");
786 76 dgisselq
                mvprintw(ln-1, 48, "%s%s%s ",
787
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
788 87 dgisselq
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__genblk2__DOT__r_busy)?"a":" "),
789 76 dgisselq
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
790
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
791
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
792
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
793
                printw("MEM: %s%s %s%s %s %-5s",
794 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
795 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
796
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
797 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
798 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
799 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
800
        }
801
 
802 43 dgisselq
        void    show_user_timers(bool v) {
803
                m_show_user_timers = v;
804
        }
805
 
806 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
807 57 dgisselq
                int     errcount = 0;
808 155 dgisselq
                if (m_dbgfp) {
809 2 dgisselq
                        dbg_flag= true;
810 155 dgisselq
                        fprintf(m_dbgfp, "CMD-READ(%d)\n", a);
811 2 dgisselq
                }
812
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
813 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
814
                        errcount++;
815
                if (errcount >= MAXERR) {
816
                        endwin();
817
 
818
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
819
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
820
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
821
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
822
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
823
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
824
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
825 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
826
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
827
#ifdef  OPT_PIPELINED
828 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
829 69 dgisselq
#endif
830 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
831 105 dgisselq
// #ifdef       OPT_EARLY_BRANCHING
832 69 dgisselq
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
833 105 dgisselq
// #endif
834 57 dgisselq
 
835
                        exit(-2);
836
                }
837
 
838
                assert(errcount < MAXERR);
839 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
840
 
841
                if (dbg_flag)
842 155 dgisselq
                        fprintf(m_dbgfp, "CMD-READ(%d) = 0x%08x\n", a, v);
843 2 dgisselq
                dbg_flag = false;
844
                return v;
845
        }
846
 
847 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
848 57 dgisselq
                int     errcount = 0;
849 34 dgisselq
                if ((a&0x0f)==0x0f)
850
                        dbg_flag = true;
851
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
852 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
853
                        errcount++;
854
                assert(errcount < MAXERR);
855 34 dgisselq
                if (dbg_flag)
856 155 dgisselq
                        fprintf(m_dbgfp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
857 34 dgisselq
                wb_write(CMD_DATA, v);
858
        }
859
 
860 27 dgisselq
        bool    halted(void) {
861
                return (m_core->v__DOT__cmd_halt != 0);
862
        }
863
 
864 2 dgisselq
        void    read_state(void) {
865
                int     ln= 0;
866 34 dgisselq
                bool    gie;
867 2 dgisselq
 
868 76 dgisselq
                read_raw_state();
869 34 dgisselq
                if (m_cursor < 0)
870
                        m_cursor = 0;
871
                else if (m_cursor >= 44)
872
                        m_cursor = 43;
873
 
874
                mvprintw(ln,0, "Peripherals-RS");
875
                mvprintw(ln,40,"%-40s", "CPU State: ");
876
                {
877
                        unsigned int v = wb_read(CMD_REG);
878
                        mvprintw(ln,51, "");
879
                        if (v & 0x010000)
880
                                printw("EXT-INT ");
881
                        if ((v & 0x003000) == 0x03000)
882
                                printw("Halted ");
883
                        else if (v & 0x001000)
884
                                printw("Sleeping ");
885
                        else if (v & 0x002000)
886 76 dgisselq
                                printw("User Mod ");
887 34 dgisselq
                        if (v & 0x008000)
888
                                printw("Break-Enabled ");
889
                        if (v & 0x000080)
890
                                printw("PIC Enabled ");
891
                } ln++;
892 76 dgisselq
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
893
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
894
                showval(ln,40, "WBUS", m_state.m_p[2], false);
895
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
896 2 dgisselq
                ln++;
897 76 dgisselq
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
898
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
899
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
900
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
901 2 dgisselq
 
902
                ln++;
903 43 dgisselq
                if (!m_show_user_timers) {
904 76 dgisselq
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
905
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
906
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
907
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
908 43 dgisselq
                } else {
909 76 dgisselq
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
910
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
911
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
912
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
913 43 dgisselq
                }
914 2 dgisselq
 
915
                ln++;
916
                ln++;
917 76 dgisselq
                unsigned int cc = m_state.m_sR[14];
918 155 dgisselq
                if (m_dbgfp) fprintf(m_dbgfp, "CC = %08x, gie = %d\n", cc,
919 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__gie);
920 34 dgisselq
                gie = (cc & 0x020);
921
                if (gie)
922 2 dgisselq
                        attroff(A_BOLD);
923
                else
924
                        attron(A_BOLD);
925
                mvprintw(ln, 0, "Supervisor Registers");
926
                ln++;
927
 
928 76 dgisselq
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
929
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
930
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
931
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
932 2 dgisselq
 
933 76 dgisselq
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
934
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
935
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
936
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
937 2 dgisselq
 
938 76 dgisselq
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
939
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
940
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
941
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
942 2 dgisselq
 
943 76 dgisselq
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
944
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
945 2 dgisselq
 
946 76 dgisselq
                if (true) {
947
                        mvprintw(ln,40, "%ssCC : 0x%08x",
948
                                (m_cursor==26)?">":" ", cc);
949
                } else {
950
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
951
                                (m_cursor==26)?">":" ",
952
                                (cc&0x01000)?"FE":"",
953
                                (cc&0x00800)?"DE":"",
954
                                (cc&0x00400)?"BE":"",
955
                                (cc&0x00200)?"TP":"",
956
                                (cc&0x00100)?"IL":"",
957
                                (cc&0x00080)?"BK":"",
958
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
959
                        mvprintw(ln, 54, "%s%s%s%s",
960
                                (cc&8)?"V":" ",
961
                                (cc&4)?"N":" ",
962
                                (cc&2)?"C":" ",
963
                                (cc&1)?"Z":" ");
964
                }
965 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
966 2 dgisselq
                ln++;
967
 
968 34 dgisselq
                if (gie)
969 2 dgisselq
                        attron(A_BOLD);
970
                else
971
                        attroff(A_BOLD);
972 69 dgisselq
                mvprintw(ln, 0, "User Registers");
973
                mvprintw(ln, 42, "DCDR=%02x %s",
974
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
975
                mvprintw(ln, 62, "OPR =%02x %s%s",
976
                        m_core->v__DOT__thecpu__DOT__opR,
977
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
978
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
979
                ln++;
980 76 dgisselq
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
981
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
982
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
983
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
984 2 dgisselq
 
985 76 dgisselq
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
986
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
987
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
988
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
989 2 dgisselq
 
990 76 dgisselq
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
991
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
992
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
993
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
994 2 dgisselq
 
995 76 dgisselq
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
996
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
997
                cc = m_state.m_uR[14];
998
                if (false) {
999
                        mvprintw(ln,40, "%cuCC : 0x%08x",
1000
                                (m_cursor == 42)?'>':' ', cc);
1001
                } else {
1002
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
1003
                                (m_cursor == 42)?'>':' ',
1004
                                (cc & 0x1000)?"FE":"",
1005
                                (cc & 0x0800)?"DE":"",
1006
                                (cc & 0x0400)?"BE":"",
1007
                                (cc & 0x0200)?"TP":"",
1008
                                (cc & 0x0100)?"IL":"",
1009
                                (cc & 0x0040)?"ST":"",
1010
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
1011
                        mvprintw(ln, 54, "%s%s%s%s",
1012
                                (cc&8)?"V":" ",
1013
                                (cc&4)?"N":" ",
1014
                                (cc&2)?"C":" ",
1015
                                (cc&1)?"Z":" ");
1016
                }
1017
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
1018 2 dgisselq
 
1019
                attroff(A_BOLD);
1020
                ln+=2;
1021
 
1022
                ln+=3;
1023
 
1024
                showins(ln, "I ",
1025 69 dgisselq
#ifdef  OPT_PIPELINED
1026 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
1027 69 dgisselq
#else
1028
                        1,
1029
#endif
1030 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
1031
                        m_core->v__DOT__thecpu__DOT__gie,
1032
                        0,
1033 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc,
1034
                        true); ln++;
1035 57 dgisselq
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
1036 2 dgisselq
 
1037
                showins(ln, "Dc",
1038 69 dgisselq
                        dcd_ce(), dcdvalid(),
1039 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
1040 69 dgisselq
#ifdef  OPT_PIPELINED
1041 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
1042 69 dgisselq
#else
1043
                        0,
1044
#endif
1045 76 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1046
#ifdef  OPT_VLIW
1047
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
1048
#else
1049
                        false
1050
#endif
1051
                        ); ln++;
1052 2 dgisselq
 
1053
                showins(ln, "Op",
1054 69 dgisselq
                        op_ce(),
1055 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
1056
                        m_core->v__DOT__thecpu__DOT__op_gie,
1057
                        m_core->v__DOT__thecpu__DOT__op_stall,
1058 76 dgisselq
                        op_pc(),
1059
#ifdef  OPT_VLIW
1060
                        m_core->v__DOT__thecpu__DOT__r_alu_phase
1061
#else
1062
                        false
1063
#endif
1064
                        ); ln++;
1065 2 dgisselq
 
1066 148 dgisselq
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem) {
1067
                        showins(ln, "Mm",
1068
                                m_core->v__DOT__thecpu__DOT__mem_ce,
1069
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
1070
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1071 69 dgisselq
#ifdef  OPT_PIPELINED
1072 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__mem_stall,
1073 69 dgisselq
#else
1074 148 dgisselq
                                0,
1075 69 dgisselq
#endif
1076 148 dgisselq
                                alu_pc(),
1077 76 dgisselq
#ifdef  OPT_VLIW
1078 148 dgisselq
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1079 76 dgisselq
#else
1080 148 dgisselq
                                false
1081 76 dgisselq
#endif
1082 148 dgisselq
                        );
1083
                } else {
1084
                        showins(ln, "Al",
1085
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1086
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1087
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1088
#ifdef  OPT_PIPELINED
1089
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1090
#else
1091
                                0,
1092
#endif
1093
                                alu_pc(),
1094
#ifdef  OPT_VLIW
1095
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1096
#else
1097
                                false
1098
#endif
1099
                        );
1100
                } ln++;
1101 2 dgisselq
        }
1102 69 dgisselq
 
1103 2 dgisselq
        void    tick(void) {
1104
                int gie = m_core->v__DOT__thecpu__DOT__gie;
1105
                /*
1106
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1107
                                                m_core->o_qspi_sck,
1108
                                                m_core->o_qspi_dat);
1109
                */
1110
 
1111 11 dgisselq
                int stb = m_core->o_wb_stb;
1112
                if ((m_core->o_wb_addr & (-1<<20))!=1)
1113
                        stb = 0;
1114
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
1115
                        m_core->i_wb_ack = 1;
1116 2 dgisselq
 
1117 155 dgisselq
                if ((dbg_flag)&&(m_dbgfp)) {
1118
                        fprintf(m_dbgfp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1119 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1120
                                (m_core->i_dbg_stb)?"STB":
1121
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1122
                                ((m_core->i_dbg_we)?"WE":"  "),
1123
                                (m_core->i_dbg_addr),0,
1124
                                m_core->i_dbg_data,
1125
                                (m_core->o_dbg_ack)?"ACK":"   ",
1126
                                (m_core->o_dbg_stall)?"STALL":"     ",
1127
                                (m_core->o_dbg_data),
1128
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1129
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
1130 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
1131 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
1132
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1133 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
1134
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
1135 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
1136
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1137
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1138
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1139 155 dgisselq
                        fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1140 2 dgisselq
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1141
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1142
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1143
                                (m_core->v__DOT__sys_addr),
1144
                                (m_core->v__DOT__dbg_addr),
1145
                                (m_core->v__DOT__sys_data),
1146
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1147
                                (m_core->v__DOT__wb_data));
1148
                }
1149
 
1150 155 dgisselq
                if (m_dbgfp)
1151
                        fprintf(m_dbgfp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1152 69 dgisselq
                                dcd_ce(),
1153 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1154 69 dgisselq
                                op_ce(),
1155 39 dgisselq
                                op_pc(),
1156 69 dgisselq
                                dcdA()&0x01f,
1157 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opR,
1158
                                m_core->v__DOT__cmd_halt,
1159
                                m_core->v__DOT__cpu_halt,
1160
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1161
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1162
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1163
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1164
                                m_core->v__DOT__thecpu__DOT__ipc,
1165
                                m_core->v__DOT__thecpu__DOT__upc);
1166
 
1167 155 dgisselq
                if ((m_dbgfp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1168
                        fprintf(m_dbgfp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1169 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1170 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1171
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1172 155 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1173 2 dgisselq
                                m_core->v__DOT__cmd_addr,
1174
                                m_core->v__DOT__dbg_idata,
1175
                                m_core->v__DOT__thecpu__DOT__master_ce,
1176
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1177
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1178
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1179 155 dgisselq
                } else if ((m_dbgfp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1180
                        fprintf(m_dbgfp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1181 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1182
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1183 155 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1184 2 dgisselq
                                m_core->v__DOT__cmd_addr,
1185
                                m_core->v__DOT__dbg_idata,
1186
                                m_core->v__DOT__thecpu__DOT__master_ce,
1187
                                m_core->v__DOT__thecpu__DOT__alu_wr,
1188
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1189
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1190
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1191
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1192 155 dgisselq
                        fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
1193 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1194 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
1195
                                m_core->v__DOT__thecpu__DOT__op_break);
1196 155 dgisselq
                } else if ((m_dbgfp)&&
1197 36 dgisselq
                                ((m_core->v__DOT__thecpu__DOT__op_break)
1198 76 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1199 36 dgisselq
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1200 155 dgisselq
                        fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1201
                        fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1202 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1203
                                m_core->v__DOT__thecpu__DOT__break_en,
1204
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1205 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__op_break,
1206
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1207 2 dgisselq
                }
1208
 
1209 155 dgisselq
                if (m_dbgfp) {
1210 34 dgisselq
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1211 155 dgisselq
                                fprintf(m_dbgfp, "\tClear Pipeline\n");
1212 34 dgisselq
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1213 155 dgisselq
                                fprintf(m_dbgfp, "\tNew PC\n");
1214 34 dgisselq
                }
1215
 
1216 155 dgisselq
                if (m_dbgfp)
1217
                        fprintf(m_dbgfp, "-----------  TICK ----------\n");
1218 36 dgisselq
                if (false) {
1219
                        m_core->i_clk = 1;
1220
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1221
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1222
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1223
                        eval();
1224
                        m_core->i_clk = 0;
1225
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1226
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1227
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1228
                        eval();
1229
                        m_tickcount++;
1230
                } else {
1231
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1232
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
1233
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1234 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
1235
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
1236
                                m_core->i_wb_err = 1;
1237
                        else
1238
                                m_core->i_wb_err = 0;
1239 36 dgisselq
                        TESTB<Vzipsystem>::tick();
1240
                }
1241 155 dgisselq
                if ((m_dbgfp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
1242
                        fprintf(m_dbgfp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1243 2 dgisselq
                                (gie)?"User":"Supervisor",
1244
                                (gie)?"Supervisor":"User",
1245
                                m_core->v__DOT__thecpu__DOT__ipc,
1246
                                m_core->v__DOT__thecpu__DOT__upc,
1247
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1248 155 dgisselq
                } if (m_dbgfp) {
1249 76 dgisselq
#ifdef  OPT_TRADITIONAL_PFCACHE
1250 155 dgisselq
                        fprintf(m_dbgfp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1251 69 dgisselq
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1252
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1253 105 dgisselq
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
1254
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
1255 69 dgisselq
                                &&(dcdvalid())
1256
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1257
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1258
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
1259
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1260 76 dgisselq
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1261
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1262 69 dgisselq
#endif
1263
                        dbgins("Dc - ",
1264
                                dcd_ce(), dcdvalid(),
1265 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1266 69 dgisselq
#ifdef  OPT_PIPELINED
1267 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1268 69 dgisselq
#else
1269
                                0,
1270
#endif
1271 76 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1272
#ifdef  OPT_VLIW
1273
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1274
#else
1275
                                false,
1276
#endif
1277
#ifdef  OPT_ILLEGAL_INSTRUCTION
1278
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1279
#else
1280
                                false
1281
#endif
1282
                                );
1283 69 dgisselq
                        dbgins("Op - ",
1284
                                op_ce(),
1285 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1286
                                m_core->v__DOT__thecpu__DOT__op_gie,
1287
                                m_core->v__DOT__thecpu__DOT__op_stall,
1288 76 dgisselq
                                op_pc(),
1289
#ifdef  OPT_VLIW
1290
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1291
#else
1292
                                false,
1293 57 dgisselq
#endif
1294 76 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
1295
                                m_core->v__DOT__thecpu__DOT__op_illegal
1296
#else
1297
                                false
1298
#endif
1299
                                );
1300 2 dgisselq
                        dbgins("Al - ",
1301
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1302
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1303
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1304 69 dgisselq
#ifdef  OPT_PIPELINED
1305 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1306 69 dgisselq
#else
1307
                                0,
1308
#endif
1309 76 dgisselq
                                alu_pc(),
1310
#ifdef  OPT_VLIW
1311
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1312
#else
1313
                                false,
1314
#endif
1315
#ifdef  OPT_ILLEGAL_INSTRUCTION
1316
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1317
#else
1318
                                false
1319
#endif
1320
                                );
1321 2 dgisselq
 
1322
                }
1323 58 dgisselq
 
1324 155 dgisselq
                if ((m_dbgfp)&&((m_core->v__DOT__thecpu__DOT__div_valid)
1325
                        ||(m_core->v__DOT__thecpu__DOT__div_ce)
1326
                        ||(m_core->v__DOT__thecpu__DOT__div_busy)
1327
                        )) {
1328
                        fprintf(m_dbgfp, "DIV: %s %s %s %s[%2x] GP:%08x/SP:%08x %s:0x%08x\n",
1329
                                (m_core->v__DOT__thecpu__DOT__div_ce)?"CE":"  ",
1330
                                (m_core->v__DOT__thecpu__DOT__div_busy)?"BUSY":"    ",
1331
                                (m_core->v__DOT__thecpu__DOT__div_valid)?"VALID":"     ",
1332
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"REG-CE":"      ",
1333
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1334
                                m_core->v__DOT__thecpu__DOT__wr_gpreg_vl,
1335
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1336
                                (m_core->v__DOT__thecpu__DOT__alu_pc_valid)?"PCV":"   ",
1337
                                m_core->v__DOT__thecpu__DOT__alu_pc);
1338
 
1339
                        fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
1340
                                m_core->v__DOT__thecpu__DOT__alu_pc,
1341
                                (m_core->v__DOT__thecpu__DOT__r_alu_pc_valid)?"VALID":"",
1342
                                (m_core->v__DOT__thecpu__DOT__alu_gie)?"ALU-GIE":"");
1343
                }
1344
 
1345 58 dgisselq
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1346
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
1347
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1348
                        if (m_profile_fp) {
1349
                                unsigned buf[2];
1350
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
1351
                                buf[1] = iticks;
1352
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1353
                        }
1354
                        m_last_instruction_tickcount = m_tickcount;
1355
                }
1356 2 dgisselq
        }
1357
 
1358
        bool    test_success(void) {
1359
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1360
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1361
        }
1362
 
1363 39 dgisselq
        unsigned        op_pc(void) {
1364
                /*
1365
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1366
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1367
                        r--;
1368
                return r;
1369
                */
1370
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1371
        }
1372
 
1373 69 dgisselq
        bool    dcd_ce(void) {
1374
#ifdef  OPT_PIPELINED
1375
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1376
#else
1377
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1378
#endif
1379
        } bool  dcdvalid(void) {
1380
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1381
        }
1382
        bool    pfstall(void) {
1383
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1384
                        ||(m_core->v__DOT__cpu_stall));
1385
        }
1386
        unsigned        dcdR(void) {
1387
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1388
        }
1389
        unsigned        dcdA(void) {
1390
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1391
        }
1392
        unsigned        dcdB(void) {
1393
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1394
        }
1395
 
1396
        bool    op_ce(void) {
1397
#ifdef  OPT_PIPELINED
1398
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1399
#else
1400
                // return (dcdvalid())&&(opvalid())
1401
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1402
                return  dcdvalid();
1403
#endif
1404
        } bool  opvalid(void) {
1405
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1406
        }
1407
 
1408 58 dgisselq
        bool    mem_busy(void) {
1409
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1410 69 dgisselq
#ifdef  OPT_PIPELINED
1411 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1412 69 dgisselq
#else
1413
                return 0;
1414
#endif
1415 58 dgisselq
        }
1416
 
1417
        bool    mem_stalled(void) {
1418
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1419
 
1420
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1421
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1422
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
1423
 
1424 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1425
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1426
                a = mem_pipe_stalled();
1427 134 dgisselq
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
1428 69 dgisselq
#else
1429
                a = false;
1430
                b = false;
1431
#endif
1432 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1433
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1434 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1435 58 dgisselq
                        &&d);
1436
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1437
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1438
        }
1439
 
1440 39 dgisselq
        unsigned        alu_pc(void) {
1441
                /*
1442
                unsigned        r = op_pc();
1443
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1444
                        r--;
1445
                return r;
1446
                */
1447
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1448
        }
1449
 
1450
#ifdef  OPT_PIPELINED_BUS_ACCESS
1451 69 dgisselq
        bool    mem_pipe_stalled(void) {
1452 39 dgisselq
                int     r = 0;
1453
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1454
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1455
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1456
                        ||(
1457
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1458
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1459
                return r;
1460
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1461
        }
1462
#endif
1463
 
1464 2 dgisselq
        bool    test_failure(void) {
1465 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1466
                        return 0;
1467
                else if (m_core->v__DOT__thecpu__DOT__gie)
1468 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
1469 134 dgisselq
                else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
1470
                        return true; // ADD to PC instruction
1471
                else // MOV to PC instruction
1472 76 dgisselq
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1473 43 dgisselq
                /*
1474 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1475 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1476 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1477 43 dgisselq
                */
1478 2 dgisselq
        }
1479
 
1480
        void    wb_write(unsigned a, unsigned int v) {
1481 36 dgisselq
                int     errcount = 0;
1482 2 dgisselq
                mvprintw(0,35, "%40s", "");
1483
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1484
                m_core->i_dbg_cyc = 1;
1485
                m_core->i_dbg_stb = 1;
1486
                m_core->i_dbg_we  = 1;
1487
                m_core->i_dbg_addr = a & 1;
1488
                m_core->i_dbg_data = v;
1489
 
1490
                tick();
1491 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1492 2 dgisselq
                        tick();
1493
 
1494
                m_core->i_dbg_stb = 0;
1495 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1496 2 dgisselq
                        tick();
1497
 
1498
                // Release the bus
1499
                m_core->i_dbg_cyc = 0;
1500
                m_core->i_dbg_stb = 0;
1501
                tick();
1502
                mvprintw(0,35, "%40s", "");
1503
                mvprintw(0,40, "wb_write -- complete");
1504 36 dgisselq
 
1505
 
1506
                if (errcount >= 100)
1507
                        bomb = true;
1508 2 dgisselq
        }
1509
 
1510
        unsigned long   wb_read(unsigned a) {
1511
                unsigned int    v;
1512 36 dgisselq
                int     errcount = 0;
1513 2 dgisselq
                mvprintw(0,35, "%40s", "");
1514
                mvprintw(0,40, "wb_read(0x%08x)", a);
1515
                m_core->i_dbg_cyc = 1;
1516
                m_core->i_dbg_stb = 1;
1517
                m_core->i_dbg_we  = 0;
1518
                m_core->i_dbg_addr = a & 1;
1519
 
1520
                tick();
1521 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1522 2 dgisselq
                        tick();
1523
 
1524
                m_core->i_dbg_stb = 0;
1525 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1526 2 dgisselq
                        tick();
1527
                v = m_core->o_dbg_data;
1528
 
1529
                // Release the bus
1530
                m_core->i_dbg_cyc = 0;
1531
                m_core->i_dbg_stb = 0;
1532
                tick();
1533
 
1534
                mvprintw(0,35, "%40s", "");
1535
                mvprintw(0,40, "wb_read = 0x%08x", v);
1536
 
1537 36 dgisselq
                if (errcount >= 100)
1538
                        bomb = true;
1539 2 dgisselq
                return v;
1540
        }
1541
 
1542 34 dgisselq
        void    cursor_up(void) {
1543
                if (m_cursor > 3)
1544
                        m_cursor -= 4;
1545
        } void  cursor_down(void) {
1546
                if (m_cursor < 40)
1547
                        m_cursor += 4;
1548
        } void  cursor_left(void) {
1549
                if (m_cursor > 0)
1550
                        m_cursor--;
1551
                else    m_cursor = 43;
1552
        } void  cursor_right(void) {
1553
                if (m_cursor < 43)
1554
                        m_cursor++;
1555
                else    m_cursor = 0;
1556
        }
1557
 
1558
        int     cursor(void) { return m_cursor; }
1559 155 dgisselq
 
1560
        void    jump_to(ZIPI address) {
1561
                m_core->v__DOT__thecpu__DOT__pf_pc = address;
1562
                m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1563
                m_core->v__DOT__thecpu__DOT__new_pc = 1;
1564
        }
1565
 
1566
        void    dump_state(void) {
1567
                if (m_dbgfp)
1568
                        dump_state(m_dbgfp);
1569
        }
1570
 
1571
        void    dump_state(FILE *fp) {
1572
                if (!fp)
1573
                        return;
1574
                fprintf(fp, "FINAL STATE: %s\n",
1575
                        (m_state.m_gie)?"GIE(User-Mode)":"Supervisor-mode");
1576
                fprintf(fp, "Supervisor Registers\n");
1577
                for(int i=0; i<16; i++) {
1578
                        char str[16];
1579
                        if (i==13)
1580
                                sprintf(str, "sSP");
1581
                        else if (i==14)
1582
                                sprintf(str, "sCC");
1583
                        else if (i==15)
1584
                                sprintf(str, "sPC");
1585
                        else // if (i<=12)
1586
                                sprintf(str, "s-%2d", i);
1587
                        dbgreg(fp, i, str, m_state.m_sR[i]);
1588
                        if ((i&3)==3)
1589
                                fprintf(fp, "\n");
1590
                }
1591
                fprintf(fp, "User Registers\n");
1592
                for(int i=0; i<16; i++) {
1593
                        char str[16];
1594
                        if (i==13)
1595
                                sprintf(str, "uSP");
1596
                        else if (i==14)
1597
                                sprintf(str, "uCC");
1598
                        else if (i==15)
1599
                                sprintf(str, "uPC");
1600
                        else // if (i<=12)
1601
                                sprintf(str, "u-%2d", i);
1602
                        dbgreg(fp, i, str, m_state.m_uR[i]);
1603
                        if ((i&3)==3)
1604
                                fprintf(fp, "\n");
1605
                }
1606
        }
1607 2 dgisselq
};
1608
 
1609 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1610
        int     wy, wx, ra;
1611
        int     c = tb->cursor();
1612
 
1613
        wx = (c & 0x03) * 20 + 9;
1614
        wy = (c>>2);
1615
        if (wy >= 3+4)
1616
                wy++;
1617
        if (wy > 3)
1618
                wy += 2;
1619
        wy++;
1620
 
1621
        if (c >= 12)
1622
                ra = c - 12;
1623
        else
1624
                ra = c + 32;
1625
 
1626
        bool    done = false;
1627
        char    str[16];
1628
        int     pos = 0; str[pos] = '\0';
1629
        while(!done) {
1630
                int     chv = getch();
1631
                switch(chv) {
1632
                case KEY_ESCAPE:
1633
                        pos = 0; str[pos] = '\0'; done = true;
1634
                        break;
1635
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1636
                        done = true;
1637
                        break;
1638
                case KEY_LEFT: case KEY_BACKSPACE:
1639
                        if (pos > 0) pos--;
1640
                        break;
1641 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1642 34 dgisselq
                case KEY_CLEAR:
1643
                        pos = 0;
1644
                        break;
1645
                case '0': case ' ': str[pos++] = '0'; break;
1646
                case '1': str[pos++] = '1'; break;
1647
                case '2': str[pos++] = '2'; break;
1648
                case '3': str[pos++] = '3'; break;
1649
                case '4': str[pos++] = '4'; break;
1650
                case '5': str[pos++] = '5'; break;
1651
                case '6': str[pos++] = '6'; break;
1652
                case '7': str[pos++] = '7'; break;
1653
                case '8': str[pos++] = '8'; break;
1654
                case '9': str[pos++] = '9'; break;
1655
                case 'A': case 'a': str[pos++] = 'A'; break;
1656
                case 'B': case 'b': str[pos++] = 'B'; break;
1657
                case 'C': case 'c': str[pos++] = 'C'; break;
1658
                case 'D': case 'd': str[pos++] = 'D'; break;
1659
                case 'E': case 'e': str[pos++] = 'E'; break;
1660
                case 'F': case 'f': str[pos++] = 'F'; break;
1661
                }
1662
 
1663
                if (pos > 8)
1664
                        pos = 8;
1665
                str[pos] = '\0';
1666
 
1667
                attron(A_NORMAL | A_UNDERLINE);
1668
                mvprintw(wy, wx, "%-8s", str);
1669
                if (pos > 0) {
1670
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1671
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1672
                }
1673
                attrset(A_NORMAL);
1674
        }
1675
 
1676
        if (pos > 0) {
1677
                int     v;
1678
                v = strtoul(str, NULL, 16);
1679
                if (!tb->halted()) {
1680
                        switch(ra) {
1681
                        case 15:
1682
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1683
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1684
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1685
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1686
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1687
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1688 69 dgisselq
#ifdef  OPT_PIPELINED
1689 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1690 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1691
#endif
1692 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1693
                                }
1694
                                break;
1695
                        case 31:
1696
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1697
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1698
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1699
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1700
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1701
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1702 69 dgisselq
#ifdef  OPT_PIPELINED
1703 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1704 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1705
#endif
1706 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1707
                                }
1708
                                break;
1709
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1710
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1711 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1712 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1713 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1714
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1715
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1716
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1717
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1718
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1719
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1720
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1721
                        default:
1722
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1723
                                break;
1724
                        }
1725
                } else
1726
                        tb->cmd_write(ra, v);
1727
        }
1728
}
1729
 
1730 155 dgisselq
 
1731
bool    iself(const char *fname) {
1732
        FILE    *fp;
1733
        bool    ret = true;
1734
        fp = fopen(fname, "rb");
1735
 
1736
        if (!fp)        return false;
1737
        if (0x7f != fgetc(fp))  ret = false;
1738
        if ('E'  != fgetc(fp))  ret = false;
1739
        if ('L'  != fgetc(fp))  ret = false;
1740
        if ('F'  != fgetc(fp))  ret = false;
1741
        fclose(fp);
1742
        return  ret;
1743
}
1744
 
1745
long    fgetwords(FILE *fp) {
1746
        // Return the number of words in the current file, and return the 
1747
        // file as though it had never been adjusted
1748
        long    fpos, flen;
1749
        fpos = ftell(fp);
1750
        if (0 != fseek(fp, 0l, SEEK_END)) {
1751
                fprintf(stderr, "ERR: Could not determine file size\n");
1752
                perror("O/S Err:");
1753
                exit(-2);
1754
        } flen = ftell(fp);
1755
        if (0 != fseek(fp, fpos, SEEK_SET)) {
1756
                fprintf(stderr, "ERR: Could not seek on file\n");
1757
                perror("O/S Err:");
1758
                exit(-2);
1759
        } flen /= sizeof(ZIPI);
1760
        return flen;
1761
}
1762
 
1763
class   SECTION {
1764
public:
1765
        unsigned        m_start, m_len;
1766
        ZIPI            m_data[1];
1767
};
1768
 
1769
SECTION **singlesection(int nwords) {
1770
        fprintf(stderr, "NWORDS = %d\n", nwords);
1771
        size_t  sz = (2*(sizeof(SECTION)+sizeof(SECTION *))
1772
                +(nwords-1)*(sizeof(ZIPI)));
1773
        char    *d = (char *)malloc(sz);
1774
        SECTION **r = (SECTION **)d;
1775
        memset(r, 0, sz);
1776
        r[0] = (SECTION *)(&d[2*sizeof(SECTION *)]);
1777
        r[0]->m_len   = nwords;
1778
        r[1] = (SECTION *)(&r[0]->m_data[r[0]->m_len]);
1779
        r[0]->m_start = 0;
1780
        r[1]->m_start = 0;
1781
        r[1]->m_len   = 0;
1782
 
1783
        return r;
1784
}
1785
 
1786
SECTION **rawsection(const char *fname) {
1787
        SECTION         **secpp, *secp;
1788
        unsigned        num_words;
1789
        FILE            *fp;
1790
        int             nr;
1791
 
1792
        fp = fopen(fname, "r");
1793
        if (fp == NULL) {
1794
                fprintf(stderr, "Could not open: %s\n", fname);
1795
                exit(-1);
1796
        }
1797
 
1798
        if ((num_words=fgetwords(fp)) > MEMWORDS) {
1799
                fprintf(stderr, "File overruns Block RAM\n");
1800
                exit(-1);
1801
        }
1802
        secpp = singlesection(num_words);
1803
        secp = secpp[0];
1804
        secp->m_start = RAMBASE;
1805
        secp->m_len = num_words;
1806
        nr= fread(secp->m_data, sizeof(ZIPI), num_words, fp);
1807
        if (nr != (int)num_words) {
1808
                fprintf(stderr, "Could not read entire file\n");
1809
                perror("O/S Err:");
1810
                exit(-2);
1811
        } assert(secpp[1]->m_len == 0);
1812
 
1813
        return secpp;
1814
}
1815
 
1816
unsigned        byteswap(unsigned n) {
1817
        unsigned        r;
1818
 
1819
        r = (n&0x0ff); n>>= 8;
1820
        r = (r<<8) | (n&0x0ff); n>>= 8;
1821
        r = (r<<8) | (n&0x0ff); n>>= 8;
1822
        r = (r<<8) | (n&0x0ff); n>>= 8;
1823
 
1824
        return r;
1825
}
1826
 
1827
#include <libelf.h>
1828
#include <gelf.h>
1829
 
1830
void    elfread(const char *fname, unsigned &entry, SECTION **&sections) {
1831
        Elf     *e;
1832
        int     fd, i;
1833
        size_t  n;
1834
        char    *id;
1835
        Elf_Kind        ek;
1836
        GElf_Ehdr       ehdr;
1837
        GElf_Phdr       phdr;
1838
        const   bool    dbg = false;
1839
 
1840
        if (elf_version(EV_CURRENT) == EV_NONE) {
1841
                fprintf(stderr, "ELF library initialization err, %s\n", elf_errmsg(-1));
1842
                perror("O/S Err:");
1843
                exit(EXIT_FAILURE);
1844
        } if ((fd = open(fname, O_RDONLY, 0)) < 0) {
1845
                fprintf(stderr, "Could not open %s\n", fname);
1846
                perror("O/S Err:");
1847
                exit(EXIT_FAILURE);
1848
        } if ((e = elf_begin(fd, ELF_C_READ, NULL))==NULL) {
1849
                fprintf(stderr, "Could not run elf_begin, %s\n", elf_errmsg(-1));
1850
                exit(EXIT_FAILURE);
1851
        }
1852
 
1853
        ek = elf_kind(e);
1854
        if (ek == ELF_K_ELF) {
1855
                ; // This is the kind of file we should expect
1856
        } else if (ek == ELF_K_AR) {
1857
                fprintf(stderr, "Cannot run an archive!\n");
1858
                exit(EXIT_FAILURE);
1859
        } else if (ek == ELF_K_NONE) {
1860
                ;
1861
        } else {
1862
                fprintf(stderr, "Unexpected ELF file kind!\n");
1863
                exit(EXIT_FAILURE);
1864
        }
1865
 
1866
        if (gelf_getehdr(e, &ehdr) == NULL) {
1867
                fprintf(stderr, "getehdr() failed: %s\n", elf_errmsg(-1));
1868
                exit(EXIT_FAILURE);
1869
        } if ((i=gelf_getclass(e)) == ELFCLASSNONE) {
1870
                fprintf(stderr, "getclass() failed: %s\n", elf_errmsg(-1));
1871
                exit(EXIT_FAILURE);
1872
        } if ((id = elf_getident(e, NULL)) == NULL) {
1873
                fprintf(stderr, "getident() failed: %s\n", elf_errmsg(-1));
1874
                exit(EXIT_FAILURE);
1875
        } if (i != ELFCLASS32) {
1876
                fprintf(stderr, "This is a 64-bit ELF file, ZipCPU ELF files are all 32-bit\n");
1877
                exit(EXIT_FAILURE);
1878
        }
1879
 
1880
        if (dbg) {
1881
        printf("    %-20s 0x%jx\n", "e_type", (uintmax_t)ehdr.e_type);
1882
        printf("    %-20s 0x%jx\n", "e_machine", (uintmax_t)ehdr.e_machine);
1883
        printf("    %-20s 0x%jx\n", "e_version", (uintmax_t)ehdr.e_version);
1884
        printf("    %-20s 0x%jx\n", "e_entry", (uintmax_t)ehdr.e_entry);
1885
        printf("    %-20s 0x%jx\n", "e_phoff", (uintmax_t)ehdr.e_phoff);
1886
        printf("    %-20s 0x%jx\n", "e_shoff", (uintmax_t)ehdr.e_shoff);
1887
        printf("    %-20s 0x%jx\n", "e_flags", (uintmax_t)ehdr.e_flags);
1888
        printf("    %-20s 0x%jx\n", "e_ehsize", (uintmax_t)ehdr.e_ehsize);
1889
        printf("    %-20s 0x%jx\n", "e_phentsize", (uintmax_t)ehdr.e_phentsize);
1890
        printf("    %-20s 0x%jx\n", "e_shentsize", (uintmax_t)ehdr.e_shentsize);
1891
        printf("\n");
1892
        }
1893
 
1894
 
1895
        // Check whether or not this is an ELF file for the ZipCPU ...
1896
        if (ehdr.e_machine != 0x0dadd) {
1897
                fprintf(stderr, "This is not a ZipCPU ELF file\n");
1898
                exit(EXIT_FAILURE);
1899
        }
1900
 
1901
        // Get our entry address
1902
        entry = ehdr.e_entry;
1903
 
1904
 
1905
        // Now, let's go look at the program header
1906
        if (elf_getphdrnum(e, &n) != 0) {
1907
                fprintf(stderr, "elf_getphdrnum() failed: %s\n", elf_errmsg(-1));
1908
                exit(EXIT_FAILURE);
1909
        }
1910
 
1911
        unsigned total_octets = 0, current_offset=0, current_section=0;
1912
        for(i=0; i<(int)n; i++) {
1913
                total_octets += sizeof(SECTION *)+sizeof(SECTION);
1914
 
1915
                if (gelf_getphdr(e, i, &phdr) != &phdr) {
1916
                        fprintf(stderr, "getphdr() failed: %s\n", elf_errmsg(-1));
1917
                        exit(EXIT_FAILURE);
1918
                }
1919
 
1920
                if (dbg) {
1921
                printf("    %-20s 0x%x\n", "p_type",   phdr.p_type);
1922
                printf("    %-20s 0x%jx\n", "p_offset", phdr.p_offset);
1923
                printf("    %-20s 0x%jx\n", "p_vaddr",  phdr.p_vaddr);
1924
                printf("    %-20s 0x%jx\n", "p_paddr",  phdr.p_paddr);
1925
                printf("    %-20s 0x%jx\n", "p_filesz", phdr.p_filesz);
1926
                printf("    %-20s 0x%jx\n", "p_memsz",  phdr.p_memsz);
1927
                printf("    %-20s 0x%x [", "p_flags",  phdr.p_flags);
1928
 
1929
                if (phdr.p_flags & PF_X)        printf(" Execute");
1930
                if (phdr.p_flags & PF_R)        printf(" Read");
1931
                if (phdr.p_flags & PF_W)        printf(" Write");
1932
                printf("]\n");
1933
                printf("    %-20s 0x%jx\n", "p_align", phdr.p_align);
1934
                }
1935
 
1936
                total_octets += phdr.p_memsz;
1937
        }
1938
 
1939
        char    *d = (char *)malloc(total_octets + sizeof(SECTION)+sizeof(SECTION *));
1940
        memset(d, 0, total_octets);
1941
 
1942
        SECTION **r = sections = (SECTION **)d;
1943
        current_offset = (n+1)*sizeof(SECTION *);
1944
        current_section = 0;
1945
 
1946
        for(i=0; i<(int)n; i++) {
1947
                r[i] = (SECTION *)(&d[current_offset]);
1948
 
1949
                if (gelf_getphdr(e, i, &phdr) != &phdr) {
1950
                        fprintf(stderr, "getphdr() failed: %s\n", elf_errmsg(-1));
1951
                        exit(EXIT_FAILURE);
1952
                }
1953
 
1954
                if (dbg) {
1955
                printf("    %-20s 0x%jx\n", "p_offset", phdr.p_offset);
1956
                printf("    %-20s 0x%jx\n", "p_vaddr",  phdr.p_vaddr);
1957
                printf("    %-20s 0x%jx\n", "p_paddr",  phdr.p_paddr);
1958
                printf("    %-20s 0x%jx\n", "p_filesz", phdr.p_filesz);
1959
                printf("    %-20s 0x%jx\n", "p_memsz",  phdr.p_memsz);
1960
                printf("    %-20s 0x%x [", "p_flags",  phdr.p_flags);
1961
 
1962
                if (phdr.p_flags & PF_X)        printf(" Execute");
1963
                if (phdr.p_flags & PF_R)        printf(" Read");
1964
                if (phdr.p_flags & PF_W)        printf(" Write");
1965
                printf("]\n");
1966
 
1967
                printf("    %-20s 0x%jx\n", "p_align", phdr.p_align);
1968
                }
1969
 
1970
                current_section++;
1971
 
1972
                r[i]->m_start = phdr.p_vaddr;
1973
                r[i]->m_len   = phdr.p_filesz/ sizeof(ZIPI);
1974
 
1975
                current_offset += phdr.p_memsz + sizeof(SECTION);
1976
 
1977
                // Now, let's read in our section ...
1978
                if (lseek(fd, phdr.p_offset, SEEK_SET) < 0) {
1979
                        fprintf(stderr, "Could not seek to file position %08lx\n", phdr.p_offset);
1980
                        perror("O/S Err:");
1981
                        exit(EXIT_FAILURE);
1982
                } if (phdr.p_filesz > phdr.p_memsz)
1983
                        phdr.p_filesz = 0;
1984
                if (read(fd, r[i]->m_data, phdr.p_filesz) != (int)phdr.p_filesz) {
1985
                        fprintf(stderr, "Didnt read entire section\n");
1986
                        perror("O/S Err:");
1987
                        exit(EXIT_FAILURE);
1988
                }
1989
 
1990
                // Next, we need to byte swap it from big to little endian
1991
                for(unsigned j=0; j<r[i]->m_len; j++)
1992
                        r[i]->m_data[j] = byteswap(r[i]->m_data[j]);
1993
 
1994
                if (dbg) for(unsigned j=0; j<r[i]->m_len; j++)
1995
                        fprintf(stderr, "ADR[%04x] = %08x\n", r[i]->m_start+j,
1996
                        r[i]->m_data[j]);
1997
        }
1998
 
1999
        r[i] = (SECTION *)(&d[current_offset]);
2000
        r[current_section]->m_start = 0;
2001
        r[current_section]->m_len   = 0;
2002
 
2003
        elf_end(e);
2004
        close(fd);
2005
}
2006
 
2007 27 dgisselq
void    usage(void) {
2008
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
2009
        printf("\n");
2010
        printf("\tWhere testfile.out is an output file from the assembler.\n");
2011 148 dgisselq
        printf("\tThis file needs to be in a raw format and not an ELF\n");
2012
        printf("\texecutable.  It will be inserted into memory at a memory\n");
2013
        printf("\taddress of 0x0100000.  The memory device itself, the only\n");
2014
        printf("\tdevice supported by this simulator, occupies addresses from\n");
2015
        printf("\t0x0100000 to 0x01fffff.\n");
2016
        printf("\n");
2017 27 dgisselq
        printf("\t-a\tSets the testbench to run automatically without any\n");
2018
        printf("\t\tuser interaction.\n");
2019
        printf("\n");
2020
        printf("\tUser Commands:\n");
2021
        printf("\t\tWhen the test bench is run interactively, the following\n");
2022
        printf("\t\tkey strokes are recognized:\n");
2023
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
2024
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
2025
        printf("\t\t\tuser intervention.\n");
2026
        printf("\t\t\'q\'\tQuit the simulation.\n");
2027
        printf("\t\t\'r\'\tReset the processor.\n");
2028
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
2029
        printf("\t\t\tThis may consume more than one tick.\n");
2030
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
2031
}
2032 2 dgisselq
 
2033 43 dgisselq
bool    signalled = false;
2034
 
2035
void    sigint(int v) {
2036
        signalled = true;
2037
}
2038
 
2039 2 dgisselq
int     main(int argc, char **argv) {
2040
        Verilated::commandArgs(argc, argv);
2041
        ZIPPY_TB        *tb = new ZIPPY_TB();
2042 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
2043 155 dgisselq
        ZIPI            entry = RAMBASE;
2044 2 dgisselq
 
2045
        // mem[0x00000] = 0xbe000010; // Halt instruction
2046
        unsigned int mptr = 0;
2047
 
2048 43 dgisselq
        signal(SIGINT, sigint);
2049
 
2050 9 dgisselq
        if (argc <= 1) {
2051 27 dgisselq
                usage();
2052
                exit(-1);
2053 9 dgisselq
        } else {
2054
                for(int argn=1; argn<argc; argn++) {
2055 27 dgisselq
                        if (argv[argn][0] == '-') {
2056
                                switch(argv[argn][1]) {
2057
                                case 'a':
2058
                                        autorun = true;
2059
                                        break;
2060
                                case 'e':
2061
                                        exit_on_done = true;
2062
                                        break;
2063
                                case 'h':
2064
                                        usage();
2065
                                        exit(0);
2066
                                        break;
2067 36 dgisselq
                                case 's':
2068
                                        autostep = true;
2069
                                        break;
2070 27 dgisselq
                                default:
2071
                                        usage();
2072
                                        exit(-1);
2073
                                        break;
2074
                                }
2075
                        } else if (access(argv[argn], R_OK)==0) {
2076 155 dgisselq
                                if (iself(argv[argn])) {
2077
                                        SECTION **secpp = NULL, *secp;
2078
                                        elfread(argv[argn], entry, secpp);
2079
                                        for(int i=0; secpp[i]->m_len; i++) {
2080
                                                secp = secpp[i];
2081
                                                assert(secp->m_start >= RAMBASE);
2082
                                                assert(secp->m_start+secp->m_len <= RAMBASE+MEMWORDS);
2083
                                                memcpy(&tb->m_mem[secp->m_start-RAMBASE],
2084
                                                        &secp->m_data,
2085
                                                        secp->m_len*sizeof(ZIPI));
2086
                                                mptr = secp->m_start+secp->m_len;
2087
                                        }
2088
                                } else {
2089 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
2090 58 dgisselq
                                int     nr, nv = 0;
2091 9 dgisselq
                                if (fp == NULL) {
2092
                                        printf("Cannot open %s\n", argv[argn]);
2093
                                        perror("O/S Err: ");
2094
                                        exit(-1);
2095 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
2096 9 dgisselq
                                fclose(fp);
2097 58 dgisselq
                                mptr+= nr;
2098
                                if (nr == 0) {
2099
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
2100
                                        perror("O/S  Err?:");
2101
                                        exit(-2);
2102
                                } for(int i=0; i<nr; i++) {
2103
                                        if (tb->m_mem[mptr-nr+i])
2104
                                                nv++;
2105
                                } if (nv == 0) {
2106
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
2107
                                        perror("O/S  Err?:");
2108
                                        exit(-2);
2109
                                }
2110 155 dgisselq
                                }
2111 58 dgisselq
                        } else {
2112
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
2113
                                exit(-2);
2114 9 dgisselq
                        }
2115
                }
2116
        }
2117
 
2118 58 dgisselq
 
2119
        assert(mptr > 0);
2120
 
2121 27 dgisselq
        if (autorun) {
2122
                bool    done = false;
2123 2 dgisselq
 
2124 27 dgisselq
                printf("Running in non-interactive mode\n");
2125
                tb->reset();
2126
                for(int i=0; i<2; i++)
2127
                        tb->tick();
2128
                tb->m_core->v__DOT__cmd_halt = 0;
2129 155 dgisselq
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
2130
                tb->wb_write(CMD_DATA, entry);
2131
                tb->wb_write(CMD_REG, 15);
2132 27 dgisselq
                while(!done) {
2133
                        tb->tick();
2134
 
2135
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
2136
                                // tb->m_core->v__DOT__cmd_halt = 0;
2137
                                // tb->m_core->v__DOT__cmd_step = 0;
2138
 
2139 34 dgisselq
                        /*
2140 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
2141
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
2142
                                tb->m_core->v__DOT__thecpu__DOT__upc,
2143
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
2144 34 dgisselq
                        */
2145 27 dgisselq
 
2146
                        done = (tb->test_success())||(tb->test_failure());
2147 43 dgisselq
                        done = done || signalled;
2148 27 dgisselq
                }
2149 36 dgisselq
        } else if (autostep) {
2150
                bool    done = false;
2151
 
2152
                printf("Running in non-interactive mode, via step commands\n");
2153 155 dgisselq
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
2154
                tb->wb_write(CMD_DATA, entry);
2155
                tb->wb_write(CMD_REG, 15);
2156 36 dgisselq
                while(!done) {
2157
                        tb->wb_write(CMD_REG, CMD_STEP);
2158
                        done = (tb->test_success())||(tb->test_failure());
2159 43 dgisselq
                        done = done || signalled;
2160 36 dgisselq
                }
2161 27 dgisselq
        } else { // Interactive
2162
                initscr();
2163
                raw();
2164
                noecho();
2165
                keypad(stdscr, true);
2166
 
2167 69 dgisselq
                // tb->reset();
2168
                // for(int i=0; i<2; i++)
2169
                        // tb->tick();
2170
                tb->m_core->v__DOT__cmd_reset = 1;
2171 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
2172
 
2173 155 dgisselq
                tb->jump_to(entry);
2174
 
2175 76 dgisselq
                // For debugging purposes: do we wish to skip some number of
2176
                // instructions to fast forward to a time of interest??
2177 155 dgisselq
                for(int i=0; i<0x3f80; i++) {
2178 76 dgisselq
                        tb->m_core->v__DOT__cmd_halt = 0;
2179
                        tb->tick();
2180
                }
2181
 
2182 27 dgisselq
                int     chv = 'q';
2183
 
2184 43 dgisselq
                bool    done = false, halted = true, manual = true,
2185
                        high_speed = false;
2186 2 dgisselq
 
2187
                halfdelay(1);
2188 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
2189 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
2190
                        // tb->show_state();
2191
 
2192
                while(!done) {
2193 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
2194 87 dgisselq
                                // chv = getch();
2195
 
2196 43 dgisselq
                                struct  pollfd  fds[1];
2197
                                fds[0].fd = STDIN_FILENO;
2198
                                fds[0].events = POLLIN;
2199 87 dgisselq
 
2200 43 dgisselq
                                if (poll(fds, 1, 0) > 0)
2201
                                        chv = getch();
2202
                                else
2203
                                        chv = ERR;
2204 87 dgisselq
 
2205 43 dgisselq
                        } else {
2206
                                chv = getch();
2207
                        }
2208 2 dgisselq
                        switch(chv) {
2209
                        case 'h': case 'H':
2210
                                tb->wb_write(CMD_REG, CMD_HALT);
2211
                                if (!halted)
2212
                                        erase();
2213
                                halted = true;
2214
                                break;
2215 43 dgisselq
                        case 'G':
2216
                                high_speed = true;
2217 87 dgisselq
                                // cbreak();
2218 43 dgisselq
                        case 'g':
2219 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
2220
                                if (halted)
2221
                                        erase();
2222
                                halted = false;
2223
                                manual = false;
2224
                                break;
2225 43 dgisselq
                        case 'm':
2226
                                tb->show_user_timers(false);
2227
                                break;
2228 2 dgisselq
                        case 'q': case 'Q':
2229
                                done = true;
2230
                                break;
2231
                        case 'r': case 'R':
2232 36 dgisselq
                                if (manual)
2233
                                        tb->reset();
2234
                                else
2235
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
2236 2 dgisselq
                                halted = true;
2237
                                erase();
2238
                                break;
2239 39 dgisselq
                        case 's':
2240 34 dgisselq
                                if (!halted)
2241 27 dgisselq
                                        erase();
2242 76 dgisselq
                                tb->step();
2243 2 dgisselq
                                manual = false;
2244 34 dgisselq
                                halted = true;
2245 87 dgisselq
                                // if (high_speed)
2246
                                        // halfdelay(1);
2247 43 dgisselq
                                high_speed = false;
2248 2 dgisselq
                                break;
2249 39 dgisselq
                        case 'S':
2250 34 dgisselq
                                if ((!manual)||(halted))
2251 27 dgisselq
                                        erase();
2252 2 dgisselq
                                manual = true;
2253 39 dgisselq
                                halted = true;
2254 87 dgisselq
                                // if (high_speed)
2255
                                        // halfdelay(1);
2256 43 dgisselq
                                high_speed = false;
2257 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
2258
                                tb->m_core->v__DOT__cmd_step = 1;
2259
                                tb->eval();
2260
                                tb->tick();
2261
                                break;
2262
                        case 'T': // 
2263
                                if ((!manual)||(halted))
2264
                                        erase();
2265
                                manual = true;
2266
                                halted = true;
2267 87 dgisselq
                                // if (high_speed)
2268
                                        // halfdelay(1);
2269 43 dgisselq
                                high_speed = false;
2270 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
2271
                                tb->m_core->v__DOT__cmd_step = 0;
2272
                                tb->eval();
2273
                                tb->tick();
2274
                                break;
2275
                        case 't':
2276
                                if ((!manual)||(halted))
2277
                                        erase();
2278
                                manual = true;
2279 34 dgisselq
                                halted = false;
2280 87 dgisselq
                                // if (high_speed)
2281
                                        // halfdelay(1);
2282 43 dgisselq
                                high_speed = false;
2283 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
2284 76 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
2285 27 dgisselq
                //              tb->m_core->v__DOT__cmd_step = 0;
2286 2 dgisselq
                                tb->tick();
2287
                                break;
2288 43 dgisselq