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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 27

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 2 dgisselq
 
41
#include <ctype.h>
42
#include <ncurses.h>
43
 
44
#include "verilated.h"
45
#include "Vzipsystem.h"
46
 
47
#include "testb.h"
48
// #include "twoc.h"
49
// #include "qspiflashsim.h"
50
#include "memsim.h"
51
#include "zopcodes.h"
52
#include "zparser.h"
53
 
54
#define CMD_REG         0
55
#define CMD_DATA        1
56
#define CMD_HALT        (1<<10)
57
#define CMD_STALL       (1<<9)
58
#define CMD_STEP        (1<<8)
59
#define CMD_INT         (1<<7)
60
#define CMD_RESET       (1<<6)
61
 
62
 
63
// No particular "parameters" need definition or redefinition here.
64
class   ZIPPY_TB : public TESTB<Vzipsystem> {
65
public:
66 9 dgisselq
        unsigned long   m_mem_size;
67 2 dgisselq
        MEMSIM          m_mem;
68
        // QSPIFLASHSIM m_flash;
69
        FILE            *dbg_fp;
70
        bool            dbg_flag, bomb;
71
 
72 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
73 2 dgisselq
                //dbg_fp = fopen("dbg.txt", "w");
74
                dbg_fp = NULL;
75
                dbg_flag = false;
76
                bomb = false;
77
        }
78
 
79
        void    reset(void) {
80
                // m_flash.debug(false);
81
                TESTB<Vzipsystem>::reset();
82
        }
83
 
84
        bool    on_tick(void) {
85
                tick();
86
                return true;
87
        }
88
 
89
        void    showval(int y, int x, const char *lbl, unsigned int v) {
90
                mvprintw(y,x, "%s: 0x%08x", lbl, v);
91
        }
92
 
93
        void    dispreg(int y, int x, const char *n, unsigned int v) {
94
                // 4,4,8,1 = 17 of 20, +3 = 19
95
                mvprintw(y, x, "%s: 0x%08x", n, v);
96
        }
97
 
98
        void    showreg(int y, int x, const char *n, int r) {
99
                // 4,4,8,1 = 17 of 20, +3 = 19
100
                mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
101
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
102
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
103
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
104
                        ?'a':' ');
105
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
106
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
107
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
108
                        ?'b':' ');
109
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
110
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
111
                        ?'W':' ');
112
        }
113
 
114
        void    showins(int y, const char *lbl, const int ce, const int valid,
115
                        const int gie, const int stall, const unsigned int pc) {
116
                char    line[80];
117
 
118
                if (ce)
119
                        mvprintw(y, 0, "Ck ");
120
                else
121
                        mvprintw(y, 0, "   ");
122
                if (stall)
123
                        printw("Stl ");
124
                else
125
                        printw("    ");
126
                printw("%s: 0x%08x", lbl, pc);
127
 
128
                if (valid) {
129
                        if (gie) attroff(A_BOLD);
130
                        else    attron(A_BOLD);
131
                        zipi_to_string(m_mem[pc], line);
132 27 dgisselq
                        printw("  %-24s", &line[1]);
133 2 dgisselq
                } else {
134
                        attroff(A_BOLD);
135
                        printw("  (0x%08x)%28s", m_mem[pc],"");
136
                }
137
                attroff(A_BOLD);
138
        }
139
 
140
        void    dbgins(const char *lbl, const int ce, const int valid,
141
                        const int gie, const int stall, const unsigned int pc) {
142
                char    line[80];
143
 
144
                if (!dbg_fp)
145
                        return;
146
 
147
                if (ce)
148
                        fprintf(dbg_fp, "%s Ck ", lbl);
149
                else
150
                        fprintf(dbg_fp, "%s    ", lbl);
151
                if (stall)
152
                        fprintf(dbg_fp, "Stl ");
153
                else
154
                        fprintf(dbg_fp, "    ");
155
                fprintf(dbg_fp, "0x%08x:  ", pc);
156
 
157
                if (valid) {
158
                        zipi_to_string(m_mem[pc], line);
159
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
160
                } else {
161
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
162
                }
163
        }
164
 
165
        void    show_state(void) {
166
                int     ln= 0;
167
 
168
                mvprintw(ln,0, "Peripherals-SS"); ln++;
169
                /*
170
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
171
                        mvprintw(ln, 17, "%s%s",
172
                                ((m_core->v__DOT__sys_cyc)
173
                                &&(m_core->v__DOT__sys_we)
174
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
175
                                (m_core->v__DOT__trap_int)?"I":" ");
176
                */
177
                showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
178
                showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
179
                showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
180
                showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
181
 
182
                ln++;
183
                showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
184
                showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
185
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
186
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
187
 
188
                ln++;
189
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
190 9 dgisselq
                showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
191 2 dgisselq
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
192 9 dgisselq
                showval(ln,61, "UICT", m_core->v__DOT__uic_data);
193 2 dgisselq
 
194
                ln++;
195
                mvprintw(ln, 40, "%s %s",
196
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
197
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
198
                mvprintw(ln, 40, "%s %s %s 0x%02x",
199
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
200
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
201
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
202
                        (m_core->v__DOT__cmd_addr)&0x3f);
203
                if (m_core->v__DOT__thecpu__DOT__gie)
204
                        attroff(A_BOLD);
205
                else
206
                        attron(A_BOLD);
207
                mvprintw(ln, 0, "Supervisor Registers");
208
                ln++;
209
 
210
                showreg(ln, 1, "sR0 ", 0);
211
                showreg(ln,21, "sR1 ", 1);
212
                showreg(ln,41, "sR2 ", 2);
213
                showreg(ln,61, "sR3 ", 3); ln++;
214
 
215
                showreg(ln, 1, "sR4 ", 4);
216
                showreg(ln,21, "sR5 ", 5);
217
                showreg(ln,41, "sR6 ", 6);
218
                showreg(ln,61, "sR7 ", 7); ln++;
219
 
220
                showreg(ln, 1, "sR8 ",  8);
221
                showreg(ln,21, "sR9 ",  9);
222
                showreg(ln,41, "sR10", 10);
223
                showreg(ln,61, "sR11", 11); ln++;
224
 
225
                showreg(ln, 1, "sR12", 12);
226
                showreg(ln,21, "sSP ", 13);
227 27 dgisselq
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s%s",
228
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
229
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
230
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
231
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
232 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
233
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
234
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
235
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
236
                mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
237
                ln++;
238
 
239
                if (m_core->v__DOT__thecpu__DOT__gie)
240
                        attron(A_BOLD);
241
                else
242
                        attroff(A_BOLD);
243
                mvprintw(ln, 0, "User Registers"); ln++;
244
                showreg(ln, 1, "uR0 ", 16);
245
                showreg(ln,21, "uR1 ", 17);
246
                showreg(ln,41, "uR2 ", 18);
247
                showreg(ln,61, "uR3 ", 19); ln++;
248
 
249
                showreg(ln, 1, "uR4 ", 20);
250
                showreg(ln,21, "uR5 ", 21);
251
                showreg(ln,41, "uR6 ", 22);
252
                showreg(ln,61, "uR7 ", 23); ln++;
253
 
254
                showreg(ln, 1, "uR8 ", 24);
255
                showreg(ln,21, "uR9 ", 25);
256
                showreg(ln,41, "uR10", 26);
257
                showreg(ln,61, "uR11", 27); ln++;
258
 
259
                showreg(ln, 1, "uR12", 28);
260
                showreg(ln,21, "uSP ", 29);
261 27 dgisselq
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s%s",
262
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
263
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
264
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
265
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
266 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
267
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
268
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
269
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
270
                mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
271
 
272
                attroff(A_BOLD);
273
                ln+=1;
274
 
275 4 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
276 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
277
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
278
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
279
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
280 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
281
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
282 2 dgisselq
                ln++;
283
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
284
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
285
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
286
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
287
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
288
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
289
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
290
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
291
                        (m_core->v__DOT__wb_data)); ln++;
292
 
293
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
294
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
295
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
296
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
297
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
298
                        (m_core->v__DOT__thecpu__DOT__mem_data),
299
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
300
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
301
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
302
 
303
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
304
                        (m_core->o_wb_cyc)?"CYC":"   ",
305
                        (m_core->o_wb_stb)?"STB":"   ",
306
                        (m_core->o_wb_we )?"WE":"  ",
307
                        (m_core->o_wb_addr),
308
                        (m_core->o_wb_data),
309
                        (m_core->i_wb_ack)?"ACK":"   ",
310
                        (m_core->i_wb_stall)?"STL":"   ",
311
                        (m_core->i_wb_data)); ln+=2;
312
 
313
                showins(ln, "I ",
314
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
315
                        m_core->v__DOT__thecpu__DOT__pf_valid,
316
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
317
                        m_core->v__DOT__thecpu__DOT__gie,
318
                        0,
319
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
320
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
321
 
322
                showins(ln, "Dc",
323
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
324
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
325
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
326
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
327
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
328
 
329
                showins(ln, "Op",
330
                        m_core->v__DOT__thecpu__DOT__op_ce,
331
                        m_core->v__DOT__thecpu__DOT__opvalid,
332
                        m_core->v__DOT__thecpu__DOT__op_gie,
333
                        m_core->v__DOT__thecpu__DOT__op_stall,
334
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
335
 
336
                showins(ln, "Al",
337
                        m_core->v__DOT__thecpu__DOT__alu_ce,
338
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
339
                        m_core->v__DOT__thecpu__DOT__alu_gie,
340
                        m_core->v__DOT__thecpu__DOT__alu_stall,
341
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
342
 
343 27 dgisselq
                mvprintw(ln-5, 48,"%s %s",
344
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
345
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
346 2 dgisselq
                mvprintw(ln-4, 48,
347
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
348
                printw("(%s:%02x,%x)",
349
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
350
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
351
                        (m_core->v__DOT__thecpu__DOT__op_gie)
352
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
353
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
354
 
355
                printw("(%s%s%s:%02x)",
356
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
357
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
358
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
359
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
360
                /*
361
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
362
                        m_core->v__DOT__thecpu__DOT__dcdI);
363
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
364
                        m_core->v__DOT__thecpu__DOT__opB);
365
                */
366 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
367 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
368 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
369
                        m_core->v__DOT__thecpu__DOT__r_opB);
370
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
371
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
372
                else
373
                        printw("%8s","");
374 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
375 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
376 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
377
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
378
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
379
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
380
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
381
        }
382
 
383
        unsigned int    cmd_read(unsigned int a) {
384
                if (dbg_fp) {
385
                        dbg_flag= true;
386
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
387
                }
388
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
389
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
390
                        ;
391
                unsigned int v = wb_read(CMD_DATA);
392
 
393
                if (dbg_flag)
394
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
395
                                v);
396
                dbg_flag = false;
397
                return v;
398
        }
399
 
400 27 dgisselq
        bool    halted(void) {
401
                return (m_core->v__DOT__cmd_halt != 0);
402
        }
403
 
404 2 dgisselq
        void    read_state(void) {
405
                int     ln= 0;
406
 
407
                mvprintw(ln,0, "Peripherals-RS"); ln++;
408
                showval(ln, 1, "PIC ", cmd_read(32+ 0));
409
                showval(ln,21, "WDT ", cmd_read(32+ 1));
410
                showval(ln,41, "CACH", cmd_read(32+ 2));
411
                showval(ln,61, "PIC2", cmd_read(32+ 3));
412
                ln++;
413
                showval(ln, 1, "TMRA", cmd_read(32+ 4));
414
                showval(ln,21, "TMRB", cmd_read(32+ 5));
415
                showval(ln,41, "TMRC", cmd_read(32+ 6));
416
                showval(ln,61, "JIF ", cmd_read(32+ 7));
417
 
418
                ln++;
419
                showval(ln, 1, "UTSK", cmd_read(32+12));
420
                showval(ln,21, "UMST", cmd_read(32+13));
421
                showval(ln,41, "UPST", cmd_read(32+14));
422
                showval(ln,61, "UAST", cmd_read(32+15));
423
 
424
                ln++;
425
                ln++;
426
                unsigned int cc = cmd_read(14);
427
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
428
                        m_core->v__DOT__thecpu__DOT__gie);
429
                if (cc & 0x020)
430
                        attroff(A_BOLD);
431
                else
432
                        attron(A_BOLD);
433
                mvprintw(ln, 0, "Supervisor Registers");
434
                ln++;
435
 
436
                dispreg(ln, 1, "sR0 ", cmd_read(0));
437
                dispreg(ln,21, "sR1 ", cmd_read(1));
438
                dispreg(ln,41, "sR2 ", cmd_read(2));
439
                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
440
 
441
                dispreg(ln, 1, "sR4 ", cmd_read(4));
442
                dispreg(ln,21, "sR5 ", cmd_read(5));
443
                dispreg(ln,41, "sR6 ", cmd_read(6));
444
                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
445
 
446
                dispreg(ln, 1, "sR8 ", cmd_read( 8));
447
                dispreg(ln,21, "sR9 ", cmd_read( 9));
448
                dispreg(ln,41, "sR10", cmd_read(10));
449
                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
450
 
451
                dispreg(ln, 1, "sR12", cmd_read(12));
452
                dispreg(ln,21, "sSP ", cmd_read(13));
453
 
454
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
455
                        (cc & 0x040)?"STP":"   ",
456
                        (cc & 0x020)?"GIE":"   ",
457
                        (cc & 0x010)?"SLP":"   ",
458
                        (cc&8)?"V":" ",
459
                        (cc&4)?"N":" ",
460
                        (cc&2)?"C":" ",
461
                        (cc&1)?"Z":" ");
462
                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
463
                ln++;
464
 
465
                if (cc & 0x020)
466
                        attron(A_BOLD);
467
                else
468
                        attroff(A_BOLD);
469
                mvprintw(ln, 0, "User Registers"); ln++;
470
                dispreg(ln, 1, "uR0 ", cmd_read(16));
471
                dispreg(ln,21, "uR1 ", cmd_read(17));
472
                dispreg(ln,41, "uR2 ", cmd_read(18));
473
                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
474
 
475
                dispreg(ln, 1, "uR4 ", cmd_read(20));
476
                dispreg(ln,21, "uR5 ", cmd_read(21));
477
                dispreg(ln,41, "uR6 ", cmd_read(22));
478
                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
479
 
480
                dispreg(ln, 1, "uR8 ", cmd_read(24));
481
                dispreg(ln,21, "uR9 ", cmd_read(25));
482
                dispreg(ln,41, "uR10", cmd_read(26));
483
                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
484
 
485
                dispreg(ln, 1, "uR12", cmd_read(28));
486
                dispreg(ln,21, "uSP ", cmd_read(29));
487
                cc = cmd_read(30);
488
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
489
                        (cc&0x040)?"STP":"   ",
490
                        (cc&0x020)?"GIE":"   ",
491
                        (cc&0x010)?"SLP":"   ",
492
                        (cc&8)?"V":" ",
493
                        (cc&4)?"N":" ",
494
                        (cc&2)?"C":" ",
495
                        (cc&1)?"Z":" ");
496
                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
497
 
498
                attroff(A_BOLD);
499
                ln+=2;
500
 
501
                ln+=3;
502
 
503
                showins(ln, "I ",
504
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
505
                        m_core->v__DOT__thecpu__DOT__pf_valid,
506
                        m_core->v__DOT__thecpu__DOT__gie,
507
                        0,
508
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
509
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
510
 
511
                showins(ln, "Dc",
512
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
513
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
514
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
515
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
516
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
517
 
518
                showins(ln, "Op",
519
                        m_core->v__DOT__thecpu__DOT__op_ce,
520
                        m_core->v__DOT__thecpu__DOT__opvalid,
521
                        m_core->v__DOT__thecpu__DOT__op_gie,
522
                        m_core->v__DOT__thecpu__DOT__op_stall,
523
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
524
 
525
                showins(ln, "Al",
526
                        m_core->v__DOT__thecpu__DOT__alu_ce,
527
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
528
                        m_core->v__DOT__thecpu__DOT__alu_gie,
529
                        m_core->v__DOT__thecpu__DOT__alu_stall,
530
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
531
        }
532
        void    tick(void) {
533
                int gie = m_core->v__DOT__thecpu__DOT__gie;
534
                /*
535
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
536
                                                m_core->o_qspi_sck,
537
                                                m_core->o_qspi_dat);
538
                */
539
 
540 11 dgisselq
                int stb = m_core->o_wb_stb;
541
                if ((m_core->o_wb_addr & (-1<<20))!=1)
542
                        stb = 0;
543 2 dgisselq
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
544
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
545
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
546 11 dgisselq
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
547
                        m_core->i_wb_ack = 1;
548 2 dgisselq
 
549
                if ((dbg_flag)&&(dbg_fp)) {
550
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
551
                                (m_core->i_dbg_cyc)?"CYC":"   ",
552
                                (m_core->i_dbg_stb)?"STB":
553
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
554
                                ((m_core->i_dbg_we)?"WE":"  "),
555
                                (m_core->i_dbg_addr),0,
556
                                m_core->i_dbg_data,
557
                                (m_core->o_dbg_ack)?"ACK":"   ",
558
                                (m_core->o_dbg_stall)?"STALL":"     ",
559
                                (m_core->o_dbg_data),
560
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
561
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
562
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
563
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
564
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
565
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
566
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
567
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
568
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
569
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
570
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
571
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
572
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
573
                                (m_core->v__DOT__sys_we)?"WE":"  ",
574
                                (m_core->v__DOT__sys_addr),
575
                                (m_core->v__DOT__dbg_addr),
576
                                (m_core->v__DOT__sys_data),
577
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
578
                                (m_core->v__DOT__wb_data));
579
                }
580
 
581
                if (dbg_fp)
582
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
583
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
584
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
585
                                m_core->v__DOT__thecpu__DOT__op_ce,
586
                                m_core->v__DOT__thecpu__DOT__op_pc,
587
                                m_core->v__DOT__thecpu__DOT__dcdA,
588
                                m_core->v__DOT__thecpu__DOT__opR,
589
                                m_core->v__DOT__cmd_halt,
590
                                m_core->v__DOT__cpu_halt,
591
                                m_core->v__DOT__thecpu__DOT__alu_ce,
592
                                m_core->v__DOT__thecpu__DOT__alu_valid,
593
                                m_core->v__DOT__thecpu__DOT__alu_wr,
594
                                m_core->v__DOT__thecpu__DOT__alu_reg,
595
                                m_core->v__DOT__thecpu__DOT__ipc,
596
                                m_core->v__DOT__thecpu__DOT__upc);
597
 
598
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
599
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
600
                                m_core->v__DOT__pic_interrupt,
601
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
602
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
603
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
604
                                m_core->v__DOT__cmd_addr,
605
                                m_core->v__DOT__dbg_idata,
606
                                m_core->v__DOT__thecpu__DOT__master_ce,
607
                                m_core->v__DOT__thecpu__DOT__alu_wr,
608
                                m_core->v__DOT__thecpu__DOT__alu_valid,
609
                                m_core->v__DOT__thecpu__DOT__mem_valid);
610
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
611
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
612
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
613
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
614
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
615
                                m_core->v__DOT__cmd_addr,
616
                                m_core->v__DOT__dbg_idata,
617
                                m_core->v__DOT__thecpu__DOT__master_ce,
618
                                m_core->v__DOT__thecpu__DOT__alu_wr,
619
                                m_core->v__DOT__thecpu__DOT__alu_valid,
620
                                m_core->v__DOT__thecpu__DOT__mem_valid,
621
                                m_core->v__DOT__thecpu__DOT__w_iflags,
622
                                m_core->v__DOT__thecpu__DOT__w_uflags);
623
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
624
                                m_core->v__DOT__thecpu__DOT__break_en,
625
                                m_core->v__DOT__thecpu__DOT__op_break);
626
                }
627
 
628
                TESTB<Vzipsystem>::tick();
629
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
630
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
631
                                (gie)?"User":"Supervisor",
632
                                (gie)?"Supervisor":"User",
633
                                m_core->v__DOT__thecpu__DOT__ipc,
634
                                m_core->v__DOT__thecpu__DOT__upc,
635
                                m_core->v__DOT__thecpu__DOT__pf_pc);
636
                } if (dbg_fp) {
637
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
638
                                m_core->v__DOT__thecpu__DOT__opvalid,
639
                                m_core->v__DOT__thecpu__DOT__op_gie,
640
                                m_core->v__DOT__thecpu__DOT__op_stall,
641
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
642
                        dbgins("Al - ",
643
                                m_core->v__DOT__thecpu__DOT__alu_ce,
644
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
645
                                m_core->v__DOT__thecpu__DOT__alu_gie,
646
                                m_core->v__DOT__thecpu__DOT__alu_stall,
647
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
648
 
649
                }
650
        }
651
 
652
        bool    test_success(void) {
653
                return ((!m_core->v__DOT__thecpu__DOT__gie)
654
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
655
        }
656
 
657
        bool    test_failure(void) {
658
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
659
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
660
                                == 0x2f0f7fff));
661
        }
662
 
663
        void    wb_write(unsigned a, unsigned int v) {
664
                mvprintw(0,35, "%40s", "");
665
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
666
                m_core->i_dbg_cyc = 1;
667
                m_core->i_dbg_stb = 1;
668
                m_core->i_dbg_we  = 1;
669
                m_core->i_dbg_addr = a & 1;
670
                m_core->i_dbg_data = v;
671
 
672
                tick();
673
                while(m_core->o_dbg_stall)
674
                        tick();
675
 
676
                m_core->i_dbg_stb = 0;
677
                while(!m_core->o_dbg_ack)
678
                        tick();
679
 
680
                // Release the bus
681
                m_core->i_dbg_cyc = 0;
682
                m_core->i_dbg_stb = 0;
683
                tick();
684
                mvprintw(0,35, "%40s", "");
685
                mvprintw(0,40, "wb_write -- complete");
686
        }
687
 
688
        unsigned long   wb_read(unsigned a) {
689
                unsigned int    v;
690
                mvprintw(0,35, "%40s", "");
691
                mvprintw(0,40, "wb_read(0x%08x)", a);
692
                m_core->i_dbg_cyc = 1;
693
                m_core->i_dbg_stb = 1;
694
                m_core->i_dbg_we  = 0;
695
                m_core->i_dbg_addr = a & 1;
696
 
697
                tick();
698
                while(m_core->o_dbg_stall)
699
                        tick();
700
 
701
                m_core->i_dbg_stb = 0;
702
                while(!m_core->o_dbg_ack)
703
                        tick();
704
                v = m_core->o_dbg_data;
705
 
706
                // Release the bus
707
                m_core->i_dbg_cyc = 0;
708
                m_core->i_dbg_stb = 0;
709
                tick();
710
 
711
                mvprintw(0,35, "%40s", "");
712
                mvprintw(0,40, "wb_read = 0x%08x", v);
713
 
714
                return v;
715
        }
716
 
717
};
718
 
719 27 dgisselq
void    usage(void) {
720
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
721
        printf("\n");
722
        printf("\tWhere testfile.out is an output file from the assembler.\n");
723
        printf("\t-a\tSets the testbench to run automatically without any\n");
724
        printf("\t\tuser interaction.\n");
725
        printf("\n");
726
        printf("\tUser Commands:\n");
727
        printf("\t\tWhen the test bench is run interactively, the following\n");
728
        printf("\t\tkey strokes are recognized:\n");
729
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
730
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
731
        printf("\t\t\tuser intervention.\n");
732
        printf("\t\t\'q\'\tQuit the simulation.\n");
733
        printf("\t\t\'r\'\tReset the processor.\n");
734
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
735
        printf("\t\t\tThis may consume more than one tick.\n");
736
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
737
}
738 2 dgisselq
 
739
int     main(int argc, char **argv) {
740
        Verilated::commandArgs(argc, argv);
741
        ZIPPY_TB        *tb = new ZIPPY_TB();
742 27 dgisselq
        bool            autorun = false, exit_on_done = false;
743 2 dgisselq
 
744
        // mem[0x00000] = 0xbe000010; // Halt instruction
745
        unsigned int mptr = 0;
746
 
747 9 dgisselq
        if (argc <= 1) {
748 27 dgisselq
                usage();
749
                exit(-1);
750 9 dgisselq
        } else {
751
                for(int argn=1; argn<argc; argn++) {
752 27 dgisselq
                        if (argv[argn][0] == '-') {
753
                                switch(argv[argn][1]) {
754
                                case 'a':
755
                                        autorun = true;
756
                                        break;
757
                                case 'e':
758
                                        exit_on_done = true;
759
                                        break;
760
                                case 'h':
761
                                        usage();
762
                                        exit(0);
763
                                        break;
764
                                default:
765
                                        usage();
766
                                        exit(-1);
767
                                        break;
768
                                }
769
                        } else if (access(argv[argn], R_OK)==0) {
770 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
771
                                if (fp == NULL) {
772
                                        printf("Cannot open %s\n", argv[argn]);
773
                                        perror("O/S Err: ");
774
                                        exit(-1);
775
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
776
                                fclose(fp);
777
                        }
778
                }
779
        }
780
 
781 27 dgisselq
        if (autorun) {
782
                bool    done = false;
783 2 dgisselq
 
784 27 dgisselq
                printf("Running in non-interactive mode\n");
785
                tb->reset();
786
                for(int i=0; i<2; i++)
787
                        tb->tick();
788
                tb->m_core->v__DOT__cmd_halt = 0;
789
                while(!done) {
790
                        tb->tick();
791
 
792
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
793
                                // tb->m_core->v__DOT__cmd_halt = 0;
794
                                // tb->m_core->v__DOT__cmd_step = 0;
795
 
796
                        printf("PC = %08x:%08x (%08x)\n",
797
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
798
                                tb->m_core->v__DOT__thecpu__DOT__upc,
799
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
800
 
801
                        done = (tb->test_success())||(tb->test_failure());
802
                }
803
        } else { // Interactive
804
                initscr();
805
                raw();
806
                noecho();
807
                keypad(stdscr, true);
808
 
809
                tb->reset();
810
                for(int i=0; i<2; i++)
811
                        tb->tick();
812
                tb->m_core->v__DOT__cmd_halt = 0;
813
 
814
                int     chv = 'q';
815
 
816 2 dgisselq
                bool    done = false, halted = true, manual = true;
817
 
818
                halfdelay(1);
819 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
820 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
821
                        // tb->show_state();
822
 
823
                while(!done) {
824
                        chv = getch();
825
                        switch(chv) {
826
                        case 'h': case 'H':
827
                                tb->wb_write(CMD_REG, CMD_HALT);
828
                                if (!halted)
829
                                        erase();
830
                                halted = true;
831
                                break;
832
                        case 'g': case 'G':
833
                                tb->wb_write(CMD_REG, 0);
834
                                if (halted)
835
                                        erase();
836
                                halted = false;
837
                                manual = false;
838
                                break;
839
                        case 'q': case 'Q':
840
                                done = true;
841
                                break;
842
                        case 'r': case 'R':
843
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
844
                                halted = true;
845
                                erase();
846
                                break;
847
                        case 's': case 'S':
848 27 dgisselq
                                if (manual)
849
                                        erase();
850 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
851
                                manual = false;
852
                                break;
853
                        case 't': case 'T':
854 27 dgisselq
                                if (!manual)
855
                                        erase();
856 2 dgisselq
                                manual = true;
857 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
858
                //              tb->m_core->v__DOT__cmd_halt = 0;
859
                //              tb->m_core->v__DOT__cmd_step = 0;
860 2 dgisselq
                                tb->tick();
861
                                break;
862
                        case ERR:
863
                        default:
864
                                if (!manual)
865
                                        tb->tick();
866
                        }
867
 
868
                        if (manual) {
869
                                tb->show_state();
870
                        } else if (halted) {
871
                                if (tb->dbg_fp)
872
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
873
                                tb->read_state();
874
                        } else
875
                                tb->show_state();
876
 
877
                        if (tb->m_core->i_rst)
878
                                done =true;
879
                        if (tb->bomb)
880
                                done = true;
881 27 dgisselq
 
882
                        if (exit_on_done) {
883
                                if (tb->test_success())
884
                                        done = true;
885
                                if (tb->test_failure())
886
                                        done = true;
887
                        }
888 2 dgisselq
                }
889 27 dgisselq
                endwin();
890
        }
891
#ifdef  MANUAL_STEPPING_MODE
892
         else { // Manual stepping mode
893 2 dgisselq
                tb->show_state();
894
 
895
                while('q' != tolower(chv = getch())) {
896
                        tb->tick();
897
                        tb->show_state();
898
 
899
                        if (tb->test_success())
900
                                break;
901
                        else if (tb->test_failure())
902
                                break;
903
                }
904
        }
905 27 dgisselq
#endif
906 2 dgisselq
 
907 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
908
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
909
        if (tb->m_core->v__DOT__mtc_data != 0)
910
                printf("Instructions / Clock: %.2f\n",
911
                        (double)tb->m_core->v__DOT__mic_data
912
                        / (double)tb->m_core->v__DOT__mtc_data);
913 2 dgisselq
        if (tb->test_success())
914
                printf("SUCCESS!\n");
915
        else if (tb->test_failure())
916
                printf("TEST FAILED!\n");
917 27 dgisselq
        else
918
                printf("User quit\n");
919 2 dgisselq
        exit(0);
920
}
921
 

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