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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 39

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 2 dgisselq
 
41
#include <ctype.h>
42
#include <ncurses.h>
43
 
44
#include "verilated.h"
45
#include "Vzipsystem.h"
46 39 dgisselq
#include "cpudefs.h"
47 2 dgisselq
 
48
#include "testb.h"
49
// #include "twoc.h"
50
// #include "qspiflashsim.h"
51
#include "memsim.h"
52
#include "zopcodes.h"
53
#include "zparser.h"
54
 
55
#define CMD_REG         0
56
#define CMD_DATA        1
57
#define CMD_HALT        (1<<10)
58
#define CMD_STALL       (1<<9)
59
#define CMD_INT         (1<<7)
60
#define CMD_RESET       (1<<6)
61 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
62 2 dgisselq
 
63 34 dgisselq
#define KEY_ESCAPE      27
64
#define KEY_RETURN      10
65 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
66 2 dgisselq
 
67
// No particular "parameters" need definition or redefinition here.
68
class   ZIPPY_TB : public TESTB<Vzipsystem> {
69
public:
70 9 dgisselq
        unsigned long   m_mem_size;
71 2 dgisselq
        MEMSIM          m_mem;
72
        // QSPIFLASHSIM m_flash;
73
        FILE            *dbg_fp;
74
        bool            dbg_flag, bomb;
75 34 dgisselq
        int             m_cursor;
76 2 dgisselq
 
77 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
78 36 dgisselq
                if (true) {
79
                        dbg_fp = fopen("dbg.txt", "w");
80
                        dbg_flag = true;
81
                } else {
82
                        dbg_fp = NULL;
83
                        dbg_flag = false;
84
                }
85 2 dgisselq
                bomb = false;
86 34 dgisselq
                m_cursor = 0;
87 2 dgisselq
        }
88
 
89
        void    reset(void) {
90
                // m_flash.debug(false);
91
                TESTB<Vzipsystem>::reset();
92
        }
93
 
94
        bool    on_tick(void) {
95
                tick();
96
                return true;
97
        }
98
 
99 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
100
                if (c)
101
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
102
                else
103
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
104 2 dgisselq
        }
105
 
106 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
107 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
108 34 dgisselq
                if (c)
109
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
110
                else
111
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
112 2 dgisselq
        }
113
 
114 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
115 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
116 34 dgisselq
                if (c)
117
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
118
                else
119
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
120 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
121
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
122
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
123 34 dgisselq
                        ?'a':((c)?'<':' '));
124 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
125
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
126
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
127 34 dgisselq
                        ?'b':((c)?'<':' '));
128 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
129
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
130 34 dgisselq
                        ?'W':((c)?'<':' '));
131 2 dgisselq
        }
132
 
133
        void    showins(int y, const char *lbl, const int ce, const int valid,
134
                        const int gie, const int stall, const unsigned int pc) {
135
                char    line[80];
136
 
137
                if (ce)
138
                        mvprintw(y, 0, "Ck ");
139
                else
140
                        mvprintw(y, 0, "   ");
141
                if (stall)
142
                        printw("Stl ");
143
                else
144
                        printw("    ");
145
                printw("%s: 0x%08x", lbl, pc);
146
 
147
                if (valid) {
148
                        if (gie) attroff(A_BOLD);
149
                        else    attron(A_BOLD);
150
                        zipi_to_string(m_mem[pc], line);
151 27 dgisselq
                        printw("  %-24s", &line[1]);
152 2 dgisselq
                } else {
153
                        attroff(A_BOLD);
154
                        printw("  (0x%08x)%28s", m_mem[pc],"");
155
                }
156
                attroff(A_BOLD);
157
        }
158
 
159
        void    dbgins(const char *lbl, const int ce, const int valid,
160
                        const int gie, const int stall, const unsigned int pc) {
161
                char    line[80];
162
 
163
                if (!dbg_fp)
164
                        return;
165
 
166
                if (ce)
167
                        fprintf(dbg_fp, "%s Ck ", lbl);
168
                else
169
                        fprintf(dbg_fp, "%s    ", lbl);
170
                if (stall)
171
                        fprintf(dbg_fp, "Stl ");
172
                else
173
                        fprintf(dbg_fp, "    ");
174
                fprintf(dbg_fp, "0x%08x:  ", pc);
175
 
176
                if (valid) {
177
                        zipi_to_string(m_mem[pc], line);
178
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
179
                } else {
180
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
181
                }
182
        }
183
 
184
        void    show_state(void) {
185
                int     ln= 0;
186
 
187
                mvprintw(ln,0, "Peripherals-SS"); ln++;
188 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
189 36 dgisselq
                printw(" %s",
190
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
191
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
192
                        );
193 39 dgisselq
#endif
194
 
195
#ifdef  OPT_EARLY_BRANCHING
196
                printw(" %s%s",
197 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
198 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
199
#endif
200 36 dgisselq
 
201
                /*
202 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
203
                        mvprintw(ln, 17, "%s%s",
204
                                ((m_core->v__DOT__sys_cyc)
205
                                &&(m_core->v__DOT__sys_we)
206
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
207
                                (m_core->v__DOT__trap_int)?"I":" ");
208
                */
209 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
210
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
211 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
212 34 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
213 2 dgisselq
 
214
                ln++;
215 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
216
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
217
                showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
218
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
219 2 dgisselq
 
220
                ln++;
221 34 dgisselq
                showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
222
                showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
223
                showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
224
                showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
225 2 dgisselq
 
226
                ln++;
227
                mvprintw(ln, 40, "%s %s",
228
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
229
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
230
                mvprintw(ln, 40, "%s %s %s 0x%02x",
231
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
232
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
233
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
234
                        (m_core->v__DOT__cmd_addr)&0x3f);
235
                if (m_core->v__DOT__thecpu__DOT__gie)
236
                        attroff(A_BOLD);
237
                else
238
                        attron(A_BOLD);
239
                mvprintw(ln, 0, "Supervisor Registers");
240
                ln++;
241
 
242 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
243
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
244
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
245
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
246 2 dgisselq
 
247 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
248
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
249
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
250
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
251 2 dgisselq
 
252 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
253
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
254
                showreg(ln,40, "sR10", 10, (m_cursor==22));
255
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
256 2 dgisselq
 
257 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
258
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
259 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
260
                        (m_cursor==26)?">":" ",
261
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
262
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
263
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
264
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
265
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
266 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
267
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
268
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
269
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
270 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
271 2 dgisselq
                ln++;
272
 
273
                if (m_core->v__DOT__thecpu__DOT__gie)
274
                        attron(A_BOLD);
275
                else
276
                        attroff(A_BOLD);
277
                mvprintw(ln, 0, "User Registers"); ln++;
278 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
279
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
280
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
281
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
282 2 dgisselq
 
283 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
284
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
285
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
286
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
287 2 dgisselq
 
288 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
289
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
290
                showreg(ln,40, "uR10", 26, (m_cursor==38));
291
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
292 2 dgisselq
 
293 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
294
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
295
                mvprintw(ln,40, "uCC :%s%s%s%s%s%s%s%s",
296 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
297
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
298
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
299
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
300 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
301
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
302
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
303
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
304 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
305 2 dgisselq
 
306
                attroff(A_BOLD);
307
                ln+=1;
308
 
309 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
310
        ln+=2;
311
#else
312 36 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
313 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
314
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
315
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
316
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
317 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
318 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
319
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
320
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
321
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
322 2 dgisselq
                ln++;
323
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
324
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
325
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
326
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
327
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
328
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
329
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
330 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
331 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
332 39 dgisselq
#endif
333 2 dgisselq
 
334
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
335 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
336
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
337
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
338
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
339 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
340
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
341
                        (m_core->v__DOT__thecpu__DOT__mem_data),
342
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
343 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
344 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
345
// #define      OPT_PIPELINED_BUS_ACCESS
346
#ifdef  OPT_PIPELINED_BUS_ACCESS
347
                printw(" %x%x%c%c",
348
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
349
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
350
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
351
                        (mem_pipe_stalled())?'S':'-'); ln++;
352
#else
353
                ln++;
354
#endif
355 2 dgisselq
 
356 36 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
357
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
358 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
359
                        (m_core->o_wb_stb)?"STB":"   ",
360
                        (m_core->o_wb_we )?"WE":"  ",
361
                        (m_core->o_wb_addr),
362
                        (m_core->o_wb_data),
363
                        (m_core->i_wb_ack)?"ACK":"   ",
364
                        (m_core->i_wb_stall)?"STL":"   ",
365
                        (m_core->i_wb_data)); ln+=2;
366 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
367
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
368
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
369
                        (m_core->v__DOT__thecpu__DOT__master_ce),
370
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
371
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline),
372
                        (m_core->v__DOT__thecpu__DOT__set_cond),
373
                        (!m_core->v__DOT__thecpu__DOT__mem_stalled),
374 2 dgisselq
 
375 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stalled),
376
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
377
                        (m_core->v__DOT__thecpu__DOT__master_ce),
378
                        (mem_pipe_stalled()),
379
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
380
                        (m_core->v__DOT__thecpu__DOT__mem_busy));
381
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
382
                        (m_core->v__DOT__thecpu__DOT__dcdvalid),
383
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
384
                        (m_core->v__DOT__thecpu__DOT__dcdM),
385
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
386
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
387
                        (m_core->v__DOT__thecpu__DOT__dcdB
388
                                == m_core->v__DOT__thecpu__DOT__op_B),
389
                        (m_core->v__DOT__thecpu__DOT__r_dcdI
390
                                == m_core->v__DOT__thecpu__DOT__r_opI),
391
                        (m_core->v__DOT__thecpu__DOT__r_dcdI+1
392
                                == m_core->v__DOT__thecpu__DOT__r_opI));
393
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
394
                        (m_core->v__DOT__thecpu__DOT__r_dcdI),
395
                        (m_core->v__DOT__thecpu__DOT__r_opI));
396
#endif
397
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
398
 
399
 
400 2 dgisselq
                showins(ln, "I ",
401
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
402
                        m_core->v__DOT__thecpu__DOT__pf_valid,
403
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
404
                        m_core->v__DOT__thecpu__DOT__gie,
405
                        0,
406 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
407
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
408 2 dgisselq
 
409
                showins(ln, "Dc",
410
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
411
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
412
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
413
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
414
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
415 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
416
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
417
                        mvprintw(ln-1,10,"I");
418
                else
419
#endif
420
                if (m_core->v__DOT__thecpu__DOT__dcdM)
421
                        mvprintw(ln-1,10,"M");
422 2 dgisselq
 
423
                showins(ln, "Op",
424
                        m_core->v__DOT__thecpu__DOT__op_ce,
425
                        m_core->v__DOT__thecpu__DOT__opvalid,
426
                        m_core->v__DOT__thecpu__DOT__op_gie,
427
                        m_core->v__DOT__thecpu__DOT__op_stall,
428 39 dgisselq
                        op_pc()); ln++;
429
#ifdef  OPT_ILLEGAL_INSTRUCTION
430
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
431
                        mvprintw(ln-1,10,"I");
432
                else
433
#endif
434
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
435
                        mvprintw(ln-1,10,"M");
436
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
437
                        mvprintw(ln-1,10,"A");
438 2 dgisselq
 
439
                showins(ln, "Al",
440
                        m_core->v__DOT__thecpu__DOT__alu_ce,
441
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
442
                        m_core->v__DOT__thecpu__DOT__alu_gie,
443
                        m_core->v__DOT__thecpu__DOT__alu_stall,
444 39 dgisselq
                        alu_pc()); ln++;
445
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
446
                        mvprintw(ln-1,10,"W");
447 2 dgisselq
 
448 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
449 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
450
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
451 2 dgisselq
                mvprintw(ln-4, 48,
452
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
453
                printw("(%s:%02x,%x)",
454
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
455
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
456
                        (m_core->v__DOT__thecpu__DOT__op_gie)
457
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
458
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
459
 
460
                printw("(%s%s%s:%02x)",
461
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
462
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
463
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
464
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
465
                /*
466
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
467
                        m_core->v__DOT__thecpu__DOT__dcdI);
468
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
469
                        m_core->v__DOT__thecpu__DOT__opB);
470
                */
471 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
472 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
473 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
474
                        m_core->v__DOT__thecpu__DOT__r_opB);
475
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
476
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
477
                else
478
                        printw("%8s","");
479 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
480 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
481 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
482
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
483
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
484 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
485 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
486
        }
487
 
488
        unsigned int    cmd_read(unsigned int a) {
489
                if (dbg_fp) {
490
                        dbg_flag= true;
491
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
492
                }
493
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
494
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
495
                        ;
496
                unsigned int v = wb_read(CMD_DATA);
497
 
498
                if (dbg_flag)
499
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
500
                                v);
501
                dbg_flag = false;
502
                return v;
503
        }
504
 
505 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
506
                if ((a&0x0f)==0x0f)
507
                        dbg_flag = true;
508
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
509
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
510
                        ;
511
                if (dbg_flag)
512
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
513
                wb_write(CMD_DATA, v);
514
        }
515
 
516 27 dgisselq
        bool    halted(void) {
517
                return (m_core->v__DOT__cmd_halt != 0);
518
        }
519
 
520 2 dgisselq
        void    read_state(void) {
521
                int     ln= 0;
522 34 dgisselq
                bool    gie;
523 2 dgisselq
 
524 34 dgisselq
                if (m_cursor < 0)
525
                        m_cursor = 0;
526
                else if (m_cursor >= 44)
527
                        m_cursor = 43;
528
 
529
                mvprintw(ln,0, "Peripherals-RS");
530
                mvprintw(ln,40,"%-40s", "CPU State: ");
531
                {
532
                        unsigned int v = wb_read(CMD_REG);
533
                        mvprintw(ln,51, "");
534
                        if (v & 0x010000)
535
                                printw("EXT-INT ");
536
                        if ((v & 0x003000) == 0x03000)
537
                                printw("Halted ");
538
                        else if (v & 0x001000)
539
                                printw("Sleeping ");
540
                        else if (v & 0x002000)
541
                                printw("Supervisor Mod ");
542
                        if (v & 0x008000)
543
                                printw("Break-Enabled ");
544
                        if (v & 0x000080)
545
                                printw("PIC Enabled ");
546
                } ln++;
547
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
548
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
549 36 dgisselq
                // showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
550 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
551 2 dgisselq
                ln++;
552 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
553
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
554
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
555
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
556 2 dgisselq
 
557
                ln++;
558 34 dgisselq
                showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
559
                showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
560
                showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
561
                showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
562 2 dgisselq
 
563
                ln++;
564
                ln++;
565
                unsigned int cc = cmd_read(14);
566
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
567
                        m_core->v__DOT__thecpu__DOT__gie);
568 34 dgisselq
                gie = (cc & 0x020);
569
                if (gie)
570 2 dgisselq
                        attroff(A_BOLD);
571
                else
572
                        attron(A_BOLD);
573
                mvprintw(ln, 0, "Supervisor Registers");
574
                ln++;
575
 
576 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
577
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
578
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
579
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
580 2 dgisselq
 
581 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
582
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
583
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
584
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
585 2 dgisselq
 
586 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
587
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
588
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
589
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
590 2 dgisselq
 
591 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
592
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
593 2 dgisselq
 
594 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
595 34 dgisselq
                        (m_cursor==26)?">":" ",
596 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
597
                        (cc & 0x080)?"BK":"  ",
598 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
599
                        (cc & 0x020)?"IE":"  ",
600
                        (cc & 0x010)?"SL":"  ",
601 2 dgisselq
                        (cc&8)?"V":" ",
602
                        (cc&4)?"N":" ",
603
                        (cc&2)?"C":" ",
604
                        (cc&1)?"Z":" ");
605 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
606 2 dgisselq
                ln++;
607
 
608 34 dgisselq
                if (gie)
609 2 dgisselq
                        attron(A_BOLD);
610
                else
611
                        attroff(A_BOLD);
612
                mvprintw(ln, 0, "User Registers"); ln++;
613 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
614
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
615
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
616
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
617 2 dgisselq
 
618 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
619
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
620
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
621
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
622 2 dgisselq
 
623 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
624
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
625
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
626
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
627 2 dgisselq
 
628 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
629
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
630 2 dgisselq
                cc = cmd_read(30);
631 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
632 36 dgisselq
                        (m_cursor == 42)?'>':' ',
633 34 dgisselq
                        (cc&0x100)?"TP":"  ",
634
                        (cc&0x040)?"ST":"  ",
635
                        (cc&0x020)?"IE":"  ",
636
                        (cc&0x010)?"SL":"  ",
637 2 dgisselq
                        (cc&8)?"V":" ",
638
                        (cc&4)?"N":" ",
639
                        (cc&2)?"C":" ",
640
                        (cc&1)?"Z":" ");
641 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
642 2 dgisselq
 
643
                attroff(A_BOLD);
644
                ln+=2;
645
 
646
                ln+=3;
647
 
648
                showins(ln, "I ",
649
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
650
                        m_core->v__DOT__thecpu__DOT__pf_valid,
651
                        m_core->v__DOT__thecpu__DOT__gie,
652
                        0,
653
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
654
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
655
 
656
                showins(ln, "Dc",
657
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
658
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
659
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
660
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
661
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
662
 
663
                showins(ln, "Op",
664
                        m_core->v__DOT__thecpu__DOT__op_ce,
665
                        m_core->v__DOT__thecpu__DOT__opvalid,
666
                        m_core->v__DOT__thecpu__DOT__op_gie,
667
                        m_core->v__DOT__thecpu__DOT__op_stall,
668 39 dgisselq
                        op_pc()); ln++;
669 2 dgisselq
 
670
                showins(ln, "Al",
671
                        m_core->v__DOT__thecpu__DOT__alu_ce,
672
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
673
                        m_core->v__DOT__thecpu__DOT__alu_gie,
674
                        m_core->v__DOT__thecpu__DOT__alu_stall,
675 39 dgisselq
                        alu_pc()); ln++;
676 2 dgisselq
        }
677
        void    tick(void) {
678
                int gie = m_core->v__DOT__thecpu__DOT__gie;
679
                /*
680
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
681
                                                m_core->o_qspi_sck,
682
                                                m_core->o_qspi_dat);
683
                */
684
 
685 11 dgisselq
                int stb = m_core->o_wb_stb;
686
                if ((m_core->o_wb_addr & (-1<<20))!=1)
687
                        stb = 0;
688
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
689
                        m_core->i_wb_ack = 1;
690 2 dgisselq
 
691
                if ((dbg_flag)&&(dbg_fp)) {
692 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
693 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
694
                                (m_core->i_dbg_stb)?"STB":
695
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
696
                                ((m_core->i_dbg_we)?"WE":"  "),
697
                                (m_core->i_dbg_addr),0,
698
                                m_core->i_dbg_data,
699
                                (m_core->o_dbg_ack)?"ACK":"   ",
700
                                (m_core->o_dbg_stall)?"STALL":"     ",
701
                                (m_core->o_dbg_data),
702
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
703
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
704
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
705
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
706
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
707 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
708
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
709 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
710
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
711
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
712
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
713
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
714
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
715
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
716
                                (m_core->v__DOT__sys_we)?"WE":"  ",
717
                                (m_core->v__DOT__sys_addr),
718
                                (m_core->v__DOT__dbg_addr),
719
                                (m_core->v__DOT__sys_data),
720
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
721
                                (m_core->v__DOT__wb_data));
722
                }
723
 
724
                if (dbg_fp)
725
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
726
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
727
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
728
                                m_core->v__DOT__thecpu__DOT__op_ce,
729 39 dgisselq
                                op_pc(),
730 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcdA,
731
                                m_core->v__DOT__thecpu__DOT__opR,
732
                                m_core->v__DOT__cmd_halt,
733
                                m_core->v__DOT__cpu_halt,
734
                                m_core->v__DOT__thecpu__DOT__alu_ce,
735
                                m_core->v__DOT__thecpu__DOT__alu_valid,
736
                                m_core->v__DOT__thecpu__DOT__alu_wr,
737
                                m_core->v__DOT__thecpu__DOT__alu_reg,
738
                                m_core->v__DOT__thecpu__DOT__ipc,
739
                                m_core->v__DOT__thecpu__DOT__upc);
740
 
741
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
742
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
743
                                m_core->v__DOT__pic_interrupt,
744
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
745
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
746
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
747
                                m_core->v__DOT__cmd_addr,
748
                                m_core->v__DOT__dbg_idata,
749
                                m_core->v__DOT__thecpu__DOT__master_ce,
750
                                m_core->v__DOT__thecpu__DOT__alu_wr,
751
                                m_core->v__DOT__thecpu__DOT__alu_valid,
752
                                m_core->v__DOT__thecpu__DOT__mem_valid);
753
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
754
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
755
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
756
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
757
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
758
                                m_core->v__DOT__cmd_addr,
759
                                m_core->v__DOT__dbg_idata,
760
                                m_core->v__DOT__thecpu__DOT__master_ce,
761
                                m_core->v__DOT__thecpu__DOT__alu_wr,
762
                                m_core->v__DOT__thecpu__DOT__alu_valid,
763
                                m_core->v__DOT__thecpu__DOT__mem_valid,
764
                                m_core->v__DOT__thecpu__DOT__w_iflags,
765
                                m_core->v__DOT__thecpu__DOT__w_uflags);
766 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
767
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
768 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
769
                                m_core->v__DOT__thecpu__DOT__op_break);
770 36 dgisselq
                } else if ((dbg_fp)&&
771
                                ((m_core->v__DOT__thecpu__DOT__op_break)
772
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
773
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
774
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
775
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
776
                                m_core->v__DOT__thecpu__DOT__break_en,
777
                                m_core->v__DOT__thecpu__DOT__dcd_break,
778
                                m_core->v__DOT__thecpu__DOT__op_break);
779 2 dgisselq
                }
780
 
781 34 dgisselq
                if (dbg_fp) {
782
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
783
                                fprintf(dbg_fp, "\tClear Pipeline\n");
784
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
785
                                fprintf(dbg_fp, "\tNew PC\n");
786
                }
787
 
788 36 dgisselq
                if (dbg_fp)
789
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
790
                if (false) {
791
                        m_core->i_clk = 1;
792
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
793
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
794
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
795
                        eval();
796
                        m_core->i_clk = 0;
797
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
798
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
799
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
800
                        eval();
801
                        m_tickcount++;
802
                } else {
803
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
804
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
805
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
806
                        TESTB<Vzipsystem>::tick();
807
                }
808 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
809
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
810
                                (gie)?"User":"Supervisor",
811
                                (gie)?"Supervisor":"User",
812
                                m_core->v__DOT__thecpu__DOT__ipc,
813
                                m_core->v__DOT__thecpu__DOT__upc,
814
                                m_core->v__DOT__thecpu__DOT__pf_pc);
815
                } if (dbg_fp) {
816
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
817
                                m_core->v__DOT__thecpu__DOT__opvalid,
818
                                m_core->v__DOT__thecpu__DOT__op_gie,
819
                                m_core->v__DOT__thecpu__DOT__op_stall,
820 39 dgisselq
                                op_pc());
821 2 dgisselq
                        dbgins("Al - ",
822
                                m_core->v__DOT__thecpu__DOT__alu_ce,
823
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
824
                                m_core->v__DOT__thecpu__DOT__alu_gie,
825
                                m_core->v__DOT__thecpu__DOT__alu_stall,
826 39 dgisselq
                                alu_pc());
827 2 dgisselq
 
828
                }
829
        }
830
 
831
        bool    test_success(void) {
832
                return ((!m_core->v__DOT__thecpu__DOT__gie)
833
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
834
        }
835
 
836 39 dgisselq
        unsigned        op_pc(void) {
837
                /*
838
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
839
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
840
                        r--;
841
                return r;
842
                */
843
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
844
        }
845
 
846
        unsigned        alu_pc(void) {
847
                /*
848
                unsigned        r = op_pc();
849
                if (m_core->v__DOT__thecpu__DOT__opvalid)
850
                        r--;
851
                return r;
852
                */
853
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
854
        }
855
 
856
#ifdef  OPT_PIPELINED_BUS_ACCESS
857
        int     mem_pipe_stalled(void) {
858
                int     r = 0;
859
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
860
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
861
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
862
                        ||(
863
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
864
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
865
                return r;
866
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
867
        }
868
#endif
869
 
870 2 dgisselq
        bool    test_failure(void) {
871
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
872 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
873 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
874 2 dgisselq
        }
875
 
876
        void    wb_write(unsigned a, unsigned int v) {
877 36 dgisselq
                int     errcount = 0;
878 2 dgisselq
                mvprintw(0,35, "%40s", "");
879
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
880
                m_core->i_dbg_cyc = 1;
881
                m_core->i_dbg_stb = 1;
882
                m_core->i_dbg_we  = 1;
883
                m_core->i_dbg_addr = a & 1;
884
                m_core->i_dbg_data = v;
885
 
886
                tick();
887 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
888 2 dgisselq
                        tick();
889
 
890
                m_core->i_dbg_stb = 0;
891 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
892 2 dgisselq
                        tick();
893
 
894
                // Release the bus
895
                m_core->i_dbg_cyc = 0;
896
                m_core->i_dbg_stb = 0;
897
                tick();
898
                mvprintw(0,35, "%40s", "");
899
                mvprintw(0,40, "wb_write -- complete");
900 36 dgisselq
 
901
 
902
                if (errcount >= 100)
903
                        bomb = true;
904 2 dgisselq
        }
905
 
906
        unsigned long   wb_read(unsigned a) {
907
                unsigned int    v;
908 36 dgisselq
                int     errcount = 0;
909 2 dgisselq
                mvprintw(0,35, "%40s", "");
910
                mvprintw(0,40, "wb_read(0x%08x)", a);
911
                m_core->i_dbg_cyc = 1;
912
                m_core->i_dbg_stb = 1;
913
                m_core->i_dbg_we  = 0;
914
                m_core->i_dbg_addr = a & 1;
915
 
916
                tick();
917 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
918 2 dgisselq
                        tick();
919
 
920
                m_core->i_dbg_stb = 0;
921 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
922 2 dgisselq
                        tick();
923
                v = m_core->o_dbg_data;
924
 
925
                // Release the bus
926
                m_core->i_dbg_cyc = 0;
927
                m_core->i_dbg_stb = 0;
928
                tick();
929
 
930
                mvprintw(0,35, "%40s", "");
931
                mvprintw(0,40, "wb_read = 0x%08x", v);
932
 
933 36 dgisselq
                if (errcount >= 100)
934
                        bomb = true;
935 2 dgisselq
                return v;
936
        }
937
 
938 34 dgisselq
        void    cursor_up(void) {
939
                if (m_cursor > 3)
940
                        m_cursor -= 4;
941
        } void  cursor_down(void) {
942
                if (m_cursor < 40)
943
                        m_cursor += 4;
944
        } void  cursor_left(void) {
945
                if (m_cursor > 0)
946
                        m_cursor--;
947
                else    m_cursor = 43;
948
        } void  cursor_right(void) {
949
                if (m_cursor < 43)
950
                        m_cursor++;
951
                else    m_cursor = 0;
952
        }
953
 
954
        int     cursor(void) { return m_cursor; }
955 2 dgisselq
};
956
 
957 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
958
        int     wy, wx, ra;
959
        int     c = tb->cursor();
960
 
961
        wx = (c & 0x03) * 20 + 9;
962
        wy = (c>>2);
963
        if (wy >= 3+4)
964
                wy++;
965
        if (wy > 3)
966
                wy += 2;
967
        wy++;
968
 
969
        if (c >= 12)
970
                ra = c - 12;
971
        else
972
                ra = c + 32;
973
 
974
        bool    done = false;
975
        char    str[16];
976
        int     pos = 0; str[pos] = '\0';
977
        while(!done) {
978
                int     chv = getch();
979
                switch(chv) {
980
                case KEY_ESCAPE:
981
                        pos = 0; str[pos] = '\0'; done = true;
982
                        break;
983
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
984
                        done = true;
985
                        break;
986
                case KEY_LEFT: case KEY_BACKSPACE:
987
                        if (pos > 0) pos--;
988
                        break;
989 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
990 34 dgisselq
                case KEY_CLEAR:
991
                        pos = 0;
992
                        break;
993
                case '0': case ' ': str[pos++] = '0'; break;
994
                case '1': str[pos++] = '1'; break;
995
                case '2': str[pos++] = '2'; break;
996
                case '3': str[pos++] = '3'; break;
997
                case '4': str[pos++] = '4'; break;
998
                case '5': str[pos++] = '5'; break;
999
                case '6': str[pos++] = '6'; break;
1000
                case '7': str[pos++] = '7'; break;
1001
                case '8': str[pos++] = '8'; break;
1002
                case '9': str[pos++] = '9'; break;
1003
                case 'A': case 'a': str[pos++] = 'A'; break;
1004
                case 'B': case 'b': str[pos++] = 'B'; break;
1005
                case 'C': case 'c': str[pos++] = 'C'; break;
1006
                case 'D': case 'd': str[pos++] = 'D'; break;
1007
                case 'E': case 'e': str[pos++] = 'E'; break;
1008
                case 'F': case 'f': str[pos++] = 'F'; break;
1009
                }
1010
 
1011
                if (pos > 8)
1012
                        pos = 8;
1013
                str[pos] = '\0';
1014
 
1015
                attron(A_NORMAL | A_UNDERLINE);
1016
                mvprintw(wy, wx, "%-8s", str);
1017
                if (pos > 0) {
1018
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1019
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1020
                }
1021
                attrset(A_NORMAL);
1022
        }
1023
 
1024
        if (pos > 0) {
1025
                int     v;
1026
                v = strtoul(str, NULL, 16);
1027
                if (!tb->halted()) {
1028
                        switch(ra) {
1029
                        case 15:
1030
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1031
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1032
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1033
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1034
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1035
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1036
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1037
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1038
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1039
                                }
1040
                                break;
1041
                        case 31:
1042
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1043
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1044
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1045
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1046
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1047
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1048
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1049
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1050
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1051
                                }
1052
                                break;
1053
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1054
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1055 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1056 34 dgisselq
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
1057
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1058
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1059
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1060
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1061
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1062
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1063
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1064
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1065
                        default:
1066
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1067
                                break;
1068
                        }
1069
                } else
1070
                        tb->cmd_write(ra, v);
1071
        }
1072
}
1073
 
1074 27 dgisselq
void    usage(void) {
1075
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1076
        printf("\n");
1077
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1078
        printf("\t-a\tSets the testbench to run automatically without any\n");
1079
        printf("\t\tuser interaction.\n");
1080
        printf("\n");
1081
        printf("\tUser Commands:\n");
1082
        printf("\t\tWhen the test bench is run interactively, the following\n");
1083
        printf("\t\tkey strokes are recognized:\n");
1084
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1085
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1086
        printf("\t\t\tuser intervention.\n");
1087
        printf("\t\t\'q\'\tQuit the simulation.\n");
1088
        printf("\t\t\'r\'\tReset the processor.\n");
1089
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1090
        printf("\t\t\tThis may consume more than one tick.\n");
1091
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1092
}
1093 2 dgisselq
 
1094
int     main(int argc, char **argv) {
1095
        Verilated::commandArgs(argc, argv);
1096
        ZIPPY_TB        *tb = new ZIPPY_TB();
1097 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1098 2 dgisselq
 
1099
        // mem[0x00000] = 0xbe000010; // Halt instruction
1100
        unsigned int mptr = 0;
1101
 
1102 9 dgisselq
        if (argc <= 1) {
1103 27 dgisselq
                usage();
1104
                exit(-1);
1105 9 dgisselq
        } else {
1106
                for(int argn=1; argn<argc; argn++) {
1107 27 dgisselq
                        if (argv[argn][0] == '-') {
1108
                                switch(argv[argn][1]) {
1109
                                case 'a':
1110
                                        autorun = true;
1111
                                        break;
1112
                                case 'e':
1113
                                        exit_on_done = true;
1114
                                        break;
1115
                                case 'h':
1116
                                        usage();
1117
                                        exit(0);
1118
                                        break;
1119 36 dgisselq
                                case 's':
1120
                                        autostep = true;
1121
                                        break;
1122 27 dgisselq
                                default:
1123
                                        usage();
1124
                                        exit(-1);
1125
                                        break;
1126
                                }
1127
                        } else if (access(argv[argn], R_OK)==0) {
1128 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1129
                                if (fp == NULL) {
1130
                                        printf("Cannot open %s\n", argv[argn]);
1131
                                        perror("O/S Err: ");
1132
                                        exit(-1);
1133
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1134
                                fclose(fp);
1135
                        }
1136
                }
1137
        }
1138
 
1139 27 dgisselq
        if (autorun) {
1140
                bool    done = false;
1141 2 dgisselq
 
1142 27 dgisselq
                printf("Running in non-interactive mode\n");
1143
                tb->reset();
1144
                for(int i=0; i<2; i++)
1145
                        tb->tick();
1146
                tb->m_core->v__DOT__cmd_halt = 0;
1147
                while(!done) {
1148
                        tb->tick();
1149
 
1150
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1151
                                // tb->m_core->v__DOT__cmd_halt = 0;
1152
                                // tb->m_core->v__DOT__cmd_step = 0;
1153
 
1154 34 dgisselq
                        /*
1155 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1156
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1157
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1158
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1159 34 dgisselq
                        */
1160 27 dgisselq
 
1161
                        done = (tb->test_success())||(tb->test_failure());
1162
                }
1163 36 dgisselq
        } else if (autostep) {
1164
                bool    done = false;
1165
 
1166
                printf("Running in non-interactive mode, via step commands\n");
1167
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1168
                while(!done) {
1169
                        tb->wb_write(CMD_REG, CMD_STEP);
1170
                        done = (tb->test_success())||(tb->test_failure());
1171
                }
1172 27 dgisselq
        } else { // Interactive
1173
                initscr();
1174
                raw();
1175
                noecho();
1176
                keypad(stdscr, true);
1177
 
1178
                tb->reset();
1179
                for(int i=0; i<2; i++)
1180
                        tb->tick();
1181
                tb->m_core->v__DOT__cmd_halt = 0;
1182
 
1183
                int     chv = 'q';
1184
 
1185 2 dgisselq
                bool    done = false, halted = true, manual = true;
1186
 
1187
                halfdelay(1);
1188 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1189 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1190
                        // tb->show_state();
1191
 
1192
                while(!done) {
1193
                        chv = getch();
1194
                        switch(chv) {
1195
                        case 'h': case 'H':
1196
                                tb->wb_write(CMD_REG, CMD_HALT);
1197
                                if (!halted)
1198
                                        erase();
1199
                                halted = true;
1200
                                break;
1201
                        case 'g': case 'G':
1202
                                tb->wb_write(CMD_REG, 0);
1203
                                if (halted)
1204
                                        erase();
1205
                                halted = false;
1206
                                manual = false;
1207
                                break;
1208
                        case 'q': case 'Q':
1209
                                done = true;
1210
                                break;
1211
                        case 'r': case 'R':
1212 36 dgisselq
                                if (manual)
1213
                                        tb->reset();
1214
                                else
1215
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1216 2 dgisselq
                                halted = true;
1217
                                erase();
1218
                                break;
1219 39 dgisselq
                        case 's':
1220 34 dgisselq
                                if (!halted)
1221 27 dgisselq
                                        erase();
1222 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1223
                                manual = false;
1224 34 dgisselq
                                halted = true;
1225 2 dgisselq
                                break;
1226 39 dgisselq
                        case 'S':
1227 34 dgisselq
                                if ((!manual)||(halted))
1228 27 dgisselq
                                        erase();
1229 2 dgisselq
                                manual = true;
1230 39 dgisselq
                                halted = true;
1231
                                tb->m_core->v__DOT__cmd_halt = 0;
1232
                                tb->m_core->v__DOT__cmd_step = 1;
1233
                                tb->eval();
1234
                                tb->tick();
1235
                                break;
1236
                        case 'T': // 
1237
                                if ((!manual)||(halted))
1238
                                        erase();
1239
                                manual = true;
1240
                                halted = true;
1241
                                tb->m_core->v__DOT__cmd_halt = 1;
1242
                                tb->m_core->v__DOT__cmd_step = 0;
1243
                                tb->eval();
1244
                                tb->tick();
1245
                                break;
1246
                        case 't':
1247
                                if ((!manual)||(halted))
1248
                                        erase();
1249
                                manual = true;
1250 34 dgisselq
                                halted = false;
1251 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1252
                //              tb->m_core->v__DOT__cmd_halt = 0;
1253
                //              tb->m_core->v__DOT__cmd_step = 0;
1254 2 dgisselq
                                tb->tick();
1255
                                break;
1256 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1257
                                get_value(tb);
1258
                                break;
1259
                        case    KEY_UP:         tb->cursor_up();        break;
1260
                        case    KEY_DOWN:       tb->cursor_down();      break;
1261
                        case    KEY_LEFT:       tb->cursor_left();      break;
1262
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1263 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1264 34 dgisselq
                        case ERR: case KEY_CLEAR:
1265 2 dgisselq
                        default:
1266
                                if (!manual)
1267
                                        tb->tick();
1268
                        }
1269
 
1270
                        if (manual) {
1271
                                tb->show_state();
1272
                        } else if (halted) {
1273
                                if (tb->dbg_fp)
1274
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1275
                                tb->read_state();
1276
                        } else
1277
                                tb->show_state();
1278
 
1279
                        if (tb->m_core->i_rst)
1280
                                done =true;
1281
                        if (tb->bomb)
1282
                                done = true;
1283 27 dgisselq
 
1284
                        if (exit_on_done) {
1285
                                if (tb->test_success())
1286
                                        done = true;
1287
                                if (tb->test_failure())
1288
                                        done = true;
1289
                        }
1290 2 dgisselq
                }
1291 27 dgisselq
                endwin();
1292
        }
1293
#ifdef  MANUAL_STEPPING_MODE
1294
         else { // Manual stepping mode
1295 2 dgisselq
                tb->show_state();
1296
 
1297
                while('q' != tolower(chv = getch())) {
1298
                        tb->tick();
1299
                        tb->show_state();
1300
 
1301
                        if (tb->test_success())
1302
                                break;
1303
                        else if (tb->test_failure())
1304
                                break;
1305
                }
1306
        }
1307 27 dgisselq
#endif
1308 2 dgisselq
 
1309 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1310
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1311
        if (tb->m_core->v__DOT__mtc_data != 0)
1312
                printf("Instructions / Clock: %.2f\n",
1313
                        (double)tb->m_core->v__DOT__mic_data
1314
                        / (double)tb->m_core->v__DOT__mtc_data);
1315 36 dgisselq
 
1316
        int     rcode = 0;
1317
        if (tb->bomb) {
1318
                printf("TEST BOMBED\n");
1319
                rcode = -1;
1320
        } else if (tb->test_success()) {
1321 2 dgisselq
                printf("SUCCESS!\n");
1322 36 dgisselq
        } else if (tb->test_failure()) {
1323
                rcode = -2;
1324 2 dgisselq
                printf("TEST FAILED!\n");
1325 36 dgisselq
        } else
1326 27 dgisselq
                printf("User quit\n");
1327 36 dgisselq
        exit(rcode);
1328 2 dgisselq
}
1329
 

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