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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 57

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 2 dgisselq
// No particular "parameters" need definition or redefinition here.
71
class   ZIPPY_TB : public TESTB<Vzipsystem> {
72
public:
73 9 dgisselq
        unsigned long   m_mem_size;
74 2 dgisselq
        MEMSIM          m_mem;
75
        // QSPIFLASHSIM m_flash;
76
        FILE            *dbg_fp;
77 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
78 34 dgisselq
        int             m_cursor;
79 2 dgisselq
 
80 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
81 43 dgisselq
                if (false) {
82 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
83
                        dbg_flag = true;
84
                } else {
85
                        dbg_fp = NULL;
86
                        dbg_flag = false;
87
                }
88 2 dgisselq
                bomb = false;
89 34 dgisselq
                m_cursor = 0;
90 43 dgisselq
                m_show_user_timers = false;
91 2 dgisselq
        }
92
 
93
        void    reset(void) {
94
                // m_flash.debug(false);
95
                TESTB<Vzipsystem>::reset();
96
        }
97
 
98
        bool    on_tick(void) {
99
                tick();
100
                return true;
101
        }
102
 
103 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
104
                if (c)
105
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
106
                else
107
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
108 2 dgisselq
        }
109
 
110 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
111 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
112 34 dgisselq
                if (c)
113
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
114
                else
115
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
116 2 dgisselq
        }
117
 
118 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
119 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
120 34 dgisselq
                if (c)
121
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
122
                else
123
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
124 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
125
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
126
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
127 34 dgisselq
                        ?'a':((c)?'<':' '));
128 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
129
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
130
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
131 34 dgisselq
                        ?'b':((c)?'<':' '));
132 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
133
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
134 34 dgisselq
                        ?'W':((c)?'<':' '));
135 2 dgisselq
        }
136
 
137
        void    showins(int y, const char *lbl, const int ce, const int valid,
138
                        const int gie, const int stall, const unsigned int pc) {
139
                char    line[80];
140
 
141
                if (ce)
142
                        mvprintw(y, 0, "Ck ");
143
                else
144
                        mvprintw(y, 0, "   ");
145
                if (stall)
146
                        printw("Stl ");
147
                else
148
                        printw("    ");
149
                printw("%s: 0x%08x", lbl, pc);
150
 
151
                if (valid) {
152
                        if (gie) attroff(A_BOLD);
153
                        else    attron(A_BOLD);
154
                        zipi_to_string(m_mem[pc], line);
155 27 dgisselq
                        printw("  %-24s", &line[1]);
156 2 dgisselq
                } else {
157
                        attroff(A_BOLD);
158
                        printw("  (0x%08x)%28s", m_mem[pc],"");
159
                }
160
                attroff(A_BOLD);
161
        }
162
 
163
        void    dbgins(const char *lbl, const int ce, const int valid,
164
                        const int gie, const int stall, const unsigned int pc) {
165
                char    line[80];
166
 
167
                if (!dbg_fp)
168
                        return;
169
 
170
                if (ce)
171
                        fprintf(dbg_fp, "%s Ck ", lbl);
172
                else
173
                        fprintf(dbg_fp, "%s    ", lbl);
174
                if (stall)
175
                        fprintf(dbg_fp, "Stl ");
176
                else
177
                        fprintf(dbg_fp, "    ");
178
                fprintf(dbg_fp, "0x%08x:  ", pc);
179
 
180
                if (valid) {
181
                        zipi_to_string(m_mem[pc], line);
182
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
183
                } else {
184
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
185
                }
186
        }
187
 
188
        void    show_state(void) {
189
                int     ln= 0;
190
 
191
                mvprintw(ln,0, "Peripherals-SS"); ln++;
192 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
193 36 dgisselq
                printw(" %s",
194
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
195
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
196
                        );
197 39 dgisselq
#endif
198
 
199
#ifdef  OPT_EARLY_BRANCHING
200
                printw(" %s%s",
201 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
202 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
203
#endif
204 36 dgisselq
 
205
                /*
206 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
207
                        mvprintw(ln, 17, "%s%s",
208
                                ((m_core->v__DOT__sys_cyc)
209
                                &&(m_core->v__DOT__sys_we)
210
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
211
                                (m_core->v__DOT__trap_int)?"I":" ");
212
                */
213 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
214
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
215 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
216 57 dgisselq
 
217
                if (!m_show_user_timers) {
218
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
219
                } else {
220
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
221
                }
222
 
223 34 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
224 2 dgisselq
 
225
                ln++;
226 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
227
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
228
                showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
229
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
230 2 dgisselq
 
231 43 dgisselq
 
232
                if (!m_show_user_timers) {
233
                        ln++;
234
                        showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
235
                        showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
236
                        showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
237
                        showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
238
                } else {
239
                        ln++;
240
                        showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
241
                        showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
242
                        showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
243
                        showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
244
                }
245 2 dgisselq
 
246
                ln++;
247
                mvprintw(ln, 40, "%s %s",
248
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
249
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
250 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
251 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
252
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
253
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
254 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
255
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
256
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
257 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
258
                        attroff(A_BOLD);
259
                else
260
                        attron(A_BOLD);
261
                mvprintw(ln, 0, "Supervisor Registers");
262
                ln++;
263
 
264 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
265
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
266
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
267
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
268 2 dgisselq
 
269 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
270
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
271
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
272
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
273 2 dgisselq
 
274 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
275
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
276
                showreg(ln,40, "sR10", 10, (m_cursor==22));
277
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
278 2 dgisselq
 
279 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
280
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
281 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
282
                        (m_cursor==26)?">":" ",
283
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
284
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
285
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
286
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
287
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
288 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
289
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
290
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
291
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
292 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
293 2 dgisselq
                ln++;
294
 
295
                if (m_core->v__DOT__thecpu__DOT__gie)
296
                        attron(A_BOLD);
297
                else
298
                        attroff(A_BOLD);
299
                mvprintw(ln, 0, "User Registers"); ln++;
300 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
301
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
302
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
303
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
304 2 dgisselq
 
305 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
306
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
307
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
308
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
309 2 dgisselq
 
310 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
311
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
312
                showreg(ln,40, "uR10", 26, (m_cursor==38));
313
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
314 2 dgisselq
 
315 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
316
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
317 43 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
318
                        (m_cursor == 42)?'>':' ',
319 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
320
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
321
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
322
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
323 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
324
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
325
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
326
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
327 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
328 2 dgisselq
 
329
                attroff(A_BOLD);
330
                ln+=1;
331
 
332 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
333
        ln+=2;
334
#else
335 36 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
336 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
337
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
338
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
339
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
340 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
341 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
342
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
343
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
344
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
345 2 dgisselq
                ln++;
346
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
347
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
348
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
349
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
350
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
351
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
352
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
353 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
354 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
355 39 dgisselq
#endif
356 2 dgisselq
 
357
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
358 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
359
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
360
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
361
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
362 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
363
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
364
                        (m_core->v__DOT__thecpu__DOT__mem_data),
365
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
366 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
367 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
368
// #define      OPT_PIPELINED_BUS_ACCESS
369
#ifdef  OPT_PIPELINED_BUS_ACCESS
370
                printw(" %x%x%c%c",
371
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
372
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
373
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
374
                        (mem_pipe_stalled())?'S':'-'); ln++;
375
#else
376
                ln++;
377
#endif
378 2 dgisselq
 
379 36 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
380
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
381 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
382
                        (m_core->o_wb_stb)?"STB":"   ",
383
                        (m_core->o_wb_we )?"WE":"  ",
384
                        (m_core->o_wb_addr),
385
                        (m_core->o_wb_data),
386
                        (m_core->i_wb_ack)?"ACK":"   ",
387
                        (m_core->i_wb_stall)?"STL":"   ",
388
                        (m_core->i_wb_data)); ln+=2;
389 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
390
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
391
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
392 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
393
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
394
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
395
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
396
                        (!m_core->v__DOT__thecpu__DOT__mem_stalled),    //1
397 2 dgisselq
 
398 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stalled),
399
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
400
                        (m_core->v__DOT__thecpu__DOT__master_ce),
401
                        (mem_pipe_stalled()),
402
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
403 57 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
404
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
405
#else
406
                        (m_core->v__DOT__thecpu__DOT__mem_busy)
407
#endif
408
                        );
409 39 dgisselq
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
410
                        (m_core->v__DOT__thecpu__DOT__dcdvalid),
411
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
412
                        (m_core->v__DOT__thecpu__DOT__dcdM),
413
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
414
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
415
                        (m_core->v__DOT__thecpu__DOT__dcdB
416
                                == m_core->v__DOT__thecpu__DOT__op_B),
417
                        (m_core->v__DOT__thecpu__DOT__r_dcdI
418
                                == m_core->v__DOT__thecpu__DOT__r_opI),
419
                        (m_core->v__DOT__thecpu__DOT__r_dcdI+1
420
                                == m_core->v__DOT__thecpu__DOT__r_opI));
421
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
422
                        (m_core->v__DOT__thecpu__DOT__r_dcdI),
423
                        (m_core->v__DOT__thecpu__DOT__r_opI));
424
#endif
425
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
426 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
427
                printw(" A:%c%c B:%c%c",
428 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
429
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
430 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
431
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
432
#endif
433 39 dgisselq
 
434
 
435 2 dgisselq
                showins(ln, "I ",
436
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
437
                        m_core->v__DOT__thecpu__DOT__pf_valid,
438
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
439
                        m_core->v__DOT__thecpu__DOT__gie,
440
                        0,
441 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
442
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
443 2 dgisselq
 
444
                showins(ln, "Dc",
445
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
446
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
447
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
448
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
449
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
450 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
451
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
452
                        mvprintw(ln-1,10,"I");
453
                else
454
#endif
455
                if (m_core->v__DOT__thecpu__DOT__dcdM)
456
                        mvprintw(ln-1,10,"M");
457 2 dgisselq
 
458
                showins(ln, "Op",
459
                        m_core->v__DOT__thecpu__DOT__op_ce,
460
                        m_core->v__DOT__thecpu__DOT__opvalid,
461
                        m_core->v__DOT__thecpu__DOT__op_gie,
462
                        m_core->v__DOT__thecpu__DOT__op_stall,
463 39 dgisselq
                        op_pc()); ln++;
464
#ifdef  OPT_ILLEGAL_INSTRUCTION
465
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
466
                        mvprintw(ln-1,10,"I");
467
                else
468
#endif
469
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
470
                        mvprintw(ln-1,10,"M");
471
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
472
                        mvprintw(ln-1,10,"A");
473 2 dgisselq
 
474
                showins(ln, "Al",
475
                        m_core->v__DOT__thecpu__DOT__alu_ce,
476
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
477
                        m_core->v__DOT__thecpu__DOT__alu_gie,
478
                        m_core->v__DOT__thecpu__DOT__alu_stall,
479 39 dgisselq
                        alu_pc()); ln++;
480
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
481
                        mvprintw(ln-1,10,"W");
482 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
483
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
484
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
485
                        mvprintw(ln-1,10,"v");
486
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
487
                        mvprintw(ln-1,10,"I");
488
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
489
                        // mvprintw(ln-1,10,"i");
490 2 dgisselq
 
491 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
492 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
493
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
494 2 dgisselq
                mvprintw(ln-4, 48,
495
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
496
                printw("(%s:%02x,%x)",
497
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
498
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
499
                        (m_core->v__DOT__thecpu__DOT__op_gie)
500
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
501
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
502
 
503
                printw("(%s%s%s:%02x)",
504
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
505
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
506
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
507
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
508
                /*
509
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
510
                        m_core->v__DOT__thecpu__DOT__dcdI);
511
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
512
                        m_core->v__DOT__thecpu__DOT__opB);
513
                */
514 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
515 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
516 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
517
                        m_core->v__DOT__thecpu__DOT__r_opB);
518
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
519
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
520
                else
521
                        printw("%8s","");
522 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
523 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
524 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
525
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
526
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
527 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
528 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
529
        }
530
 
531 43 dgisselq
        void    show_user_timers(bool v) {
532
                m_show_user_timers = v;
533
        }
534
 
535 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
536 57 dgisselq
                int     errcount = 0;
537 2 dgisselq
                if (dbg_fp) {
538
                        dbg_flag= true;
539
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
540
                }
541
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
542 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
543
                        errcount++;
544
                if (errcount >= MAXERR) {
545
                        endwin();
546
 
547
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
548
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
549
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
550
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
551
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
552
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
553
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
554
                        printf("dcdvalid       = %d\n", m_core->v__DOT__thecpu__DOT__dcdvalid);
555
                        printf("dcd_ce         = %d\n", m_core->v__DOT__thecpu__DOT__dcd_ce);
556
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
557
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
558
                        printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch);
559
                        printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb);
560
 
561
                        exit(-2);
562
                }
563
 
564
                assert(errcount < MAXERR);
565 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
566
 
567
                if (dbg_flag)
568
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
569
                                v);
570
                dbg_flag = false;
571
                return v;
572
        }
573
 
574 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
575 57 dgisselq
                int     errcount = 0;
576 34 dgisselq
                if ((a&0x0f)==0x0f)
577
                        dbg_flag = true;
578
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
579 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
580
                        errcount++;
581
                assert(errcount < MAXERR);
582 34 dgisselq
                if (dbg_flag)
583
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
584
                wb_write(CMD_DATA, v);
585
        }
586
 
587 27 dgisselq
        bool    halted(void) {
588
                return (m_core->v__DOT__cmd_halt != 0);
589
        }
590
 
591 2 dgisselq
        void    read_state(void) {
592
                int     ln= 0;
593 34 dgisselq
                bool    gie;
594 2 dgisselq
 
595 34 dgisselq
                if (m_cursor < 0)
596
                        m_cursor = 0;
597
                else if (m_cursor >= 44)
598
                        m_cursor = 43;
599
 
600
                mvprintw(ln,0, "Peripherals-RS");
601
                mvprintw(ln,40,"%-40s", "CPU State: ");
602
                {
603
                        unsigned int v = wb_read(CMD_REG);
604
                        mvprintw(ln,51, "");
605
                        if (v & 0x010000)
606
                                printw("EXT-INT ");
607
                        if ((v & 0x003000) == 0x03000)
608
                                printw("Halted ");
609
                        else if (v & 0x001000)
610
                                printw("Sleeping ");
611
                        else if (v & 0x002000)
612
                                printw("Supervisor Mod ");
613
                        if (v & 0x008000)
614
                                printw("Break-Enabled ");
615
                        if (v & 0x000080)
616
                                printw("PIC Enabled ");
617
                } ln++;
618
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
619
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
620 57 dgisselq
                showval(ln,40, "WBUS", cmd_read(32+ 2), false);
621 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
622 2 dgisselq
                ln++;
623 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
624
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
625
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
626
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
627 2 dgisselq
 
628
                ln++;
629 43 dgisselq
                if (!m_show_user_timers) {
630
                        showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
631
                        showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
632
                        showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
633
                        showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
634
                } else {
635
                        showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
636
                        showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
637
                        showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
638
                        showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
639
                }
640 2 dgisselq
 
641
                ln++;
642
                ln++;
643
                unsigned int cc = cmd_read(14);
644
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
645
                        m_core->v__DOT__thecpu__DOT__gie);
646 34 dgisselq
                gie = (cc & 0x020);
647
                if (gie)
648 2 dgisselq
                        attroff(A_BOLD);
649
                else
650
                        attron(A_BOLD);
651
                mvprintw(ln, 0, "Supervisor Registers");
652
                ln++;
653
 
654 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
655
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
656
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
657
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
658 2 dgisselq
 
659 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
660
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
661
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
662
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
663 2 dgisselq
 
664 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
665
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
666
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
667
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
668 2 dgisselq
 
669 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
670
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
671 2 dgisselq
 
672 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
673 34 dgisselq
                        (m_cursor==26)?">":" ",
674 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
675
                        (cc & 0x080)?"BK":"  ",
676 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
677
                        (cc & 0x020)?"IE":"  ",
678
                        (cc & 0x010)?"SL":"  ",
679 2 dgisselq
                        (cc&8)?"V":" ",
680
                        (cc&4)?"N":" ",
681
                        (cc&2)?"C":" ",
682
                        (cc&1)?"Z":" ");
683 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
684 2 dgisselq
                ln++;
685
 
686 34 dgisselq
                if (gie)
687 2 dgisselq
                        attron(A_BOLD);
688
                else
689
                        attroff(A_BOLD);
690
                mvprintw(ln, 0, "User Registers"); ln++;
691 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
692
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
693
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
694
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
695 2 dgisselq
 
696 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
697
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
698
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
699
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
700 2 dgisselq
 
701 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
702
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
703
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
704
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
705 2 dgisselq
 
706 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
707
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
708 2 dgisselq
                cc = cmd_read(30);
709 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
710 36 dgisselq
                        (m_cursor == 42)?'>':' ',
711 34 dgisselq
                        (cc&0x100)?"TP":"  ",
712
                        (cc&0x040)?"ST":"  ",
713
                        (cc&0x020)?"IE":"  ",
714
                        (cc&0x010)?"SL":"  ",
715 2 dgisselq
                        (cc&8)?"V":" ",
716
                        (cc&4)?"N":" ",
717
                        (cc&2)?"C":" ",
718
                        (cc&1)?"Z":" ");
719 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
720 2 dgisselq
 
721
                attroff(A_BOLD);
722
                ln+=2;
723
 
724
                ln+=3;
725
 
726
                showins(ln, "I ",
727
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
728
                        m_core->v__DOT__thecpu__DOT__pf_valid,
729
                        m_core->v__DOT__thecpu__DOT__gie,
730
                        0,
731 57 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
732
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
733 2 dgisselq
 
734
                showins(ln, "Dc",
735
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
736
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
737
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
738
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
739
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
740
 
741
                showins(ln, "Op",
742
                        m_core->v__DOT__thecpu__DOT__op_ce,
743
                        m_core->v__DOT__thecpu__DOT__opvalid,
744
                        m_core->v__DOT__thecpu__DOT__op_gie,
745
                        m_core->v__DOT__thecpu__DOT__op_stall,
746 39 dgisselq
                        op_pc()); ln++;
747 2 dgisselq
 
748
                showins(ln, "Al",
749
                        m_core->v__DOT__thecpu__DOT__alu_ce,
750
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
751
                        m_core->v__DOT__thecpu__DOT__alu_gie,
752
                        m_core->v__DOT__thecpu__DOT__alu_stall,
753 39 dgisselq
                        alu_pc()); ln++;
754 2 dgisselq
        }
755
        void    tick(void) {
756
                int gie = m_core->v__DOT__thecpu__DOT__gie;
757
                /*
758
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
759
                                                m_core->o_qspi_sck,
760
                                                m_core->o_qspi_dat);
761
                */
762
 
763 11 dgisselq
                int stb = m_core->o_wb_stb;
764
                if ((m_core->o_wb_addr & (-1<<20))!=1)
765
                        stb = 0;
766
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
767
                        m_core->i_wb_ack = 1;
768 2 dgisselq
 
769
                if ((dbg_flag)&&(dbg_fp)) {
770 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
771 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
772
                                (m_core->i_dbg_stb)?"STB":
773
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
774
                                ((m_core->i_dbg_we)?"WE":"  "),
775
                                (m_core->i_dbg_addr),0,
776
                                m_core->i_dbg_data,
777
                                (m_core->o_dbg_ack)?"ACK":"   ",
778
                                (m_core->o_dbg_stall)?"STALL":"     ",
779
                                (m_core->o_dbg_data),
780
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
781
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
782
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
783
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
784
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
785 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
786
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
787 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
788
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
789
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
790
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
791
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
792
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
793
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
794
                                (m_core->v__DOT__sys_we)?"WE":"  ",
795
                                (m_core->v__DOT__sys_addr),
796
                                (m_core->v__DOT__dbg_addr),
797
                                (m_core->v__DOT__sys_data),
798
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
799
                                (m_core->v__DOT__wb_data));
800
                }
801
 
802
                if (dbg_fp)
803
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
804
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
805
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
806
                                m_core->v__DOT__thecpu__DOT__op_ce,
807 39 dgisselq
                                op_pc(),
808 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcdA,
809
                                m_core->v__DOT__thecpu__DOT__opR,
810
                                m_core->v__DOT__cmd_halt,
811
                                m_core->v__DOT__cpu_halt,
812
                                m_core->v__DOT__thecpu__DOT__alu_ce,
813
                                m_core->v__DOT__thecpu__DOT__alu_valid,
814
                                m_core->v__DOT__thecpu__DOT__alu_wr,
815
                                m_core->v__DOT__thecpu__DOT__alu_reg,
816
                                m_core->v__DOT__thecpu__DOT__ipc,
817
                                m_core->v__DOT__thecpu__DOT__upc);
818
 
819
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
820
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
821
                                m_core->v__DOT__pic_interrupt,
822
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
823
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
824
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
825
                                m_core->v__DOT__cmd_addr,
826
                                m_core->v__DOT__dbg_idata,
827
                                m_core->v__DOT__thecpu__DOT__master_ce,
828
                                m_core->v__DOT__thecpu__DOT__alu_wr,
829
                                m_core->v__DOT__thecpu__DOT__alu_valid,
830
                                m_core->v__DOT__thecpu__DOT__mem_valid);
831
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
832
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
833
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
834
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
835
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
836
                                m_core->v__DOT__cmd_addr,
837
                                m_core->v__DOT__dbg_idata,
838
                                m_core->v__DOT__thecpu__DOT__master_ce,
839
                                m_core->v__DOT__thecpu__DOT__alu_wr,
840
                                m_core->v__DOT__thecpu__DOT__alu_valid,
841
                                m_core->v__DOT__thecpu__DOT__mem_valid,
842
                                m_core->v__DOT__thecpu__DOT__w_iflags,
843
                                m_core->v__DOT__thecpu__DOT__w_uflags);
844 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
845
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
846 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
847
                                m_core->v__DOT__thecpu__DOT__op_break);
848 36 dgisselq
                } else if ((dbg_fp)&&
849
                                ((m_core->v__DOT__thecpu__DOT__op_break)
850
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
851
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
852
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
853
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
854
                                m_core->v__DOT__thecpu__DOT__break_en,
855
                                m_core->v__DOT__thecpu__DOT__dcd_break,
856
                                m_core->v__DOT__thecpu__DOT__op_break);
857 2 dgisselq
                }
858
 
859 34 dgisselq
                if (dbg_fp) {
860
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
861
                                fprintf(dbg_fp, "\tClear Pipeline\n");
862
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
863
                                fprintf(dbg_fp, "\tNew PC\n");
864
                }
865
 
866 36 dgisselq
                if (dbg_fp)
867
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
868
                if (false) {
869
                        m_core->i_clk = 1;
870
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
871
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
872
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
873
                        eval();
874
                        m_core->i_clk = 0;
875
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
876
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
877
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
878
                        eval();
879
                        m_tickcount++;
880
                } else {
881
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
882
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
883
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
884 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
885
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
886
                                m_core->i_wb_err = 1;
887
                        else
888
                                m_core->i_wb_err = 0;
889 36 dgisselq
                        TESTB<Vzipsystem>::tick();
890
                }
891 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
892
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
893
                                (gie)?"User":"Supervisor",
894
                                (gie)?"Supervisor":"User",
895
                                m_core->v__DOT__thecpu__DOT__ipc,
896
                                m_core->v__DOT__thecpu__DOT__upc,
897
                                m_core->v__DOT__thecpu__DOT__pf_pc);
898
                } if (dbg_fp) {
899 57 dgisselq
                        dbgins("Dc - ", m_core->v__DOT__thecpu__DOT__dcd_ce,
900
                                m_core->v__DOT__thecpu__DOT__dcdvalid,
901
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
902
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
903
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1);
904 2 dgisselq
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
905
                                m_core->v__DOT__thecpu__DOT__opvalid,
906
                                m_core->v__DOT__thecpu__DOT__op_gie,
907
                                m_core->v__DOT__thecpu__DOT__op_stall,
908 39 dgisselq
                                op_pc());
909 57 dgisselq
/*
910
#ifdef  OPT_SINGLE_CYCLE
911
                        fprintf(dbg_fp, "\t\t  A = %08x,   B = %08x, I = %08x, B+I = %08x, %c%c %s%s%s[%2x] = %08x %s\n",
912
                                m_core->v__DOT__thecpu__DOT__r_opA,
913
                                m_core->v__DOT__thecpu__DOT__r_opB,
914
                                m_core->v__DOT__thecpu__DOT__w_opBnI,
915
                                m_core->v__DOT__thecpu__DOT__r_dcdI,
916
                                (m_core->v__DOT__thecpu__DOT__opvalid_alu)?'A':'-',
917
                                (m_core->v__DOT__thecpu__DOT__opvalid_mem)?'M':'-',
918
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"W":" ",
919
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"A":"M",
920
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"k":"-",
921
                                (m_core->v__DOT__thecpu__DOT__wr_reg_id),
922
                                (m_core->v__DOT__thecpu__DOT__wr_reg_vl),
923
                                (m_core->v__DOT__thecpu__DOT__mem_rdbusy)?"Mem-RdBusy":
924
                                ((m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)?"Mem-Busy":""));
925
                        fprintf(dbg_fp, "\t\topA = %08x, opB = %08x, alu_result = %08x\n",
926
                                m_core->v__DOT__thecpu__DOT__opA,
927
                                m_core->v__DOT__thecpu__DOT__opB,
928
                                m_core->v__DOT__thecpu__DOT__alu_result);
929
#endif
930
*/
931 2 dgisselq
                        dbgins("Al - ",
932
                                m_core->v__DOT__thecpu__DOT__alu_ce,
933
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
934
                                m_core->v__DOT__thecpu__DOT__alu_gie,
935
                                m_core->v__DOT__thecpu__DOT__alu_stall,
936 39 dgisselq
                                alu_pc());
937 2 dgisselq
 
938
                }
939
        }
940
 
941
        bool    test_success(void) {
942
                return ((!m_core->v__DOT__thecpu__DOT__gie)
943
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
944
        }
945
 
946 39 dgisselq
        unsigned        op_pc(void) {
947
                /*
948
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
949
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
950
                        r--;
951
                return r;
952
                */
953
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
954
        }
955
 
956
        unsigned        alu_pc(void) {
957
                /*
958
                unsigned        r = op_pc();
959
                if (m_core->v__DOT__thecpu__DOT__opvalid)
960
                        r--;
961
                return r;
962
                */
963
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
964
        }
965
 
966
#ifdef  OPT_PIPELINED_BUS_ACCESS
967
        int     mem_pipe_stalled(void) {
968
                int     r = 0;
969
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
970
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
971
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
972
                        ||(
973
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
974
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
975
                return r;
976
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
977
        }
978
#endif
979
 
980 2 dgisselq
        bool    test_failure(void) {
981 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
982
                        return 0;
983
                else if (m_core->v__DOT__thecpu__DOT__gie)
984
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
985
                else
986
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
987
                /*
988 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
989 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
990 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
991 43 dgisselq
                */
992 2 dgisselq
        }
993
 
994
        void    wb_write(unsigned a, unsigned int v) {
995 36 dgisselq
                int     errcount = 0;
996 2 dgisselq
                mvprintw(0,35, "%40s", "");
997
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
998
                m_core->i_dbg_cyc = 1;
999
                m_core->i_dbg_stb = 1;
1000
                m_core->i_dbg_we  = 1;
1001
                m_core->i_dbg_addr = a & 1;
1002
                m_core->i_dbg_data = v;
1003
 
1004
                tick();
1005 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1006 2 dgisselq
                        tick();
1007
 
1008
                m_core->i_dbg_stb = 0;
1009 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1010 2 dgisselq
                        tick();
1011
 
1012
                // Release the bus
1013
                m_core->i_dbg_cyc = 0;
1014
                m_core->i_dbg_stb = 0;
1015
                tick();
1016
                mvprintw(0,35, "%40s", "");
1017
                mvprintw(0,40, "wb_write -- complete");
1018 36 dgisselq
 
1019
 
1020
                if (errcount >= 100)
1021
                        bomb = true;
1022 2 dgisselq
        }
1023
 
1024
        unsigned long   wb_read(unsigned a) {
1025
                unsigned int    v;
1026 36 dgisselq
                int     errcount = 0;
1027 2 dgisselq
                mvprintw(0,35, "%40s", "");
1028
                mvprintw(0,40, "wb_read(0x%08x)", a);
1029
                m_core->i_dbg_cyc = 1;
1030
                m_core->i_dbg_stb = 1;
1031
                m_core->i_dbg_we  = 0;
1032
                m_core->i_dbg_addr = a & 1;
1033
 
1034
                tick();
1035 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1036 2 dgisselq
                        tick();
1037
 
1038
                m_core->i_dbg_stb = 0;
1039 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1040 2 dgisselq
                        tick();
1041
                v = m_core->o_dbg_data;
1042
 
1043
                // Release the bus
1044
                m_core->i_dbg_cyc = 0;
1045
                m_core->i_dbg_stb = 0;
1046
                tick();
1047
 
1048
                mvprintw(0,35, "%40s", "");
1049
                mvprintw(0,40, "wb_read = 0x%08x", v);
1050
 
1051 36 dgisselq
                if (errcount >= 100)
1052
                        bomb = true;
1053 2 dgisselq
                return v;
1054
        }
1055
 
1056 34 dgisselq
        void    cursor_up(void) {
1057
                if (m_cursor > 3)
1058
                        m_cursor -= 4;
1059
        } void  cursor_down(void) {
1060
                if (m_cursor < 40)
1061
                        m_cursor += 4;
1062
        } void  cursor_left(void) {
1063
                if (m_cursor > 0)
1064
                        m_cursor--;
1065
                else    m_cursor = 43;
1066
        } void  cursor_right(void) {
1067
                if (m_cursor < 43)
1068
                        m_cursor++;
1069
                else    m_cursor = 0;
1070
        }
1071
 
1072
        int     cursor(void) { return m_cursor; }
1073 2 dgisselq
};
1074
 
1075 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1076
        int     wy, wx, ra;
1077
        int     c = tb->cursor();
1078
 
1079
        wx = (c & 0x03) * 20 + 9;
1080
        wy = (c>>2);
1081
        if (wy >= 3+4)
1082
                wy++;
1083
        if (wy > 3)
1084
                wy += 2;
1085
        wy++;
1086
 
1087
        if (c >= 12)
1088
                ra = c - 12;
1089
        else
1090
                ra = c + 32;
1091
 
1092
        bool    done = false;
1093
        char    str[16];
1094
        int     pos = 0; str[pos] = '\0';
1095
        while(!done) {
1096
                int     chv = getch();
1097
                switch(chv) {
1098
                case KEY_ESCAPE:
1099
                        pos = 0; str[pos] = '\0'; done = true;
1100
                        break;
1101
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1102
                        done = true;
1103
                        break;
1104
                case KEY_LEFT: case KEY_BACKSPACE:
1105
                        if (pos > 0) pos--;
1106
                        break;
1107 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1108 34 dgisselq
                case KEY_CLEAR:
1109
                        pos = 0;
1110
                        break;
1111
                case '0': case ' ': str[pos++] = '0'; break;
1112
                case '1': str[pos++] = '1'; break;
1113
                case '2': str[pos++] = '2'; break;
1114
                case '3': str[pos++] = '3'; break;
1115
                case '4': str[pos++] = '4'; break;
1116
                case '5': str[pos++] = '5'; break;
1117
                case '6': str[pos++] = '6'; break;
1118
                case '7': str[pos++] = '7'; break;
1119
                case '8': str[pos++] = '8'; break;
1120
                case '9': str[pos++] = '9'; break;
1121
                case 'A': case 'a': str[pos++] = 'A'; break;
1122
                case 'B': case 'b': str[pos++] = 'B'; break;
1123
                case 'C': case 'c': str[pos++] = 'C'; break;
1124
                case 'D': case 'd': str[pos++] = 'D'; break;
1125
                case 'E': case 'e': str[pos++] = 'E'; break;
1126
                case 'F': case 'f': str[pos++] = 'F'; break;
1127
                }
1128
 
1129
                if (pos > 8)
1130
                        pos = 8;
1131
                str[pos] = '\0';
1132
 
1133
                attron(A_NORMAL | A_UNDERLINE);
1134
                mvprintw(wy, wx, "%-8s", str);
1135
                if (pos > 0) {
1136
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1137
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1138
                }
1139
                attrset(A_NORMAL);
1140
        }
1141
 
1142
        if (pos > 0) {
1143
                int     v;
1144
                v = strtoul(str, NULL, 16);
1145
                if (!tb->halted()) {
1146
                        switch(ra) {
1147
                        case 15:
1148
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1149
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1150
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1151
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1152
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1153
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1154
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1155
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1156
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1157
                                }
1158
                                break;
1159
                        case 31:
1160
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1161
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1162
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1163
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1164
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1165
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1166
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1167
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1168
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1169
                                }
1170
                                break;
1171
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1172
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1173 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1174 34 dgisselq
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
1175
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1176
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1177
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1178
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1179
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1180
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1181
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1182
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1183
                        default:
1184
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1185
                                break;
1186
                        }
1187
                } else
1188
                        tb->cmd_write(ra, v);
1189
        }
1190
}
1191
 
1192 27 dgisselq
void    usage(void) {
1193
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1194
        printf("\n");
1195
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1196
        printf("\t-a\tSets the testbench to run automatically without any\n");
1197
        printf("\t\tuser interaction.\n");
1198
        printf("\n");
1199
        printf("\tUser Commands:\n");
1200
        printf("\t\tWhen the test bench is run interactively, the following\n");
1201
        printf("\t\tkey strokes are recognized:\n");
1202
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1203
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1204
        printf("\t\t\tuser intervention.\n");
1205
        printf("\t\t\'q\'\tQuit the simulation.\n");
1206
        printf("\t\t\'r\'\tReset the processor.\n");
1207
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1208
        printf("\t\t\tThis may consume more than one tick.\n");
1209
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1210
}
1211 2 dgisselq
 
1212 43 dgisselq
bool    signalled = false;
1213
 
1214
void    sigint(int v) {
1215
        signalled = true;
1216
}
1217
 
1218 2 dgisselq
int     main(int argc, char **argv) {
1219
        Verilated::commandArgs(argc, argv);
1220
        ZIPPY_TB        *tb = new ZIPPY_TB();
1221 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1222 2 dgisselq
 
1223
        // mem[0x00000] = 0xbe000010; // Halt instruction
1224
        unsigned int mptr = 0;
1225
 
1226 43 dgisselq
        signal(SIGINT, sigint);
1227
 
1228 9 dgisselq
        if (argc <= 1) {
1229 27 dgisselq
                usage();
1230
                exit(-1);
1231 9 dgisselq
        } else {
1232
                for(int argn=1; argn<argc; argn++) {
1233 27 dgisselq
                        if (argv[argn][0] == '-') {
1234
                                switch(argv[argn][1]) {
1235
                                case 'a':
1236
                                        autorun = true;
1237
                                        break;
1238
                                case 'e':
1239
                                        exit_on_done = true;
1240
                                        break;
1241
                                case 'h':
1242
                                        usage();
1243
                                        exit(0);
1244
                                        break;
1245 36 dgisselq
                                case 's':
1246
                                        autostep = true;
1247
                                        break;
1248 27 dgisselq
                                default:
1249
                                        usage();
1250
                                        exit(-1);
1251
                                        break;
1252
                                }
1253
                        } else if (access(argv[argn], R_OK)==0) {
1254 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1255
                                if (fp == NULL) {
1256
                                        printf("Cannot open %s\n", argv[argn]);
1257
                                        perror("O/S Err: ");
1258
                                        exit(-1);
1259
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1260
                                fclose(fp);
1261
                        }
1262
                }
1263
        }
1264
 
1265 27 dgisselq
        if (autorun) {
1266
                bool    done = false;
1267 2 dgisselq
 
1268 27 dgisselq
                printf("Running in non-interactive mode\n");
1269
                tb->reset();
1270
                for(int i=0; i<2; i++)
1271
                        tb->tick();
1272
                tb->m_core->v__DOT__cmd_halt = 0;
1273
                while(!done) {
1274
                        tb->tick();
1275
 
1276
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1277
                                // tb->m_core->v__DOT__cmd_halt = 0;
1278
                                // tb->m_core->v__DOT__cmd_step = 0;
1279
 
1280 34 dgisselq
                        /*
1281 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1282
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1283
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1284
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1285 34 dgisselq
                        */
1286 27 dgisselq
 
1287
                        done = (tb->test_success())||(tb->test_failure());
1288 43 dgisselq
                        done = done || signalled;
1289 27 dgisselq
                }
1290 36 dgisselq
        } else if (autostep) {
1291
                bool    done = false;
1292
 
1293
                printf("Running in non-interactive mode, via step commands\n");
1294
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1295
                while(!done) {
1296
                        tb->wb_write(CMD_REG, CMD_STEP);
1297
                        done = (tb->test_success())||(tb->test_failure());
1298 43 dgisselq
                        done = done || signalled;
1299 36 dgisselq
                }
1300 27 dgisselq
        } else { // Interactive
1301
                initscr();
1302
                raw();
1303
                noecho();
1304
                keypad(stdscr, true);
1305
 
1306
                tb->reset();
1307
                for(int i=0; i<2; i++)
1308
                        tb->tick();
1309
                tb->m_core->v__DOT__cmd_halt = 0;
1310
 
1311
                int     chv = 'q';
1312
 
1313 43 dgisselq
                bool    done = false, halted = true, manual = true,
1314
                        high_speed = false;
1315 2 dgisselq
 
1316
                halfdelay(1);
1317 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1318 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1319
                        // tb->show_state();
1320
 
1321
                while(!done) {
1322 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1323
                                struct  pollfd  fds[1];
1324
                                fds[0].fd = STDIN_FILENO;
1325
                                fds[0].events = POLLIN;
1326
                                if (poll(fds, 1, 0) > 0)
1327
                                        chv = getch();
1328
                                else
1329
                                        chv = ERR;
1330
                        } else {
1331
                                chv = getch();
1332
                        }
1333 2 dgisselq
                        switch(chv) {
1334
                        case 'h': case 'H':
1335
                                tb->wb_write(CMD_REG, CMD_HALT);
1336
                                if (!halted)
1337
                                        erase();
1338
                                halted = true;
1339
                                break;
1340 43 dgisselq
                        case 'G':
1341
                                high_speed = true;
1342
                        case 'g':
1343 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1344
                                if (halted)
1345
                                        erase();
1346
                                halted = false;
1347
                                manual = false;
1348
                                break;
1349 43 dgisselq
                        case 'm':
1350
                                tb->show_user_timers(false);
1351
                                break;
1352 2 dgisselq
                        case 'q': case 'Q':
1353
                                done = true;
1354
                                break;
1355
                        case 'r': case 'R':
1356 36 dgisselq
                                if (manual)
1357
                                        tb->reset();
1358
                                else
1359
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1360 2 dgisselq
                                halted = true;
1361
                                erase();
1362
                                break;
1363 39 dgisselq
                        case 's':
1364 34 dgisselq
                                if (!halted)
1365 27 dgisselq
                                        erase();
1366 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1367
                                manual = false;
1368 34 dgisselq
                                halted = true;
1369 43 dgisselq
                                high_speed = false;
1370 2 dgisselq
                                break;
1371 39 dgisselq
                        case 'S':
1372 34 dgisselq
                                if ((!manual)||(halted))
1373 27 dgisselq
                                        erase();
1374 2 dgisselq
                                manual = true;
1375 39 dgisselq
                                halted = true;
1376 43 dgisselq
                                high_speed = false;
1377 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1378
                                tb->m_core->v__DOT__cmd_step = 1;
1379
                                tb->eval();
1380
                                tb->tick();
1381
                                break;
1382
                        case 'T': // 
1383
                                if ((!manual)||(halted))
1384
                                        erase();
1385
                                manual = true;
1386
                                halted = true;
1387 43 dgisselq
                                high_speed = false;
1388 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1389
                                tb->m_core->v__DOT__cmd_step = 0;
1390
                                tb->eval();
1391
                                tb->tick();
1392
                                break;
1393
                        case 't':
1394
                                if ((!manual)||(halted))
1395
                                        erase();
1396
                                manual = true;
1397 34 dgisselq
                                halted = false;
1398 43 dgisselq
                                high_speed = false;
1399 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1400
                //              tb->m_core->v__DOT__cmd_halt = 0;
1401
                //              tb->m_core->v__DOT__cmd_step = 0;
1402 2 dgisselq
                                tb->tick();
1403
                                break;
1404 43 dgisselq
                        case 'u':
1405
                                tb->show_user_timers(true);
1406
                                break;
1407 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1408
                                get_value(tb);
1409
                                break;
1410
                        case    KEY_UP:         tb->cursor_up();        break;
1411
                        case    KEY_DOWN:       tb->cursor_down();      break;
1412
                        case    KEY_LEFT:       tb->cursor_left();      break;
1413
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1414 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1415 34 dgisselq
                        case ERR: case KEY_CLEAR:
1416 2 dgisselq
                        default:
1417
                                if (!manual)
1418
                                        tb->tick();
1419
                        }
1420
 
1421
                        if (manual) {
1422
                                tb->show_state();
1423
                        } else if (halted) {
1424
                                if (tb->dbg_fp)
1425
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1426
                                tb->read_state();
1427
                        } else
1428
                                tb->show_state();
1429
 
1430
                        if (tb->m_core->i_rst)
1431
                                done =true;
1432 43 dgisselq
                        if ((tb->bomb)||(signalled))
1433 2 dgisselq
                                done = true;
1434 27 dgisselq
 
1435
                        if (exit_on_done) {
1436
                                if (tb->test_success())
1437
                                        done = true;
1438
                                if (tb->test_failure())
1439
                                        done = true;
1440
                        }
1441 2 dgisselq
                }
1442 27 dgisselq
                endwin();
1443
        }
1444
#ifdef  MANUAL_STEPPING_MODE
1445
         else { // Manual stepping mode
1446 2 dgisselq
                tb->show_state();
1447
 
1448
                while('q' != tolower(chv = getch())) {
1449
                        tb->tick();
1450
                        tb->show_state();
1451
 
1452
                        if (tb->test_success())
1453
                                break;
1454
                        else if (tb->test_failure())
1455
                                break;
1456 43 dgisselq
                        else if (signalled)
1457
                                break;
1458 2 dgisselq
                }
1459
        }
1460 27 dgisselq
#endif
1461 2 dgisselq
 
1462 43 dgisselq
        printf("\n");
1463 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1464
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1465 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1466 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1467
                printf("Instructions / Clock: %.2f\n",
1468
                        (double)tb->m_core->v__DOT__mic_data
1469
                        / (double)tb->m_core->v__DOT__mtc_data);
1470 36 dgisselq
 
1471
        int     rcode = 0;
1472
        if (tb->bomb) {
1473
                printf("TEST BOMBED\n");
1474
                rcode = -1;
1475
        } else if (tb->test_success()) {
1476 2 dgisselq
                printf("SUCCESS!\n");
1477 36 dgisselq
        } else if (tb->test_failure()) {
1478
                rcode = -2;
1479 2 dgisselq
                printf("TEST FAILED!\n");
1480 36 dgisselq
        } else
1481 27 dgisselq
                printf("User quit\n");
1482 43 dgisselq
        delete tb;
1483 36 dgisselq
        exit(rcode);
1484 2 dgisselq
}
1485
 

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