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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 58

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Tecnology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 2 dgisselq
// No particular "parameters" need definition or redefinition here.
71
class   ZIPPY_TB : public TESTB<Vzipsystem> {
72
public:
73 9 dgisselq
        unsigned long   m_mem_size;
74 2 dgisselq
        MEMSIM          m_mem;
75
        // QSPIFLASHSIM m_flash;
76 58 dgisselq
        FILE            *dbg_fp, *m_profile_fp;
77 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
78 34 dgisselq
        int             m_cursor;
79 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
80 2 dgisselq
 
81 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
82 43 dgisselq
                if (false) {
83 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
84
                        dbg_flag = true;
85
                } else {
86
                        dbg_fp = NULL;
87
                        dbg_flag = false;
88
                }
89 2 dgisselq
                bomb = false;
90 34 dgisselq
                m_cursor = 0;
91 43 dgisselq
                m_show_user_timers = false;
92 58 dgisselq
 
93
                m_last_instruction_tickcount = 0l;
94
                if (true) {
95
                        m_profile_fp = fopen("pfile.bin","wb");
96
                } else {
97
                        m_profile_fp = NULL;
98
                }
99 2 dgisselq
        }
100
 
101
        void    reset(void) {
102
                // m_flash.debug(false);
103
                TESTB<Vzipsystem>::reset();
104
        }
105
 
106
        bool    on_tick(void) {
107
                tick();
108
                return true;
109
        }
110
 
111 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
112
                if (c)
113
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
114
                else
115
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
116 2 dgisselq
        }
117
 
118 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
119 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
120 34 dgisselq
                if (c)
121
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
122
                else
123
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
124 2 dgisselq
        }
125
 
126 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
127 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
128 34 dgisselq
                if (c)
129
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
130
                else
131
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
132 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
133
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
134
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
135 34 dgisselq
                        ?'a':((c)?'<':' '));
136 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
137
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
138
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
139 34 dgisselq
                        ?'b':((c)?'<':' '));
140 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
141
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
142 34 dgisselq
                        ?'W':((c)?'<':' '));
143 2 dgisselq
        }
144
 
145
        void    showins(int y, const char *lbl, const int ce, const int valid,
146
                        const int gie, const int stall, const unsigned int pc) {
147
                char    line[80];
148
 
149
                if (ce)
150
                        mvprintw(y, 0, "Ck ");
151
                else
152
                        mvprintw(y, 0, "   ");
153
                if (stall)
154
                        printw("Stl ");
155
                else
156
                        printw("    ");
157
                printw("%s: 0x%08x", lbl, pc);
158
 
159
                if (valid) {
160
                        if (gie) attroff(A_BOLD);
161
                        else    attron(A_BOLD);
162
                        zipi_to_string(m_mem[pc], line);
163 27 dgisselq
                        printw("  %-24s", &line[1]);
164 2 dgisselq
                } else {
165
                        attroff(A_BOLD);
166
                        printw("  (0x%08x)%28s", m_mem[pc],"");
167
                }
168
                attroff(A_BOLD);
169
        }
170
 
171
        void    dbgins(const char *lbl, const int ce, const int valid,
172
                        const int gie, const int stall, const unsigned int pc) {
173
                char    line[80];
174
 
175
                if (!dbg_fp)
176
                        return;
177
 
178
                if (ce)
179
                        fprintf(dbg_fp, "%s Ck ", lbl);
180
                else
181
                        fprintf(dbg_fp, "%s    ", lbl);
182
                if (stall)
183
                        fprintf(dbg_fp, "Stl ");
184
                else
185
                        fprintf(dbg_fp, "    ");
186
                fprintf(dbg_fp, "0x%08x:  ", pc);
187
 
188
                if (valid) {
189
                        zipi_to_string(m_mem[pc], line);
190
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
191
                } else {
192
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
193
                }
194
        }
195
 
196
        void    show_state(void) {
197
                int     ln= 0;
198
 
199
                mvprintw(ln,0, "Peripherals-SS"); ln++;
200 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
201 36 dgisselq
                printw(" %s",
202
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
203
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
204
                        );
205 39 dgisselq
#endif
206
 
207
#ifdef  OPT_EARLY_BRANCHING
208
                printw(" %s%s",
209 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
210 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
211
#endif
212 36 dgisselq
 
213
                /*
214 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
215
                        mvprintw(ln, 17, "%s%s",
216
                                ((m_core->v__DOT__sys_cyc)
217
                                &&(m_core->v__DOT__sys_we)
218
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
219
                                (m_core->v__DOT__trap_int)?"I":" ");
220
                */
221 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
222
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
223 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
224 57 dgisselq
 
225
                if (!m_show_user_timers) {
226
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
227
                } else {
228
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
229
                }
230
 
231 34 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
232 2 dgisselq
 
233
                ln++;
234 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
235
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
236
                showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
237
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
238 2 dgisselq
 
239 43 dgisselq
 
240
                if (!m_show_user_timers) {
241
                        ln++;
242
                        showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
243
                        showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
244
                        showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
245
                        showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
246
                } else {
247
                        ln++;
248
                        showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
249
                        showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
250
                        showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
251
                        showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
252
                }
253 2 dgisselq
 
254
                ln++;
255
                mvprintw(ln, 40, "%s %s",
256
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
257
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
258 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
259 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
260
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
261
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
262 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
263
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
264
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
265 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
266
                        attroff(A_BOLD);
267
                else
268
                        attron(A_BOLD);
269
                mvprintw(ln, 0, "Supervisor Registers");
270
                ln++;
271
 
272 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
273
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
274
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
275
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
276 2 dgisselq
 
277 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
278
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
279
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
280
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
281 2 dgisselq
 
282 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
283
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
284
                showreg(ln,40, "sR10", 10, (m_cursor==22));
285
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
286 2 dgisselq
 
287 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
288
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
289 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
290
                        (m_cursor==26)?">":" ",
291
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
292
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
293
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
294
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
295
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
296 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
297
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
298
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
299
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
300 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
301 2 dgisselq
                ln++;
302
 
303
                if (m_core->v__DOT__thecpu__DOT__gie)
304
                        attron(A_BOLD);
305
                else
306
                        attroff(A_BOLD);
307
                mvprintw(ln, 0, "User Registers"); ln++;
308 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
309
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
310
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
311
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
312 2 dgisselq
 
313 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
314
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
315
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
316
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
317 2 dgisselq
 
318 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
319
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
320
                showreg(ln,40, "uR10", 26, (m_cursor==38));
321
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
322 2 dgisselq
 
323 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
324
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
325 43 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
326
                        (m_cursor == 42)?'>':' ',
327 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
328
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
329
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
330
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
331 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
332
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
333
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
334
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
335 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
336 2 dgisselq
 
337
                attroff(A_BOLD);
338
                ln+=1;
339
 
340 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
341
        ln+=2;
342
#else
343 36 dgisselq
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
344 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
345
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
346
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
347
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
348 4 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
349 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
350
                        m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
351
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
352
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
353 2 dgisselq
                ln++;
354
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
355
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
356
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
357
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
358
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
359
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
360
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
361 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
362 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
363 39 dgisselq
#endif
364 2 dgisselq
 
365
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
366 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
367
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
368
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
369
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
370 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
371
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
372
                        (m_core->v__DOT__thecpu__DOT__mem_data),
373
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
374 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
375 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
376
// #define      OPT_PIPELINED_BUS_ACCESS
377
#ifdef  OPT_PIPELINED_BUS_ACCESS
378
                printw(" %x%x%c%c",
379
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
380
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
381
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
382
                        (mem_pipe_stalled())?'S':'-'); ln++;
383
#else
384
                ln++;
385
#endif
386 2 dgisselq
 
387 36 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
388
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
389 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
390
                        (m_core->o_wb_stb)?"STB":"   ",
391
                        (m_core->o_wb_we )?"WE":"  ",
392
                        (m_core->o_wb_addr),
393
                        (m_core->o_wb_data),
394
                        (m_core->i_wb_ack)?"ACK":"   ",
395
                        (m_core->i_wb_stall)?"STL":"   ",
396
                        (m_core->i_wb_data)); ln+=2;
397 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
398
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
399
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
400 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
401
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
402
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
403
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
404 58 dgisselq
                        (!mem_stalled()),       //1
405 2 dgisselq
 
406 58 dgisselq
                        (mem_stalled()),
407 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
408
                        (m_core->v__DOT__thecpu__DOT__master_ce),
409
                        (mem_pipe_stalled()),
410
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
411 57 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
412
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
413
#else
414
                        (m_core->v__DOT__thecpu__DOT__mem_busy)
415
#endif
416
                        );
417 39 dgisselq
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
418
                        (m_core->v__DOT__thecpu__DOT__dcdvalid),
419
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
420
                        (m_core->v__DOT__thecpu__DOT__dcdM),
421
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
422
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
423
                        (m_core->v__DOT__thecpu__DOT__dcdB
424
                                == m_core->v__DOT__thecpu__DOT__op_B),
425
                        (m_core->v__DOT__thecpu__DOT__r_dcdI
426
                                == m_core->v__DOT__thecpu__DOT__r_opI),
427
                        (m_core->v__DOT__thecpu__DOT__r_dcdI+1
428
                                == m_core->v__DOT__thecpu__DOT__r_opI));
429
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
430
                        (m_core->v__DOT__thecpu__DOT__r_dcdI),
431
                        (m_core->v__DOT__thecpu__DOT__r_opI));
432
#endif
433
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
434 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
435
                printw(" A:%c%c B:%c%c",
436 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
437
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
438 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
439
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
440
#endif
441 39 dgisselq
 
442
 
443 2 dgisselq
                showins(ln, "I ",
444
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
445
                        m_core->v__DOT__thecpu__DOT__pf_valid,
446
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
447
                        m_core->v__DOT__thecpu__DOT__gie,
448
                        0,
449 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
450
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
451 2 dgisselq
 
452
                showins(ln, "Dc",
453
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
454
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
455
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
456
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
457
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
458 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
459
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
460
                        mvprintw(ln-1,10,"I");
461
                else
462
#endif
463
                if (m_core->v__DOT__thecpu__DOT__dcdM)
464
                        mvprintw(ln-1,10,"M");
465 2 dgisselq
 
466
                showins(ln, "Op",
467
                        m_core->v__DOT__thecpu__DOT__op_ce,
468
                        m_core->v__DOT__thecpu__DOT__opvalid,
469
                        m_core->v__DOT__thecpu__DOT__op_gie,
470
                        m_core->v__DOT__thecpu__DOT__op_stall,
471 39 dgisselq
                        op_pc()); ln++;
472
#ifdef  OPT_ILLEGAL_INSTRUCTION
473
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
474
                        mvprintw(ln-1,10,"I");
475
                else
476
#endif
477
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
478
                        mvprintw(ln-1,10,"M");
479
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
480
                        mvprintw(ln-1,10,"A");
481 2 dgisselq
 
482
                showins(ln, "Al",
483
                        m_core->v__DOT__thecpu__DOT__alu_ce,
484
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
485
                        m_core->v__DOT__thecpu__DOT__alu_gie,
486
                        m_core->v__DOT__thecpu__DOT__alu_stall,
487 39 dgisselq
                        alu_pc()); ln++;
488
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
489
                        mvprintw(ln-1,10,"W");
490 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
491
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
492
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
493
                        mvprintw(ln-1,10,"v");
494 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
495 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
496
                        mvprintw(ln-1,10,"I");
497 58 dgisselq
#endif
498 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
499
                        // mvprintw(ln-1,10,"i");
500 2 dgisselq
 
501 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
502 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
503
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
504 2 dgisselq
                mvprintw(ln-4, 48,
505
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
506
                printw("(%s:%02x,%x)",
507
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
508
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
509
                        (m_core->v__DOT__thecpu__DOT__op_gie)
510
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
511
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
512
 
513
                printw("(%s%s%s:%02x)",
514
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
515
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
516
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
517
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
518
                /*
519
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
520
                        m_core->v__DOT__thecpu__DOT__dcdI);
521
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
522
                        m_core->v__DOT__thecpu__DOT__opB);
523
                */
524 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
525 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
526 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
527
                        m_core->v__DOT__thecpu__DOT__r_opB);
528
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
529
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
530
                else
531
                        printw("%8s","");
532 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
533 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
534 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
535
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
536 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
537 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
538 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
539
        }
540
 
541 43 dgisselq
        void    show_user_timers(bool v) {
542
                m_show_user_timers = v;
543
        }
544
 
545 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
546 57 dgisselq
                int     errcount = 0;
547 2 dgisselq
                if (dbg_fp) {
548
                        dbg_flag= true;
549
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
550
                }
551
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
552 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
553
                        errcount++;
554
                if (errcount >= MAXERR) {
555
                        endwin();
556
 
557
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
558
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
559
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
560
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
561
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
562
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
563
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
564
                        printf("dcdvalid       = %d\n", m_core->v__DOT__thecpu__DOT__dcdvalid);
565
                        printf("dcd_ce         = %d\n", m_core->v__DOT__thecpu__DOT__dcd_ce);
566
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
567
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
568
                        printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch);
569
                        printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb);
570
 
571
                        exit(-2);
572
                }
573
 
574
                assert(errcount < MAXERR);
575 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
576
 
577
                if (dbg_flag)
578
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
579
                                v);
580
                dbg_flag = false;
581
                return v;
582
        }
583
 
584 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
585 57 dgisselq
                int     errcount = 0;
586 34 dgisselq
                if ((a&0x0f)==0x0f)
587
                        dbg_flag = true;
588
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
589 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
590
                        errcount++;
591
                assert(errcount < MAXERR);
592 34 dgisselq
                if (dbg_flag)
593
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
594
                wb_write(CMD_DATA, v);
595
        }
596
 
597 27 dgisselq
        bool    halted(void) {
598
                return (m_core->v__DOT__cmd_halt != 0);
599
        }
600
 
601 2 dgisselq
        void    read_state(void) {
602
                int     ln= 0;
603 34 dgisselq
                bool    gie;
604 2 dgisselq
 
605 34 dgisselq
                if (m_cursor < 0)
606
                        m_cursor = 0;
607
                else if (m_cursor >= 44)
608
                        m_cursor = 43;
609
 
610
                mvprintw(ln,0, "Peripherals-RS");
611
                mvprintw(ln,40,"%-40s", "CPU State: ");
612
                {
613
                        unsigned int v = wb_read(CMD_REG);
614
                        mvprintw(ln,51, "");
615
                        if (v & 0x010000)
616
                                printw("EXT-INT ");
617
                        if ((v & 0x003000) == 0x03000)
618
                                printw("Halted ");
619
                        else if (v & 0x001000)
620
                                printw("Sleeping ");
621
                        else if (v & 0x002000)
622
                                printw("Supervisor Mod ");
623
                        if (v & 0x008000)
624
                                printw("Break-Enabled ");
625
                        if (v & 0x000080)
626
                                printw("PIC Enabled ");
627
                } ln++;
628
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
629
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
630 57 dgisselq
                showval(ln,40, "WBUS", cmd_read(32+ 2), false);
631 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
632 2 dgisselq
                ln++;
633 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
634
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
635
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
636
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
637 2 dgisselq
 
638
                ln++;
639 43 dgisselq
                if (!m_show_user_timers) {
640
                        showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
641
                        showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
642
                        showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
643
                        showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
644
                } else {
645
                        showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
646
                        showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
647
                        showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
648
                        showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
649
                }
650 2 dgisselq
 
651
                ln++;
652
                ln++;
653
                unsigned int cc = cmd_read(14);
654
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
655
                        m_core->v__DOT__thecpu__DOT__gie);
656 34 dgisselq
                gie = (cc & 0x020);
657
                if (gie)
658 2 dgisselq
                        attroff(A_BOLD);
659
                else
660
                        attron(A_BOLD);
661
                mvprintw(ln, 0, "Supervisor Registers");
662
                ln++;
663
 
664 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
665
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
666
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
667
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
668 2 dgisselq
 
669 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
670
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
671
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
672
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
673 2 dgisselq
 
674 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
675
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
676
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
677
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
678 2 dgisselq
 
679 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
680
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
681 2 dgisselq
 
682 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
683 34 dgisselq
                        (m_cursor==26)?">":" ",
684 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
685
                        (cc & 0x080)?"BK":"  ",
686 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
687
                        (cc & 0x020)?"IE":"  ",
688
                        (cc & 0x010)?"SL":"  ",
689 2 dgisselq
                        (cc&8)?"V":" ",
690
                        (cc&4)?"N":" ",
691
                        (cc&2)?"C":" ",
692
                        (cc&1)?"Z":" ");
693 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
694 2 dgisselq
                ln++;
695
 
696 34 dgisselq
                if (gie)
697 2 dgisselq
                        attron(A_BOLD);
698
                else
699
                        attroff(A_BOLD);
700
                mvprintw(ln, 0, "User Registers"); ln++;
701 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
702
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
703
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
704
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
705 2 dgisselq
 
706 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
707
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
708
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
709
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
710 2 dgisselq
 
711 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
712
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
713
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
714
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
715 2 dgisselq
 
716 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
717
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
718 2 dgisselq
                cc = cmd_read(30);
719 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
720 36 dgisselq
                        (m_cursor == 42)?'>':' ',
721 34 dgisselq
                        (cc&0x100)?"TP":"  ",
722
                        (cc&0x040)?"ST":"  ",
723
                        (cc&0x020)?"IE":"  ",
724
                        (cc&0x010)?"SL":"  ",
725 2 dgisselq
                        (cc&8)?"V":" ",
726
                        (cc&4)?"N":" ",
727
                        (cc&2)?"C":" ",
728
                        (cc&1)?"Z":" ");
729 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
730 2 dgisselq
 
731
                attroff(A_BOLD);
732
                ln+=2;
733
 
734
                ln+=3;
735
 
736
                showins(ln, "I ",
737
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
738
                        m_core->v__DOT__thecpu__DOT__pf_valid,
739
                        m_core->v__DOT__thecpu__DOT__gie,
740
                        0,
741 57 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
742
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
743 2 dgisselq
 
744
                showins(ln, "Dc",
745
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
746
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
747
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
748
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
749
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
750
 
751
                showins(ln, "Op",
752
                        m_core->v__DOT__thecpu__DOT__op_ce,
753
                        m_core->v__DOT__thecpu__DOT__opvalid,
754
                        m_core->v__DOT__thecpu__DOT__op_gie,
755
                        m_core->v__DOT__thecpu__DOT__op_stall,
756 39 dgisselq
                        op_pc()); ln++;
757 2 dgisselq
 
758
                showins(ln, "Al",
759
                        m_core->v__DOT__thecpu__DOT__alu_ce,
760
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
761
                        m_core->v__DOT__thecpu__DOT__alu_gie,
762
                        m_core->v__DOT__thecpu__DOT__alu_stall,
763 39 dgisselq
                        alu_pc()); ln++;
764 2 dgisselq
        }
765
        void    tick(void) {
766
                int gie = m_core->v__DOT__thecpu__DOT__gie;
767
                /*
768
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
769
                                                m_core->o_qspi_sck,
770
                                                m_core->o_qspi_dat);
771
                */
772
 
773 11 dgisselq
                int stb = m_core->o_wb_stb;
774
                if ((m_core->o_wb_addr & (-1<<20))!=1)
775
                        stb = 0;
776
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
777
                        m_core->i_wb_ack = 1;
778 2 dgisselq
 
779
                if ((dbg_flag)&&(dbg_fp)) {
780 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
781 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
782
                                (m_core->i_dbg_stb)?"STB":
783
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
784
                                ((m_core->i_dbg_we)?"WE":"  "),
785
                                (m_core->i_dbg_addr),0,
786
                                m_core->i_dbg_data,
787
                                (m_core->o_dbg_ack)?"ACK":"   ",
788
                                (m_core->o_dbg_stall)?"STALL":"     ",
789
                                (m_core->o_dbg_data),
790
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
791
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
792
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
793
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
794
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
795 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
796
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
797 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
798
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
799
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
800
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
801
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
802
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
803
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
804
                                (m_core->v__DOT__sys_we)?"WE":"  ",
805
                                (m_core->v__DOT__sys_addr),
806
                                (m_core->v__DOT__dbg_addr),
807
                                (m_core->v__DOT__sys_data),
808
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
809
                                (m_core->v__DOT__wb_data));
810
                }
811
 
812
                if (dbg_fp)
813
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
814
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
815
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
816
                                m_core->v__DOT__thecpu__DOT__op_ce,
817 39 dgisselq
                                op_pc(),
818 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcdA,
819
                                m_core->v__DOT__thecpu__DOT__opR,
820
                                m_core->v__DOT__cmd_halt,
821
                                m_core->v__DOT__cpu_halt,
822
                                m_core->v__DOT__thecpu__DOT__alu_ce,
823
                                m_core->v__DOT__thecpu__DOT__alu_valid,
824
                                m_core->v__DOT__thecpu__DOT__alu_wr,
825
                                m_core->v__DOT__thecpu__DOT__alu_reg,
826
                                m_core->v__DOT__thecpu__DOT__ipc,
827
                                m_core->v__DOT__thecpu__DOT__upc);
828
 
829
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
830
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
831
                                m_core->v__DOT__pic_interrupt,
832
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
833
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
834
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
835
                                m_core->v__DOT__cmd_addr,
836
                                m_core->v__DOT__dbg_idata,
837
                                m_core->v__DOT__thecpu__DOT__master_ce,
838
                                m_core->v__DOT__thecpu__DOT__alu_wr,
839
                                m_core->v__DOT__thecpu__DOT__alu_valid,
840
                                m_core->v__DOT__thecpu__DOT__mem_valid);
841
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
842
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
843
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
844
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
845
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
846
                                m_core->v__DOT__cmd_addr,
847
                                m_core->v__DOT__dbg_idata,
848
                                m_core->v__DOT__thecpu__DOT__master_ce,
849
                                m_core->v__DOT__thecpu__DOT__alu_wr,
850
                                m_core->v__DOT__thecpu__DOT__alu_valid,
851
                                m_core->v__DOT__thecpu__DOT__mem_valid,
852
                                m_core->v__DOT__thecpu__DOT__w_iflags,
853
                                m_core->v__DOT__thecpu__DOT__w_uflags);
854 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
855
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
856 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
857
                                m_core->v__DOT__thecpu__DOT__op_break);
858 36 dgisselq
                } else if ((dbg_fp)&&
859
                                ((m_core->v__DOT__thecpu__DOT__op_break)
860
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
861
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
862
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
863
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
864
                                m_core->v__DOT__thecpu__DOT__break_en,
865
                                m_core->v__DOT__thecpu__DOT__dcd_break,
866
                                m_core->v__DOT__thecpu__DOT__op_break);
867 2 dgisselq
                }
868
 
869 34 dgisselq
                if (dbg_fp) {
870
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
871
                                fprintf(dbg_fp, "\tClear Pipeline\n");
872
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
873
                                fprintf(dbg_fp, "\tNew PC\n");
874
                }
875
 
876 36 dgisselq
                if (dbg_fp)
877
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
878
                if (false) {
879
                        m_core->i_clk = 1;
880
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
881
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
882
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
883
                        eval();
884
                        m_core->i_clk = 0;
885
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
886
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
887
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
888
                        eval();
889
                        m_tickcount++;
890
                } else {
891
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
892
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
893
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
894 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
895
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
896
                                m_core->i_wb_err = 1;
897
                        else
898
                                m_core->i_wb_err = 0;
899 36 dgisselq
                        TESTB<Vzipsystem>::tick();
900
                }
901 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
902
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
903
                                (gie)?"User":"Supervisor",
904
                                (gie)?"Supervisor":"User",
905
                                m_core->v__DOT__thecpu__DOT__ipc,
906
                                m_core->v__DOT__thecpu__DOT__upc,
907
                                m_core->v__DOT__thecpu__DOT__pf_pc);
908
                } if (dbg_fp) {
909 57 dgisselq
                        dbgins("Dc - ", m_core->v__DOT__thecpu__DOT__dcd_ce,
910
                                m_core->v__DOT__thecpu__DOT__dcdvalid,
911
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
912
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
913
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1);
914 2 dgisselq
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
915
                                m_core->v__DOT__thecpu__DOT__opvalid,
916
                                m_core->v__DOT__thecpu__DOT__op_gie,
917
                                m_core->v__DOT__thecpu__DOT__op_stall,
918 39 dgisselq
                                op_pc());
919 57 dgisselq
/*
920
#ifdef  OPT_SINGLE_CYCLE
921
                        fprintf(dbg_fp, "\t\t  A = %08x,   B = %08x, I = %08x, B+I = %08x, %c%c %s%s%s[%2x] = %08x %s\n",
922
                                m_core->v__DOT__thecpu__DOT__r_opA,
923
                                m_core->v__DOT__thecpu__DOT__r_opB,
924
                                m_core->v__DOT__thecpu__DOT__w_opBnI,
925
                                m_core->v__DOT__thecpu__DOT__r_dcdI,
926
                                (m_core->v__DOT__thecpu__DOT__opvalid_alu)?'A':'-',
927
                                (m_core->v__DOT__thecpu__DOT__opvalid_mem)?'M':'-',
928
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"W":" ",
929
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"A":"M",
930
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"k":"-",
931
                                (m_core->v__DOT__thecpu__DOT__wr_reg_id),
932
                                (m_core->v__DOT__thecpu__DOT__wr_reg_vl),
933
                                (m_core->v__DOT__thecpu__DOT__mem_rdbusy)?"Mem-RdBusy":
934
                                ((m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)?"Mem-Busy":""));
935
                        fprintf(dbg_fp, "\t\topA = %08x, opB = %08x, alu_result = %08x\n",
936
                                m_core->v__DOT__thecpu__DOT__opA,
937
                                m_core->v__DOT__thecpu__DOT__opB,
938
                                m_core->v__DOT__thecpu__DOT__alu_result);
939
#endif
940
*/
941 2 dgisselq
                        dbgins("Al - ",
942
                                m_core->v__DOT__thecpu__DOT__alu_ce,
943
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
944
                                m_core->v__DOT__thecpu__DOT__alu_gie,
945
                                m_core->v__DOT__thecpu__DOT__alu_stall,
946 39 dgisselq
                                alu_pc());
947 2 dgisselq
 
948
                }
949 58 dgisselq
 
950
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
951
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
952
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
953
                        if (m_profile_fp) {
954
                                unsigned buf[2];
955
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
956
                                buf[1] = iticks;
957
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
958
                        }
959
                        m_last_instruction_tickcount = m_tickcount;
960
                }
961 2 dgisselq
        }
962
 
963
        bool    test_success(void) {
964
                return ((!m_core->v__DOT__thecpu__DOT__gie)
965
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
966
        }
967
 
968 39 dgisselq
        unsigned        op_pc(void) {
969
                /*
970
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
971
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
972
                        r--;
973
                return r;
974
                */
975
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
976
        }
977
 
978 58 dgisselq
        bool    mem_busy(void) {
979
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
980
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
981
        }
982
 
983
        bool    mem_stalled(void) {
984
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
985
 
986
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
987
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
988
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
989
 
990
                a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
991
                b = (m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
992
                d = ((wr_write_pc)||(wr_write_cc));
993
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
994
                        &&((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)==op_gie)
995
                        &&d);
996
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
997
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
998
        }
999
 
1000 39 dgisselq
        unsigned        alu_pc(void) {
1001
                /*
1002
                unsigned        r = op_pc();
1003
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1004
                        r--;
1005
                return r;
1006
                */
1007
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1008
        }
1009
 
1010
#ifdef  OPT_PIPELINED_BUS_ACCESS
1011
        int     mem_pipe_stalled(void) {
1012
                int     r = 0;
1013
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1014
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1015
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1016
                        ||(
1017
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1018
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1019
                return r;
1020
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1021
        }
1022
#endif
1023
 
1024 2 dgisselq
        bool    test_failure(void) {
1025 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1026
                        return 0;
1027
                else if (m_core->v__DOT__thecpu__DOT__gie)
1028
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
1029
                else
1030
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
1031
                /*
1032 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1033 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1034 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1035 43 dgisselq
                */
1036 2 dgisselq
        }
1037
 
1038
        void    wb_write(unsigned a, unsigned int v) {
1039 36 dgisselq
                int     errcount = 0;
1040 2 dgisselq
                mvprintw(0,35, "%40s", "");
1041
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1042
                m_core->i_dbg_cyc = 1;
1043
                m_core->i_dbg_stb = 1;
1044
                m_core->i_dbg_we  = 1;
1045
                m_core->i_dbg_addr = a & 1;
1046
                m_core->i_dbg_data = v;
1047
 
1048
                tick();
1049 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1050 2 dgisselq
                        tick();
1051
 
1052
                m_core->i_dbg_stb = 0;
1053 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1054 2 dgisselq
                        tick();
1055
 
1056
                // Release the bus
1057
                m_core->i_dbg_cyc = 0;
1058
                m_core->i_dbg_stb = 0;
1059
                tick();
1060
                mvprintw(0,35, "%40s", "");
1061
                mvprintw(0,40, "wb_write -- complete");
1062 36 dgisselq
 
1063
 
1064
                if (errcount >= 100)
1065
                        bomb = true;
1066 2 dgisselq
        }
1067
 
1068
        unsigned long   wb_read(unsigned a) {
1069
                unsigned int    v;
1070 36 dgisselq
                int     errcount = 0;
1071 2 dgisselq
                mvprintw(0,35, "%40s", "");
1072
                mvprintw(0,40, "wb_read(0x%08x)", a);
1073
                m_core->i_dbg_cyc = 1;
1074
                m_core->i_dbg_stb = 1;
1075
                m_core->i_dbg_we  = 0;
1076
                m_core->i_dbg_addr = a & 1;
1077
 
1078
                tick();
1079 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1080 2 dgisselq
                        tick();
1081
 
1082
                m_core->i_dbg_stb = 0;
1083 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1084 2 dgisselq
                        tick();
1085
                v = m_core->o_dbg_data;
1086
 
1087
                // Release the bus
1088
                m_core->i_dbg_cyc = 0;
1089
                m_core->i_dbg_stb = 0;
1090
                tick();
1091
 
1092
                mvprintw(0,35, "%40s", "");
1093
                mvprintw(0,40, "wb_read = 0x%08x", v);
1094
 
1095 36 dgisselq
                if (errcount >= 100)
1096
                        bomb = true;
1097 2 dgisselq
                return v;
1098
        }
1099
 
1100 34 dgisselq
        void    cursor_up(void) {
1101
                if (m_cursor > 3)
1102
                        m_cursor -= 4;
1103
        } void  cursor_down(void) {
1104
                if (m_cursor < 40)
1105
                        m_cursor += 4;
1106
        } void  cursor_left(void) {
1107
                if (m_cursor > 0)
1108
                        m_cursor--;
1109
                else    m_cursor = 43;
1110
        } void  cursor_right(void) {
1111
                if (m_cursor < 43)
1112
                        m_cursor++;
1113
                else    m_cursor = 0;
1114
        }
1115
 
1116
        int     cursor(void) { return m_cursor; }
1117 2 dgisselq
};
1118
 
1119 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1120
        int     wy, wx, ra;
1121
        int     c = tb->cursor();
1122
 
1123
        wx = (c & 0x03) * 20 + 9;
1124
        wy = (c>>2);
1125
        if (wy >= 3+4)
1126
                wy++;
1127
        if (wy > 3)
1128
                wy += 2;
1129
        wy++;
1130
 
1131
        if (c >= 12)
1132
                ra = c - 12;
1133
        else
1134
                ra = c + 32;
1135
 
1136
        bool    done = false;
1137
        char    str[16];
1138
        int     pos = 0; str[pos] = '\0';
1139
        while(!done) {
1140
                int     chv = getch();
1141
                switch(chv) {
1142
                case KEY_ESCAPE:
1143
                        pos = 0; str[pos] = '\0'; done = true;
1144
                        break;
1145
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1146
                        done = true;
1147
                        break;
1148
                case KEY_LEFT: case KEY_BACKSPACE:
1149
                        if (pos > 0) pos--;
1150
                        break;
1151 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1152 34 dgisselq
                case KEY_CLEAR:
1153
                        pos = 0;
1154
                        break;
1155
                case '0': case ' ': str[pos++] = '0'; break;
1156
                case '1': str[pos++] = '1'; break;
1157
                case '2': str[pos++] = '2'; break;
1158
                case '3': str[pos++] = '3'; break;
1159
                case '4': str[pos++] = '4'; break;
1160
                case '5': str[pos++] = '5'; break;
1161
                case '6': str[pos++] = '6'; break;
1162
                case '7': str[pos++] = '7'; break;
1163
                case '8': str[pos++] = '8'; break;
1164
                case '9': str[pos++] = '9'; break;
1165
                case 'A': case 'a': str[pos++] = 'A'; break;
1166
                case 'B': case 'b': str[pos++] = 'B'; break;
1167
                case 'C': case 'c': str[pos++] = 'C'; break;
1168
                case 'D': case 'd': str[pos++] = 'D'; break;
1169
                case 'E': case 'e': str[pos++] = 'E'; break;
1170
                case 'F': case 'f': str[pos++] = 'F'; break;
1171
                }
1172
 
1173
                if (pos > 8)
1174
                        pos = 8;
1175
                str[pos] = '\0';
1176
 
1177
                attron(A_NORMAL | A_UNDERLINE);
1178
                mvprintw(wy, wx, "%-8s", str);
1179
                if (pos > 0) {
1180
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1181
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1182
                }
1183
                attrset(A_NORMAL);
1184
        }
1185
 
1186
        if (pos > 0) {
1187
                int     v;
1188
                v = strtoul(str, NULL, 16);
1189
                if (!tb->halted()) {
1190
                        switch(ra) {
1191
                        case 15:
1192
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1193
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1194
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1195
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1196
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1197
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1198
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1199
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1200
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1201
                                }
1202
                                break;
1203
                        case 31:
1204
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1205
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1206
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1207
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1208
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1209
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1210
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1211
                                        tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
1212
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1213
                                }
1214
                                break;
1215
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1216
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1217 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1218 34 dgisselq
                        case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
1219
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1220
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1221
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1222
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1223
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1224
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1225
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1226
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1227
                        default:
1228
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1229
                                break;
1230
                        }
1231
                } else
1232
                        tb->cmd_write(ra, v);
1233
        }
1234
}
1235
 
1236 27 dgisselq
void    usage(void) {
1237
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1238
        printf("\n");
1239
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1240
        printf("\t-a\tSets the testbench to run automatically without any\n");
1241
        printf("\t\tuser interaction.\n");
1242
        printf("\n");
1243
        printf("\tUser Commands:\n");
1244
        printf("\t\tWhen the test bench is run interactively, the following\n");
1245
        printf("\t\tkey strokes are recognized:\n");
1246
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1247
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1248
        printf("\t\t\tuser intervention.\n");
1249
        printf("\t\t\'q\'\tQuit the simulation.\n");
1250
        printf("\t\t\'r\'\tReset the processor.\n");
1251
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1252
        printf("\t\t\tThis may consume more than one tick.\n");
1253
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1254
}
1255 2 dgisselq
 
1256 43 dgisselq
bool    signalled = false;
1257
 
1258
void    sigint(int v) {
1259
        signalled = true;
1260
}
1261
 
1262 2 dgisselq
int     main(int argc, char **argv) {
1263
        Verilated::commandArgs(argc, argv);
1264
        ZIPPY_TB        *tb = new ZIPPY_TB();
1265 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1266 2 dgisselq
 
1267
        // mem[0x00000] = 0xbe000010; // Halt instruction
1268
        unsigned int mptr = 0;
1269
 
1270 43 dgisselq
        signal(SIGINT, sigint);
1271
 
1272 9 dgisselq
        if (argc <= 1) {
1273 27 dgisselq
                usage();
1274
                exit(-1);
1275 9 dgisselq
        } else {
1276
                for(int argn=1; argn<argc; argn++) {
1277 27 dgisselq
                        if (argv[argn][0] == '-') {
1278
                                switch(argv[argn][1]) {
1279
                                case 'a':
1280
                                        autorun = true;
1281
                                        break;
1282
                                case 'e':
1283
                                        exit_on_done = true;
1284
                                        break;
1285
                                case 'h':
1286
                                        usage();
1287
                                        exit(0);
1288
                                        break;
1289 36 dgisselq
                                case 's':
1290
                                        autostep = true;
1291
                                        break;
1292 27 dgisselq
                                default:
1293
                                        usage();
1294
                                        exit(-1);
1295
                                        break;
1296
                                }
1297
                        } else if (access(argv[argn], R_OK)==0) {
1298 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1299 58 dgisselq
                                int     nr, nv = 0;
1300 9 dgisselq
                                if (fp == NULL) {
1301
                                        printf("Cannot open %s\n", argv[argn]);
1302
                                        perror("O/S Err: ");
1303
                                        exit(-1);
1304 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1305 9 dgisselq
                                fclose(fp);
1306 58 dgisselq
                                mptr+= nr;
1307
                                if (nr == 0) {
1308
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
1309
                                        perror("O/S  Err?:");
1310
                                        exit(-2);
1311
                                } for(int i=0; i<nr; i++) {
1312
                                        if (tb->m_mem[mptr-nr+i])
1313
                                                nv++;
1314
                                } if (nv == 0) {
1315
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
1316
                                        perror("O/S  Err?:");
1317
                                        exit(-2);
1318
                                }
1319
                        } else {
1320
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1321
                                exit(-2);
1322 9 dgisselq
                        }
1323
                }
1324
        }
1325
 
1326 58 dgisselq
 
1327
        assert(mptr > 0);
1328
 
1329 27 dgisselq
        if (autorun) {
1330
                bool    done = false;
1331 2 dgisselq
 
1332 27 dgisselq
                printf("Running in non-interactive mode\n");
1333
                tb->reset();
1334
                for(int i=0; i<2; i++)
1335
                        tb->tick();
1336
                tb->m_core->v__DOT__cmd_halt = 0;
1337
                while(!done) {
1338
                        tb->tick();
1339
 
1340
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1341
                                // tb->m_core->v__DOT__cmd_halt = 0;
1342
                                // tb->m_core->v__DOT__cmd_step = 0;
1343
 
1344 34 dgisselq
                        /*
1345 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1346
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1347
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1348
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1349 34 dgisselq
                        */
1350 27 dgisselq
 
1351
                        done = (tb->test_success())||(tb->test_failure());
1352 43 dgisselq
                        done = done || signalled;
1353 27 dgisselq
                }
1354 36 dgisselq
        } else if (autostep) {
1355
                bool    done = false;
1356
 
1357
                printf("Running in non-interactive mode, via step commands\n");
1358
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1359
                while(!done) {
1360
                        tb->wb_write(CMD_REG, CMD_STEP);
1361
                        done = (tb->test_success())||(tb->test_failure());
1362 43 dgisselq
                        done = done || signalled;
1363 36 dgisselq
                }
1364 27 dgisselq
        } else { // Interactive
1365
                initscr();
1366
                raw();
1367
                noecho();
1368
                keypad(stdscr, true);
1369
 
1370
                tb->reset();
1371
                for(int i=0; i<2; i++)
1372
                        tb->tick();
1373
                tb->m_core->v__DOT__cmd_halt = 0;
1374
 
1375
                int     chv = 'q';
1376
 
1377 43 dgisselq
                bool    done = false, halted = true, manual = true,
1378
                        high_speed = false;
1379 2 dgisselq
 
1380
                halfdelay(1);
1381 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1382 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1383
                        // tb->show_state();
1384
 
1385
                while(!done) {
1386 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1387
                                struct  pollfd  fds[1];
1388
                                fds[0].fd = STDIN_FILENO;
1389
                                fds[0].events = POLLIN;
1390
                                if (poll(fds, 1, 0) > 0)
1391
                                        chv = getch();
1392
                                else
1393
                                        chv = ERR;
1394
                        } else {
1395
                                chv = getch();
1396
                        }
1397 2 dgisselq
                        switch(chv) {
1398
                        case 'h': case 'H':
1399
                                tb->wb_write(CMD_REG, CMD_HALT);
1400
                                if (!halted)
1401
                                        erase();
1402
                                halted = true;
1403
                                break;
1404 43 dgisselq
                        case 'G':
1405
                                high_speed = true;
1406
                        case 'g':
1407 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1408
                                if (halted)
1409
                                        erase();
1410
                                halted = false;
1411
                                manual = false;
1412
                                break;
1413 43 dgisselq
                        case 'm':
1414
                                tb->show_user_timers(false);
1415
                                break;
1416 2 dgisselq
                        case 'q': case 'Q':
1417
                                done = true;
1418
                                break;
1419
                        case 'r': case 'R':
1420 36 dgisselq
                                if (manual)
1421
                                        tb->reset();
1422
                                else
1423
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1424 2 dgisselq
                                halted = true;
1425
                                erase();
1426
                                break;
1427 39 dgisselq
                        case 's':
1428 34 dgisselq
                                if (!halted)
1429 27 dgisselq
                                        erase();
1430 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1431
                                manual = false;
1432 34 dgisselq
                                halted = true;
1433 43 dgisselq
                                high_speed = false;
1434 2 dgisselq
                                break;
1435 39 dgisselq
                        case 'S':
1436 34 dgisselq
                                if ((!manual)||(halted))
1437 27 dgisselq
                                        erase();
1438 2 dgisselq
                                manual = true;
1439 39 dgisselq
                                halted = true;
1440 43 dgisselq
                                high_speed = false;
1441 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1442
                                tb->m_core->v__DOT__cmd_step = 1;
1443
                                tb->eval();
1444
                                tb->tick();
1445
                                break;
1446
                        case 'T': // 
1447
                                if ((!manual)||(halted))
1448
                                        erase();
1449
                                manual = true;
1450
                                halted = true;
1451 43 dgisselq
                                high_speed = false;
1452 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1453
                                tb->m_core->v__DOT__cmd_step = 0;
1454
                                tb->eval();
1455
                                tb->tick();
1456
                                break;
1457
                        case 't':
1458
                                if ((!manual)||(halted))
1459
                                        erase();
1460
                                manual = true;
1461 34 dgisselq
                                halted = false;
1462 43 dgisselq
                                high_speed = false;
1463 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1464
                //              tb->m_core->v__DOT__cmd_halt = 0;
1465
                //              tb->m_core->v__DOT__cmd_step = 0;
1466 2 dgisselq
                                tb->tick();
1467
                                break;
1468 43 dgisselq
                        case 'u':
1469
                                tb->show_user_timers(true);
1470
                                break;
1471 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1472
                                get_value(tb);
1473
                                break;
1474
                        case    KEY_UP:         tb->cursor_up();        break;
1475
                        case    KEY_DOWN:       tb->cursor_down();      break;
1476
                        case    KEY_LEFT:       tb->cursor_left();      break;
1477
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1478 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1479 34 dgisselq
                        case ERR: case KEY_CLEAR:
1480 2 dgisselq
                        default:
1481
                                if (!manual)
1482
                                        tb->tick();
1483
                        }
1484
 
1485
                        if (manual) {
1486
                                tb->show_state();
1487
                        } else if (halted) {
1488
                                if (tb->dbg_fp)
1489
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1490
                                tb->read_state();
1491
                        } else
1492
                                tb->show_state();
1493
 
1494
                        if (tb->m_core->i_rst)
1495
                                done =true;
1496 43 dgisselq
                        if ((tb->bomb)||(signalled))
1497 2 dgisselq
                                done = true;
1498 27 dgisselq
 
1499
                        if (exit_on_done) {
1500
                                if (tb->test_success())
1501
                                        done = true;
1502
                                if (tb->test_failure())
1503
                                        done = true;
1504
                        }
1505 2 dgisselq
                }
1506 27 dgisselq
                endwin();
1507
        }
1508
#ifdef  MANUAL_STEPPING_MODE
1509
         else { // Manual stepping mode
1510 2 dgisselq
                tb->show_state();
1511
 
1512
                while('q' != tolower(chv = getch())) {
1513
                        tb->tick();
1514
                        tb->show_state();
1515
 
1516
                        if (tb->test_success())
1517
                                break;
1518
                        else if (tb->test_failure())
1519
                                break;
1520 43 dgisselq
                        else if (signalled)
1521
                                break;
1522 2 dgisselq
                }
1523
        }
1524 27 dgisselq
#endif
1525 2 dgisselq
 
1526 43 dgisselq
        printf("\n");
1527 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1528
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1529 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1530 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1531
                printf("Instructions / Clock: %.2f\n",
1532
                        (double)tb->m_core->v__DOT__mic_data
1533
                        / (double)tb->m_core->v__DOT__mtc_data);
1534 36 dgisselq
 
1535
        int     rcode = 0;
1536
        if (tb->bomb) {
1537
                printf("TEST BOMBED\n");
1538
                rcode = -1;
1539
        } else if (tb->test_success()) {
1540 2 dgisselq
                printf("SUCCESS!\n");
1541 36 dgisselq
        } else if (tb->test_failure()) {
1542
                rcode = -2;
1543 2 dgisselq
                printf("TEST FAILED!\n");
1544 36 dgisselq
        } else
1545 27 dgisselq
                printf("User quit\n");
1546 43 dgisselq
        delete tb;
1547 36 dgisselq
        exit(rcode);
1548 2 dgisselq
}
1549
 

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