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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Blame information for rev 69

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//              code to load into memory.  For now, we hand assemble with the
10
//              computers help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14 69 dgisselq
//              Gisselquist Technology, LLC
15 2 dgisselq
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39 9 dgisselq
#include <unistd.h>
40 43 dgisselq
#include <poll.h>
41 2 dgisselq
 
42
#include <ctype.h>
43
#include <ncurses.h>
44
 
45
#include "verilated.h"
46
#include "Vzipsystem.h"
47 39 dgisselq
#include "cpudefs.h"
48 2 dgisselq
 
49
#include "testb.h"
50
// #include "twoc.h"
51
// #include "qspiflashsim.h"
52
#include "memsim.h"
53
#include "zopcodes.h"
54
#include "zparser.h"
55
 
56
#define CMD_REG         0
57
#define CMD_DATA        1
58
#define CMD_HALT        (1<<10)
59
#define CMD_STALL       (1<<9)
60
#define CMD_INT         (1<<7)
61
#define CMD_RESET       (1<<6)
62 36 dgisselq
#define CMD_STEP        ((1<<8)|CMD_HALT)
63 2 dgisselq
 
64 34 dgisselq
#define KEY_ESCAPE      27
65
#define KEY_RETURN      10
66 36 dgisselq
#define CTRL(X)         ((X)&0x01f)
67 2 dgisselq
 
68 57 dgisselq
#define MAXERR          10000
69
 
70 2 dgisselq
// No particular "parameters" need definition or redefinition here.
71
class   ZIPPY_TB : public TESTB<Vzipsystem> {
72
public:
73 9 dgisselq
        unsigned long   m_mem_size;
74 2 dgisselq
        MEMSIM          m_mem;
75
        // QSPIFLASHSIM m_flash;
76 58 dgisselq
        FILE            *dbg_fp, *m_profile_fp;
77 43 dgisselq
        bool            dbg_flag, bomb, m_show_user_timers;
78 34 dgisselq
        int             m_cursor;
79 58 dgisselq
        unsigned long   m_last_instruction_tickcount;
80 2 dgisselq
 
81 9 dgisselq
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
82 69 dgisselq
                if (true) {
83 36 dgisselq
                        dbg_fp = fopen("dbg.txt", "w");
84
                        dbg_flag = true;
85
                } else {
86
                        dbg_fp = NULL;
87
                        dbg_flag = false;
88
                }
89 2 dgisselq
                bomb = false;
90 34 dgisselq
                m_cursor = 0;
91 43 dgisselq
                m_show_user_timers = false;
92 58 dgisselq
 
93
                m_last_instruction_tickcount = 0l;
94
                if (true) {
95
                        m_profile_fp = fopen("pfile.bin","wb");
96
                } else {
97
                        m_profile_fp = NULL;
98
                }
99 2 dgisselq
        }
100
 
101 69 dgisselq
        ~ZIPPY_TB(void) {
102
                if (dbg_fp)
103
                        fclose(dbg_fp);
104
                if (m_profile_fp)
105
                        fclose(m_profile_fp);
106
        }
107
 
108 2 dgisselq
        void    reset(void) {
109
                // m_flash.debug(false);
110
                TESTB<Vzipsystem>::reset();
111
        }
112
 
113
        bool    on_tick(void) {
114
                tick();
115
                return true;
116
        }
117
 
118 34 dgisselq
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
119
                if (c)
120
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
121
                else
122
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
123 2 dgisselq
        }
124
 
125 34 dgisselq
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
126 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
127 34 dgisselq
                if (c)
128
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
129
                else
130
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
131 2 dgisselq
        }
132
 
133 34 dgisselq
        void    showreg(int y, int x, const char *n, int r, bool c) {
134 2 dgisselq
                // 4,4,8,1 = 17 of 20, +3 = 19
135 34 dgisselq
                if (c)
136
                        mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
137
                else
138
                        mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
139 69 dgisselq
#ifdef  OPT_PIPELINED
140
                addch( ((r == (int)(dcdA()&0x01f))
141
                                &&(dcdvalid())
142 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
143 34 dgisselq
                        ?'a':((c)?'<':' '));
144 69 dgisselq
                addch( ((r == (int)(dcdB()&0x01f))
145
                                &&(dcdvalid())
146 2 dgisselq
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
147 34 dgisselq
                        ?'b':((c)?'<':' '));
148 69 dgisselq
#endif
149 2 dgisselq
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
150
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
151 34 dgisselq
                        ?'W':((c)?'<':' '));
152 2 dgisselq
        }
153
 
154
        void    showins(int y, const char *lbl, const int ce, const int valid,
155
                        const int gie, const int stall, const unsigned int pc) {
156
                char    line[80];
157
 
158
                if (ce)
159
                        mvprintw(y, 0, "Ck ");
160
                else
161
                        mvprintw(y, 0, "   ");
162
                if (stall)
163
                        printw("Stl ");
164
                else
165
                        printw("    ");
166
                printw("%s: 0x%08x", lbl, pc);
167
 
168
                if (valid) {
169
                        if (gie) attroff(A_BOLD);
170
                        else    attron(A_BOLD);
171
                        zipi_to_string(m_mem[pc], line);
172 27 dgisselq
                        printw("  %-24s", &line[1]);
173 2 dgisselq
                } else {
174
                        attroff(A_BOLD);
175
                        printw("  (0x%08x)%28s", m_mem[pc],"");
176
                }
177
                attroff(A_BOLD);
178
        }
179
 
180
        void    dbgins(const char *lbl, const int ce, const int valid,
181
                        const int gie, const int stall, const unsigned int pc) {
182
                char    line[80];
183
 
184
                if (!dbg_fp)
185
                        return;
186
 
187
                if (ce)
188
                        fprintf(dbg_fp, "%s Ck ", lbl);
189
                else
190
                        fprintf(dbg_fp, "%s    ", lbl);
191
                if (stall)
192
                        fprintf(dbg_fp, "Stl ");
193
                else
194
                        fprintf(dbg_fp, "    ");
195
                fprintf(dbg_fp, "0x%08x:  ", pc);
196
 
197
                if (valid) {
198
                        zipi_to_string(m_mem[pc], line);
199
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
200
                } else {
201
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
202
                }
203
        }
204
 
205
        void    show_state(void) {
206
                int     ln= 0;
207
 
208
                mvprintw(ln,0, "Peripherals-SS"); ln++;
209 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
210 36 dgisselq
                printw(" %s",
211
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
212
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
213
                        );
214 39 dgisselq
#endif
215
 
216
#ifdef  OPT_EARLY_BRANCHING
217 69 dgisselq
                printw(" %s",
218
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)?"EB":"  ");
219 39 dgisselq
#endif
220 36 dgisselq
 
221
                /*
222 2 dgisselq
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
223
                        mvprintw(ln, 17, "%s%s",
224
                                ((m_core->v__DOT__sys_cyc)
225
                                &&(m_core->v__DOT__sys_we)
226
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
227
                                (m_core->v__DOT__trap_int)?"I":" ");
228
                */
229 34 dgisselq
                showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
230
                showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
231 36 dgisselq
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
232 57 dgisselq
 
233
                if (!m_show_user_timers) {
234
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
235
                } else {
236
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
237
                }
238
 
239 69 dgisselq
                showval(ln,60, "PIC2", m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state, (m_cursor==3));
240 2 dgisselq
 
241
                ln++;
242 34 dgisselq
                showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
243
                showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
244 69 dgisselq
                showval(ln,40, "TMRC", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
245 34 dgisselq
                showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
246 2 dgisselq
 
247 43 dgisselq
 
248
                if (!m_show_user_timers) {
249
                        ln++;
250
                        showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
251
                        showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
252
                        showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
253
                        showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
254
                } else {
255
                        ln++;
256
                        showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
257
                        showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
258
                        showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
259
                        showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
260
                }
261 2 dgisselq
 
262
                ln++;
263
                mvprintw(ln, 40, "%s %s",
264
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
265
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
266 57 dgisselq
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
267 2 dgisselq
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
268
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
269
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
270 57 dgisselq
                        (m_core->v__DOT__cmd_addr)&0x3f,
271
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
272
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
273 2 dgisselq
                if (m_core->v__DOT__thecpu__DOT__gie)
274
                        attroff(A_BOLD);
275
                else
276
                        attron(A_BOLD);
277
                mvprintw(ln, 0, "Supervisor Registers");
278
                ln++;
279
 
280 34 dgisselq
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
281
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
282
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
283
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
284 2 dgisselq
 
285 34 dgisselq
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
286
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
287
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
288
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
289 2 dgisselq
 
290 34 dgisselq
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
291
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
292
                showreg(ln,40, "sR10", 10, (m_cursor==22));
293
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
294 2 dgisselq
 
295 34 dgisselq
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
296
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
297 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
298
                        (m_cursor==26)?">":" ",
299
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
300
                        (m_core->v__DOT__thecpu__DOT__break_en)?"BK":"  ",
301
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
302
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
303
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
304 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
305
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
306
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
307
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
308 34 dgisselq
                showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
309 69 dgisselq
                mvprintw(ln,60,"%s",
310
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
311
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
312
                                ?"V"
313
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
314
                                &&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
315
                        :" "));
316 2 dgisselq
                ln++;
317
 
318
                if (m_core->v__DOT__thecpu__DOT__gie)
319
                        attron(A_BOLD);
320
                else
321
                        attroff(A_BOLD);
322 69 dgisselq
                mvprintw(ln, 0, "User Registers");
323
                mvprintw(ln, 42, "DCDR=%02x %s%s",
324
                        dcdR(),
325
                        (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
326
                        (m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
327
                mvprintw(ln, 62, "OPR =%02x %s%s",
328
                        m_core->v__DOT__thecpu__DOT__opR,
329
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
330
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
331
                ln++;
332 34 dgisselq
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
333
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
334
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
335
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
336 2 dgisselq
 
337 34 dgisselq
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
338
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
339
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
340
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
341 2 dgisselq
 
342 34 dgisselq
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
343
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
344
                showreg(ln,40, "uR10", 26, (m_cursor==38));
345
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
346 2 dgisselq
 
347 34 dgisselq
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
348
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
349 69 dgisselq
                mvprintw(ln,40, "%cuCC :%s  %s%s%s%s%s%s%s",
350 43 dgisselq
                        (m_cursor == 42)?'>':' ',
351 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__trap)?"TP":"  ",
352
                        (m_core->v__DOT__thecpu__DOT__step)?"ST":"  ",
353
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SL":"  ",
354
                        (m_core->v__DOT__thecpu__DOT__gie)?"IE":"  ",
355 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
356
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
357
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
358
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
359 34 dgisselq
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
360 69 dgisselq
                mvprintw(ln,60,"%s",
361
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
362
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
363
                                ?"V"
364
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
365
                                &&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
366
                        :" "));
367 2 dgisselq
 
368
                attroff(A_BOLD);
369
                ln+=1;
370
 
371 39 dgisselq
#ifdef  OPT_SINGLE_FETCH
372 69 dgisselq
                ln++;
373
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
374
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
375
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
376
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
377
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
378
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
379
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
380
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
381
                        (m_core->v__DOT__wb_data)); ln++;
382 39 dgisselq
#else
383 69 dgisselq
 
384
                mvprintw(ln, 0, "PFCACH: v=%08x, %s, tag=%08x, pf_pc=%08x, lastpc=%08x",
385
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
386
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
387
                        m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
388
                        m_core->v__DOT__thecpu__DOT__pf_pc,
389
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
390
 
391 2 dgisselq
                ln++;
392
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
393
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
394
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
395
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
396
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
397
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
398
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
399 69 dgisselq
                        (pfstall())?"STL":"   ",
400 2 dgisselq
                        (m_core->v__DOT__wb_data)); ln++;
401 39 dgisselq
#endif
402 2 dgisselq
 
403
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
404 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
405
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
406
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
407
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
408 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
409
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
410
                        (m_core->v__DOT__thecpu__DOT__mem_data),
411
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
412 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
413 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_result));
414
// #define      OPT_PIPELINED_BUS_ACCESS
415
#ifdef  OPT_PIPELINED_BUS_ACCESS
416
                printw(" %x%x%c%c",
417
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
418
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
419
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
420
                        (mem_pipe_stalled())?'S':'-'); ln++;
421
#else
422
                ln++;
423
#endif
424 2 dgisselq
 
425 69 dgisselq
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
426 36 dgisselq
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
427 2 dgisselq
                        (m_core->o_wb_cyc)?"CYC":"   ",
428
                        (m_core->o_wb_stb)?"STB":"   ",
429
                        (m_core->o_wb_we )?"WE":"  ",
430
                        (m_core->o_wb_addr),
431
                        (m_core->o_wb_data),
432
                        (m_core->i_wb_ack)?"ACK":"   ",
433
                        (m_core->i_wb_stall)?"STL":"   ",
434 69 dgisselq
                        (m_core->i_wb_data),
435
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
436 39 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
437
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
438
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
439 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
440
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),     //0
441
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
442
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
443 58 dgisselq
                        (!mem_stalled()),       //1
444 2 dgisselq
 
445 58 dgisselq
                        (mem_stalled()),
446 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
447
                        (m_core->v__DOT__thecpu__DOT__master_ce),
448
                        (mem_pipe_stalled()),
449
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
450 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
451
                        );
452 39 dgisselq
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
453 69 dgisselq
                        (dcdvalid()),
454 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
455
                        (m_core->v__DOT__thecpu__DOT__dcdM),
456
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
457
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
458 69 dgisselq
                        ((int)(dcdB()&0x01f)
459 39 dgisselq
                                == m_core->v__DOT__thecpu__DOT__op_B),
460 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcdI
461 39 dgisselq
                                == m_core->v__DOT__thecpu__DOT__r_opI),
462 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcdI+1
463 39 dgisselq
                                == m_core->v__DOT__thecpu__DOT__r_opI));
464
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
465 69 dgisselq
                        (m_core->v__DOT__thecpu__DOT__dcdI),
466 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__r_opI));
467
#endif
468
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
469 57 dgisselq
#ifdef  OPT_SINGLE_CYCLE
470
                printw(" A:%c%c B:%c%c",
471 43 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
472
                        (m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
473 57 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
474
                        (m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
475 69 dgisselq
#else
476
                printw(" A:xx B:xx");
477 57 dgisselq
#endif
478 69 dgisselq
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
479 39 dgisselq
 
480
 
481 2 dgisselq
                showins(ln, "I ",
482 69 dgisselq
#ifdef  OPT_PIPELINED
483 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
484 69 dgisselq
#else
485
                        1,
486
#endif
487 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
488
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
489
                        m_core->v__DOT__thecpu__DOT__gie,
490
                        0,
491 36 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
492
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
493 2 dgisselq
 
494
                showins(ln, "Dc",
495 69 dgisselq
                        dcd_ce(), dcdvalid(),
496 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
497 69 dgisselq
#ifdef  OPT_PIPELINED
498 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
499 69 dgisselq
#else
500
                        0,
501
#endif
502 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
503 39 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
504
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
505
                        mvprintw(ln-1,10,"I");
506
                else
507
#endif
508
                if (m_core->v__DOT__thecpu__DOT__dcdM)
509
                        mvprintw(ln-1,10,"M");
510 2 dgisselq
 
511
                showins(ln, "Op",
512 69 dgisselq
                        op_ce(),
513 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
514
                        m_core->v__DOT__thecpu__DOT__op_gie,
515
                        m_core->v__DOT__thecpu__DOT__op_stall,
516 39 dgisselq
                        op_pc()); ln++;
517
#ifdef  OPT_ILLEGAL_INSTRUCTION
518
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
519
                        mvprintw(ln-1,10,"I");
520
                else
521
#endif
522
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
523
                        mvprintw(ln-1,10,"M");
524
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
525
                        mvprintw(ln-1,10,"A");
526 2 dgisselq
 
527
                showins(ln, "Al",
528
                        m_core->v__DOT__thecpu__DOT__alu_ce,
529
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
530
                        m_core->v__DOT__thecpu__DOT__alu_gie,
531 69 dgisselq
#ifdef  OPT_PIPELINED
532 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
533 69 dgisselq
#else
534
                        0,
535
#endif
536 39 dgisselq
                        alu_pc()); ln++;
537
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
538
                        mvprintw(ln-1,10,"W");
539 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
540
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
541
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
542
                        mvprintw(ln-1,10,"v");
543 58 dgisselq
#ifdef  OPT_ILLEGAL_INSTRUCTION
544 57 dgisselq
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
545
                        mvprintw(ln-1,10,"I");
546 58 dgisselq
#endif
547 57 dgisselq
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
548
                        // mvprintw(ln-1,10,"i");
549 2 dgisselq
 
550 39 dgisselq
                mvprintw(ln-5, 65,"%s %s",
551 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
552
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
553 2 dgisselq
                mvprintw(ln-4, 48,
554
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
555
                printw("(%s:%02x,%x)",
556
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
557
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
558
                        (m_core->v__DOT__thecpu__DOT__op_gie)
559
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
560
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
561
 
562
                printw("(%s%s%s:%02x)",
563
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
564
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
565
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
566
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
567
                /*
568
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
569
                        m_core->v__DOT__thecpu__DOT__dcdI);
570
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
571
                        m_core->v__DOT__thecpu__DOT__opB);
572
                */
573 27 dgisselq
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
574 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opn,
575 27 dgisselq
                        m_core->v__DOT__thecpu__DOT__r_opA,
576
                        m_core->v__DOT__thecpu__DOT__r_opB);
577
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
578
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
579
                else
580
                        printw("%8s","");
581 2 dgisselq
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
582 27 dgisselq
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
583 2 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
584
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
585 58 dgisselq
                        (mem_stalled())?"PIPE":"    ",
586 39 dgisselq
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
587 2 dgisselq
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
588
        }
589
 
590 43 dgisselq
        void    show_user_timers(bool v) {
591
                m_show_user_timers = v;
592
        }
593
 
594 2 dgisselq
        unsigned int    cmd_read(unsigned int a) {
595 57 dgisselq
                int     errcount = 0;
596 2 dgisselq
                if (dbg_fp) {
597
                        dbg_flag= true;
598
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
599
                }
600
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
601 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
602
                        errcount++;
603
                if (errcount >= MAXERR) {
604
                        endwin();
605
 
606
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
607
                        printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
608
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__cpu_dbg_stall);
609
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
610
                        printf("mem_cyc_gbl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
611
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
612
                        printf("opvalid        = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
613 69 dgisselq
                        printf("dcdvalid       = %d\n", dcdvalid()?1:0);
614
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
615
#ifdef  OPT_PIPELINED
616 57 dgisselq
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
617 69 dgisselq
#endif
618 57 dgisselq
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
619 69 dgisselq
#ifdef  OPT_EARLY_BRANCHING
620
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
621
#endif
622 57 dgisselq
 
623
                        exit(-2);
624
                }
625
 
626
                assert(errcount < MAXERR);
627 2 dgisselq
                unsigned int v = wb_read(CMD_DATA);
628
 
629
                if (dbg_flag)
630
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
631
                                v);
632
                dbg_flag = false;
633
                return v;
634
        }
635
 
636 34 dgisselq
        void    cmd_write(unsigned int a, int v) {
637 57 dgisselq
                int     errcount = 0;
638 34 dgisselq
                if ((a&0x0f)==0x0f)
639
                        dbg_flag = true;
640
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
641 57 dgisselq
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
642
                        errcount++;
643
                assert(errcount < MAXERR);
644 34 dgisselq
                if (dbg_flag)
645
                        fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
646
                wb_write(CMD_DATA, v);
647
        }
648
 
649 27 dgisselq
        bool    halted(void) {
650
                return (m_core->v__DOT__cmd_halt != 0);
651
        }
652
 
653 2 dgisselq
        void    read_state(void) {
654
                int     ln= 0;
655 34 dgisselq
                bool    gie;
656 2 dgisselq
 
657 34 dgisselq
                if (m_cursor < 0)
658
                        m_cursor = 0;
659
                else if (m_cursor >= 44)
660
                        m_cursor = 43;
661
 
662
                mvprintw(ln,0, "Peripherals-RS");
663
                mvprintw(ln,40,"%-40s", "CPU State: ");
664
                {
665
                        unsigned int v = wb_read(CMD_REG);
666
                        mvprintw(ln,51, "");
667
                        if (v & 0x010000)
668
                                printw("EXT-INT ");
669
                        if ((v & 0x003000) == 0x03000)
670
                                printw("Halted ");
671
                        else if (v & 0x001000)
672
                                printw("Sleeping ");
673
                        else if (v & 0x002000)
674
                                printw("Supervisor Mod ");
675
                        if (v & 0x008000)
676
                                printw("Break-Enabled ");
677
                        if (v & 0x000080)
678
                                printw("PIC Enabled ");
679
                } ln++;
680
                showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
681
                showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
682 57 dgisselq
                showval(ln,40, "WBUS", cmd_read(32+ 2), false);
683 34 dgisselq
                showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
684 2 dgisselq
                ln++;
685 34 dgisselq
                showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
686
                showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
687
                showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
688
                showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
689 2 dgisselq
 
690
                ln++;
691 43 dgisselq
                if (!m_show_user_timers) {
692
                        showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
693
                        showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
694
                        showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
695
                        showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
696
                } else {
697
                        showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
698
                        showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
699
                        showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
700
                        showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
701
                }
702 2 dgisselq
 
703
                ln++;
704
                ln++;
705
                unsigned int cc = cmd_read(14);
706
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
707
                        m_core->v__DOT__thecpu__DOT__gie);
708 34 dgisselq
                gie = (cc & 0x020);
709
                if (gie)
710 2 dgisselq
                        attroff(A_BOLD);
711
                else
712
                        attron(A_BOLD);
713
                mvprintw(ln, 0, "Supervisor Registers");
714
                ln++;
715
 
716 34 dgisselq
                dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
717
                dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
718
                dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
719
                dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
720 2 dgisselq
 
721 34 dgisselq
                dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
722
                dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
723
                dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
724
                dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
725 2 dgisselq
 
726 34 dgisselq
                dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
727
                dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
728
                dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
729
                dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
730 2 dgisselq
 
731 34 dgisselq
                dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
732
                dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
733 2 dgisselq
 
734 36 dgisselq
                mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
735 34 dgisselq
                        (m_cursor==26)?">":" ",
736 36 dgisselq
                        (cc & 0x200)?"TP":"  ",
737
                        (cc & 0x080)?"BK":"  ",
738 34 dgisselq
                        (cc & 0x040)?"ST":"  ",
739
                        (cc & 0x020)?"IE":"  ",
740
                        (cc & 0x010)?"SL":"  ",
741 2 dgisselq
                        (cc&8)?"V":" ",
742
                        (cc&4)?"N":" ",
743
                        (cc&2)?"C":" ",
744
                        (cc&1)?"Z":" ");
745 34 dgisselq
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
746 2 dgisselq
                ln++;
747
 
748 34 dgisselq
                if (gie)
749 2 dgisselq
                        attron(A_BOLD);
750
                else
751
                        attroff(A_BOLD);
752 69 dgisselq
                mvprintw(ln, 0, "User Registers");
753
                mvprintw(ln, 42, "DCDR=%02x %s",
754
                        dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
755
                mvprintw(ln, 62, "OPR =%02x %s%s",
756
                        m_core->v__DOT__thecpu__DOT__opR,
757
                        (m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
758
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
759
                ln++;
760 34 dgisselq
                dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
761
                dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
762
                dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
763
                dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
764 2 dgisselq
 
765 34 dgisselq
                dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
766
                dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
767
                dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
768
                dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
769 2 dgisselq
 
770 34 dgisselq
                dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
771
                dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
772
                dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
773
                dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
774 2 dgisselq
 
775 34 dgisselq
                dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
776
                dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
777 2 dgisselq
                cc = cmd_read(30);
778 34 dgisselq
                mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
779 36 dgisselq
                        (m_cursor == 42)?'>':' ',
780 34 dgisselq
                        (cc&0x100)?"TP":"  ",
781
                        (cc&0x040)?"ST":"  ",
782
                        (cc&0x020)?"IE":"  ",
783
                        (cc&0x010)?"SL":"  ",
784 2 dgisselq
                        (cc&8)?"V":" ",
785
                        (cc&4)?"N":" ",
786
                        (cc&2)?"C":" ",
787
                        (cc&1)?"Z":" ");
788 34 dgisselq
                dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
789 2 dgisselq
 
790
                attroff(A_BOLD);
791
                ln+=2;
792
 
793
                ln+=3;
794
 
795
                showins(ln, "I ",
796 69 dgisselq
#ifdef  OPT_PIPELINED
797 2 dgisselq
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
798 69 dgisselq
#else
799
                        1,
800
#endif
801 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__pf_valid,
802
                        m_core->v__DOT__thecpu__DOT__gie,
803
                        0,
804 57 dgisselq
                        m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
805
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
806 2 dgisselq
 
807
                showins(ln, "Dc",
808 69 dgisselq
                        dcd_ce(), dcdvalid(),
809 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
810 69 dgisselq
#ifdef  OPT_PIPELINED
811 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
812 69 dgisselq
#else
813
                        0,
814
#endif
815 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
816
 
817
                showins(ln, "Op",
818 69 dgisselq
                        op_ce(),
819 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__opvalid,
820
                        m_core->v__DOT__thecpu__DOT__op_gie,
821
                        m_core->v__DOT__thecpu__DOT__op_stall,
822 39 dgisselq
                        op_pc()); ln++;
823 2 dgisselq
 
824
                showins(ln, "Al",
825
                        m_core->v__DOT__thecpu__DOT__alu_ce,
826
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
827
                        m_core->v__DOT__thecpu__DOT__alu_gie,
828 69 dgisselq
#ifdef  OPT_PIPELINED
829 2 dgisselq
                        m_core->v__DOT__thecpu__DOT__alu_stall,
830 69 dgisselq
#else
831
                        0,
832
#endif
833 39 dgisselq
                        alu_pc()); ln++;
834 2 dgisselq
        }
835 69 dgisselq
 
836 2 dgisselq
        void    tick(void) {
837
                int gie = m_core->v__DOT__thecpu__DOT__gie;
838
                /*
839
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
840
                                                m_core->o_qspi_sck,
841
                                                m_core->o_qspi_dat);
842
                */
843
 
844 11 dgisselq
                int stb = m_core->o_wb_stb;
845
                if ((m_core->o_wb_addr & (-1<<20))!=1)
846
                        stb = 0;
847
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
848
                        m_core->i_wb_ack = 1;
849 2 dgisselq
 
850
                if ((dbg_flag)&&(dbg_fp)) {
851 36 dgisselq
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
852 2 dgisselq
                                (m_core->i_dbg_cyc)?"CYC":"   ",
853
                                (m_core->i_dbg_stb)?"STB":
854
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
855
                                ((m_core->i_dbg_we)?"WE":"  "),
856
                                (m_core->i_dbg_addr),0,
857
                                m_core->i_dbg_data,
858
                                (m_core->o_dbg_ack)?"ACK":"   ",
859
                                (m_core->o_dbg_stall)?"STALL":"     ",
860
                                (m_core->o_dbg_data),
861
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
862
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
863 69 dgisselq
                                (dcdvalid())?"DCDV ":"",
864 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
865
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
866 36 dgisselq
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":"  ",
867
                                (m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":"  ",
868 2 dgisselq
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
869
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
870
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
871
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
872
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
873
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
874
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
875
                                (m_core->v__DOT__sys_we)?"WE":"  ",
876
                                (m_core->v__DOT__sys_addr),
877
                                (m_core->v__DOT__dbg_addr),
878
                                (m_core->v__DOT__sys_data),
879
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
880
                                (m_core->v__DOT__wb_data));
881
                }
882
 
883
                if (dbg_fp)
884
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
885 69 dgisselq
                                dcd_ce(),
886 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
887 69 dgisselq
                                op_ce(),
888 39 dgisselq
                                op_pc(),
889 69 dgisselq
                                dcdA()&0x01f,
890 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opR,
891
                                m_core->v__DOT__cmd_halt,
892
                                m_core->v__DOT__cpu_halt,
893
                                m_core->v__DOT__thecpu__DOT__alu_ce,
894
                                m_core->v__DOT__thecpu__DOT__alu_valid,
895
                                m_core->v__DOT__thecpu__DOT__alu_wr,
896
                                m_core->v__DOT__thecpu__DOT__alu_reg,
897
                                m_core->v__DOT__thecpu__DOT__ipc,
898
                                m_core->v__DOT__thecpu__DOT__upc);
899
 
900
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
901
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
902 69 dgisselq
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
903 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
904
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
905
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
906
                                m_core->v__DOT__cmd_addr,
907
                                m_core->v__DOT__dbg_idata,
908
                                m_core->v__DOT__thecpu__DOT__master_ce,
909
                                m_core->v__DOT__thecpu__DOT__alu_wr,
910
                                m_core->v__DOT__thecpu__DOT__alu_valid,
911
                                m_core->v__DOT__thecpu__DOT__mem_valid);
912
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
913
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
914
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
915
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
916
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
917
                                m_core->v__DOT__cmd_addr,
918
                                m_core->v__DOT__dbg_idata,
919
                                m_core->v__DOT__thecpu__DOT__master_ce,
920
                                m_core->v__DOT__thecpu__DOT__alu_wr,
921
                                m_core->v__DOT__thecpu__DOT__alu_valid,
922
                                m_core->v__DOT__thecpu__DOT__mem_valid,
923
                                m_core->v__DOT__thecpu__DOT__w_iflags,
924
                                m_core->v__DOT__thecpu__DOT__w_uflags);
925 36 dgisselq
                        fprintf(dbg_fp, "\tbrk=%s %d,%d\n",
926
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
927 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__break_en,
928
                                m_core->v__DOT__thecpu__DOT__op_break);
929 36 dgisselq
                } else if ((dbg_fp)&&
930
                                ((m_core->v__DOT__thecpu__DOT__op_break)
931
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
932
                        fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
933
                        fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
934
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
935
                                m_core->v__DOT__thecpu__DOT__break_en,
936
                                m_core->v__DOT__thecpu__DOT__dcd_break,
937
                                m_core->v__DOT__thecpu__DOT__op_break);
938 2 dgisselq
                }
939
 
940 34 dgisselq
                if (dbg_fp) {
941
                        if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
942
                                fprintf(dbg_fp, "\tClear Pipeline\n");
943
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
944
                                fprintf(dbg_fp, "\tNew PC\n");
945
                }
946
 
947 36 dgisselq
                if (dbg_fp)
948
                        fprintf(dbg_fp, "-----------  TICK ----------\n");
949
                if (false) {
950
                        m_core->i_clk = 1;
951
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
952
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
953
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
954
                        eval();
955
                        m_core->i_clk = 0;
956
                        m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
957
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
958
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
959
                        eval();
960
                        m_tickcount++;
961
                } else {
962
                        m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
963
                                m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
964
                                m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
965 43 dgisselq
                        if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
966
                                &&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
967
                                m_core->i_wb_err = 1;
968
                        else
969
                                m_core->i_wb_err = 0;
970 36 dgisselq
                        TESTB<Vzipsystem>::tick();
971
                }
972 2 dgisselq
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
973
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
974
                                (gie)?"User":"Supervisor",
975
                                (gie)?"Supervisor":"User",
976
                                m_core->v__DOT__thecpu__DOT__ipc,
977
                                m_core->v__DOT__thecpu__DOT__upc,
978
                                m_core->v__DOT__thecpu__DOT__pf_pc);
979
                } if (dbg_fp) {
980 69 dgisselq
#ifdef  NEW_PREFETCH_VERSION
981
                        fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s\n",
982
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
983
                                m_core->v__DOT__thecpu__DOT__pf_pc,
984
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
985
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)
986
                                &&(dcdvalid())
987
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
988
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
989
                                m_core->v__DOT__thecpu__DOT__instruction_pc,
990
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
991
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ");
992
#endif
993
                        dbgins("Dc - ",
994
                                dcd_ce(), dcdvalid(),
995 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
996 69 dgisselq
#ifdef  OPT_PIPELINED
997 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
998 69 dgisselq
#else
999
                                0,
1000
#endif
1001 57 dgisselq
                                m_core->v__DOT__thecpu__DOT__dcd_pc-1);
1002 69 dgisselq
                        dbgins("Op - ",
1003
                                op_ce(),
1004 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__opvalid,
1005
                                m_core->v__DOT__thecpu__DOT__op_gie,
1006
                                m_core->v__DOT__thecpu__DOT__op_stall,
1007 39 dgisselq
                                op_pc());
1008 57 dgisselq
/*
1009
#ifdef  OPT_SINGLE_CYCLE
1010
                        fprintf(dbg_fp, "\t\t  A = %08x,   B = %08x, I = %08x, B+I = %08x, %c%c %s%s%s[%2x] = %08x %s\n",
1011
                                m_core->v__DOT__thecpu__DOT__r_opA,
1012
                                m_core->v__DOT__thecpu__DOT__r_opB,
1013
                                m_core->v__DOT__thecpu__DOT__w_opBnI,
1014
                                m_core->v__DOT__thecpu__DOT__r_dcdI,
1015
                                (m_core->v__DOT__thecpu__DOT__opvalid_alu)?'A':'-',
1016
                                (m_core->v__DOT__thecpu__DOT__opvalid_mem)?'M':'-',
1017
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"W":" ",
1018
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"A":"M",
1019
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"k":"-",
1020
                                (m_core->v__DOT__thecpu__DOT__wr_reg_id),
1021
                                (m_core->v__DOT__thecpu__DOT__wr_reg_vl),
1022
                                (m_core->v__DOT__thecpu__DOT__mem_rdbusy)?"Mem-RdBusy":
1023
                                ((m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)?"Mem-Busy":""));
1024
                        fprintf(dbg_fp, "\t\topA = %08x, opB = %08x, alu_result = %08x\n",
1025
                                m_core->v__DOT__thecpu__DOT__opA,
1026
                                m_core->v__DOT__thecpu__DOT__opB,
1027
                                m_core->v__DOT__thecpu__DOT__alu_result);
1028
#endif
1029
*/
1030 2 dgisselq
                        dbgins("Al - ",
1031
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1032
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1033
                                m_core->v__DOT__thecpu__DOT__alu_gie,
1034 69 dgisselq
#ifdef  OPT_PIPELINED
1035 2 dgisselq
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1036 69 dgisselq
#else
1037
                                0,
1038
#endif
1039 39 dgisselq
                                alu_pc());
1040 2 dgisselq
 
1041
                }
1042 58 dgisselq
 
1043
                if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1044
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)) {
1045
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1046
                        if (m_profile_fp) {
1047
                                unsigned buf[2];
1048
                                buf[0] = m_core->v__DOT__thecpu__DOT__alu_pc-1;
1049
                                buf[1] = iticks;
1050
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1051
                        }
1052
                        m_last_instruction_tickcount = m_tickcount;
1053
                }
1054 2 dgisselq
        }
1055
 
1056
        bool    test_success(void) {
1057
                return ((!m_core->v__DOT__thecpu__DOT__gie)
1058
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1059
        }
1060
 
1061 39 dgisselq
        unsigned        op_pc(void) {
1062
                /*
1063
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
1064
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
1065
                        r--;
1066
                return r;
1067
                */
1068
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
1069
        }
1070
 
1071 69 dgisselq
        bool    dcd_ce(void) {
1072
#ifdef  OPT_PIPELINED
1073
                return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
1074
#else
1075
                return (m_core->v__DOT__thecpu__DOT__pf_valid);
1076
#endif
1077
        } bool  dcdvalid(void) {
1078
                return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
1079
        }
1080
        bool    pfstall(void) {
1081
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1082
                        ||(m_core->v__DOT__cpu_stall));
1083
        }
1084
        unsigned        dcdR(void) {
1085
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1086
        }
1087
        unsigned        dcdA(void) {
1088
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1089
        }
1090
        unsigned        dcdB(void) {
1091
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1092
        }
1093
 
1094
        bool    op_ce(void) {
1095
#ifdef  OPT_PIPELINED
1096
                return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
1097
#else
1098
                // return (dcdvalid())&&(opvalid())
1099
                //      &&(m_core->v__DOT__thecpu__DOT__op_stall);
1100
                return  dcdvalid();
1101
#endif
1102
        } bool  opvalid(void) {
1103
                return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
1104
        }
1105
 
1106 58 dgisselq
        bool    mem_busy(void) {
1107
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1108 69 dgisselq
#ifdef  OPT_PIPELINED
1109 58 dgisselq
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1110 69 dgisselq
#else
1111
                return 0;
1112
#endif
1113 58 dgisselq
        }
1114
 
1115
        bool    mem_stalled(void) {
1116
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1117
 
1118
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1119
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1120
                op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
1121
 
1122 69 dgisselq
#ifdef  OPT_PIPELINED_BUS_ACCESS
1123
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1124
                a = mem_pipe_stalled();
1125
                b = (!m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
1126
#else
1127
                a = false;
1128
                b = false;
1129
#endif
1130 58 dgisselq
                d = ((wr_write_pc)||(wr_write_cc));
1131
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1132 69 dgisselq
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1133 58 dgisselq
                        &&d);
1134
                d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
1135
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1136
        }
1137
 
1138 39 dgisselq
        unsigned        alu_pc(void) {
1139
                /*
1140
                unsigned        r = op_pc();
1141
                if (m_core->v__DOT__thecpu__DOT__opvalid)
1142
                        r--;
1143
                return r;
1144
                */
1145
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
1146
        }
1147
 
1148
#ifdef  OPT_PIPELINED_BUS_ACCESS
1149 69 dgisselq
        bool    mem_pipe_stalled(void) {
1150 39 dgisselq
                int     r = 0;
1151
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
1152
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
1153
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1154
                        ||(
1155
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1156
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1157
                return r;
1158
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1159
        }
1160
#endif
1161
 
1162 2 dgisselq
        bool    test_failure(void) {
1163 43 dgisselq
                if (m_core->v__DOT__thecpu__DOT__sleep)
1164
                        return 0;
1165
                else if (m_core->v__DOT__thecpu__DOT__gie)
1166
                        return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
1167
                else
1168
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
1169
                /*
1170 2 dgisselq
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1171 39 dgisselq
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1172 36 dgisselq
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1173 43 dgisselq
                */
1174 2 dgisselq
        }
1175
 
1176
        void    wb_write(unsigned a, unsigned int v) {
1177 36 dgisselq
                int     errcount = 0;
1178 2 dgisselq
                mvprintw(0,35, "%40s", "");
1179
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1180
                m_core->i_dbg_cyc = 1;
1181
                m_core->i_dbg_stb = 1;
1182
                m_core->i_dbg_we  = 1;
1183
                m_core->i_dbg_addr = a & 1;
1184
                m_core->i_dbg_data = v;
1185
 
1186
                tick();
1187 36 dgisselq
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1188 2 dgisselq
                        tick();
1189
 
1190
                m_core->i_dbg_stb = 0;
1191 36 dgisselq
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1192 2 dgisselq
                        tick();
1193
 
1194
                // Release the bus
1195
                m_core->i_dbg_cyc = 0;
1196
                m_core->i_dbg_stb = 0;
1197
                tick();
1198
                mvprintw(0,35, "%40s", "");
1199
                mvprintw(0,40, "wb_write -- complete");
1200 36 dgisselq
 
1201
 
1202
                if (errcount >= 100)
1203
                        bomb = true;
1204 2 dgisselq
        }
1205
 
1206
        unsigned long   wb_read(unsigned a) {
1207
                unsigned int    v;
1208 36 dgisselq
                int     errcount = 0;
1209 2 dgisselq
                mvprintw(0,35, "%40s", "");
1210
                mvprintw(0,40, "wb_read(0x%08x)", a);
1211
                m_core->i_dbg_cyc = 1;
1212
                m_core->i_dbg_stb = 1;
1213
                m_core->i_dbg_we  = 0;
1214
                m_core->i_dbg_addr = a & 1;
1215
 
1216
                tick();
1217 36 dgisselq
                while((errcount++<100)&&(m_core->o_dbg_stall))
1218 2 dgisselq
                        tick();
1219
 
1220
                m_core->i_dbg_stb = 0;
1221 36 dgisselq
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1222 2 dgisselq
                        tick();
1223
                v = m_core->o_dbg_data;
1224
 
1225
                // Release the bus
1226
                m_core->i_dbg_cyc = 0;
1227
                m_core->i_dbg_stb = 0;
1228
                tick();
1229
 
1230
                mvprintw(0,35, "%40s", "");
1231
                mvprintw(0,40, "wb_read = 0x%08x", v);
1232
 
1233 36 dgisselq
                if (errcount >= 100)
1234
                        bomb = true;
1235 2 dgisselq
                return v;
1236
        }
1237
 
1238 34 dgisselq
        void    cursor_up(void) {
1239
                if (m_cursor > 3)
1240
                        m_cursor -= 4;
1241
        } void  cursor_down(void) {
1242
                if (m_cursor < 40)
1243
                        m_cursor += 4;
1244
        } void  cursor_left(void) {
1245
                if (m_cursor > 0)
1246
                        m_cursor--;
1247
                else    m_cursor = 43;
1248
        } void  cursor_right(void) {
1249
                if (m_cursor < 43)
1250
                        m_cursor++;
1251
                else    m_cursor = 0;
1252
        }
1253
 
1254
        int     cursor(void) { return m_cursor; }
1255 2 dgisselq
};
1256
 
1257 34 dgisselq
void    get_value(ZIPPY_TB *tb) {
1258
        int     wy, wx, ra;
1259
        int     c = tb->cursor();
1260
 
1261
        wx = (c & 0x03) * 20 + 9;
1262
        wy = (c>>2);
1263
        if (wy >= 3+4)
1264
                wy++;
1265
        if (wy > 3)
1266
                wy += 2;
1267
        wy++;
1268
 
1269
        if (c >= 12)
1270
                ra = c - 12;
1271
        else
1272
                ra = c + 32;
1273
 
1274
        bool    done = false;
1275
        char    str[16];
1276
        int     pos = 0; str[pos] = '\0';
1277
        while(!done) {
1278
                int     chv = getch();
1279
                switch(chv) {
1280
                case KEY_ESCAPE:
1281
                        pos = 0; str[pos] = '\0'; done = true;
1282
                        break;
1283
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1284
                        done = true;
1285
                        break;
1286
                case KEY_LEFT: case KEY_BACKSPACE:
1287
                        if (pos > 0) pos--;
1288
                        break;
1289 36 dgisselq
                case CTRL('L'): redrawwin(stdscr); break;
1290 34 dgisselq
                case KEY_CLEAR:
1291
                        pos = 0;
1292
                        break;
1293
                case '0': case ' ': str[pos++] = '0'; break;
1294
                case '1': str[pos++] = '1'; break;
1295
                case '2': str[pos++] = '2'; break;
1296
                case '3': str[pos++] = '3'; break;
1297
                case '4': str[pos++] = '4'; break;
1298
                case '5': str[pos++] = '5'; break;
1299
                case '6': str[pos++] = '6'; break;
1300
                case '7': str[pos++] = '7'; break;
1301
                case '8': str[pos++] = '8'; break;
1302
                case '9': str[pos++] = '9'; break;
1303
                case 'A': case 'a': str[pos++] = 'A'; break;
1304
                case 'B': case 'b': str[pos++] = 'B'; break;
1305
                case 'C': case 'c': str[pos++] = 'C'; break;
1306
                case 'D': case 'd': str[pos++] = 'D'; break;
1307
                case 'E': case 'e': str[pos++] = 'E'; break;
1308
                case 'F': case 'f': str[pos++] = 'F'; break;
1309
                }
1310
 
1311
                if (pos > 8)
1312
                        pos = 8;
1313
                str[pos] = '\0';
1314
 
1315
                attron(A_NORMAL | A_UNDERLINE);
1316
                mvprintw(wy, wx, "%-8s", str);
1317
                if (pos > 0) {
1318
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1319
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1320
                }
1321
                attrset(A_NORMAL);
1322
        }
1323
 
1324
        if (pos > 0) {
1325
                int     v;
1326
                v = strtoul(str, NULL, 16);
1327
                if (!tb->halted()) {
1328
                        switch(ra) {
1329
                        case 15:
1330
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1331
                                if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
1332
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1333
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1334
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1335
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1336 69 dgisselq
#ifdef  OPT_PIPELINED
1337 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1338 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1339
#endif
1340 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1341
                                }
1342
                                break;
1343
                        case 31:
1344
                                tb->m_core->v__DOT__thecpu__DOT__upc = v;
1345
                                if (tb->m_core->v__DOT__thecpu__DOT__gie) {
1346
                                        tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
1347
                                        tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
1348
                                        tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1349
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1350 69 dgisselq
#ifdef  OPT_PIPELINED
1351 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1352 69 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
1353
#endif
1354 34 dgisselq
                                        tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
1355
                                }
1356
                                break;
1357
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1358
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1359 36 dgisselq
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1360 69 dgisselq
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1361 34 dgisselq
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1362
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1363
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1364
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1365
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1366
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1367
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1368
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1369
                        default:
1370
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1371
                                break;
1372
                        }
1373
                } else
1374
                        tb->cmd_write(ra, v);
1375
        }
1376
}
1377
 
1378 27 dgisselq
void    usage(void) {
1379
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1380
        printf("\n");
1381
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1382
        printf("\t-a\tSets the testbench to run automatically without any\n");
1383
        printf("\t\tuser interaction.\n");
1384
        printf("\n");
1385
        printf("\tUser Commands:\n");
1386
        printf("\t\tWhen the test bench is run interactively, the following\n");
1387
        printf("\t\tkey strokes are recognized:\n");
1388
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1389
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1390
        printf("\t\t\tuser intervention.\n");
1391
        printf("\t\t\'q\'\tQuit the simulation.\n");
1392
        printf("\t\t\'r\'\tReset the processor.\n");
1393
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1394
        printf("\t\t\tThis may consume more than one tick.\n");
1395
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1396
}
1397 2 dgisselq
 
1398 43 dgisselq
bool    signalled = false;
1399
 
1400
void    sigint(int v) {
1401
        signalled = true;
1402
}
1403
 
1404 2 dgisselq
int     main(int argc, char **argv) {
1405
        Verilated::commandArgs(argc, argv);
1406
        ZIPPY_TB        *tb = new ZIPPY_TB();
1407 36 dgisselq
        bool            autorun = false, exit_on_done = false, autostep=false;
1408 2 dgisselq
 
1409
        // mem[0x00000] = 0xbe000010; // Halt instruction
1410
        unsigned int mptr = 0;
1411
 
1412 43 dgisselq
        signal(SIGINT, sigint);
1413
 
1414 9 dgisselq
        if (argc <= 1) {
1415 27 dgisselq
                usage();
1416
                exit(-1);
1417 9 dgisselq
        } else {
1418
                for(int argn=1; argn<argc; argn++) {
1419 27 dgisselq
                        if (argv[argn][0] == '-') {
1420
                                switch(argv[argn][1]) {
1421
                                case 'a':
1422
                                        autorun = true;
1423
                                        break;
1424
                                case 'e':
1425
                                        exit_on_done = true;
1426
                                        break;
1427
                                case 'h':
1428
                                        usage();
1429
                                        exit(0);
1430
                                        break;
1431 36 dgisselq
                                case 's':
1432
                                        autostep = true;
1433
                                        break;
1434 27 dgisselq
                                default:
1435
                                        usage();
1436
                                        exit(-1);
1437
                                        break;
1438
                                }
1439
                        } else if (access(argv[argn], R_OK)==0) {
1440 9 dgisselq
                                FILE *fp = fopen(argv[argn], "r");
1441 58 dgisselq
                                int     nr, nv = 0;
1442 9 dgisselq
                                if (fp == NULL) {
1443
                                        printf("Cannot open %s\n", argv[argn]);
1444
                                        perror("O/S Err: ");
1445
                                        exit(-1);
1446 58 dgisselq
                                } nr = fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
1447 9 dgisselq
                                fclose(fp);
1448 58 dgisselq
                                mptr+= nr;
1449
                                if (nr == 0) {
1450
                                        printf("Could not read from %s, only read 0 words\n", argv[argn]);
1451
                                        perror("O/S  Err?:");
1452
                                        exit(-2);
1453
                                } for(int i=0; i<nr; i++) {
1454
                                        if (tb->m_mem[mptr-nr+i])
1455
                                                nv++;
1456
                                } if (nv == 0) {
1457
                                        printf("Read nothing but zeros from %s\n", argv[argn]);
1458
                                        perror("O/S  Err?:");
1459
                                        exit(-2);
1460
                                }
1461
                        } else {
1462
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1463
                                exit(-2);
1464 9 dgisselq
                        }
1465
                }
1466
        }
1467
 
1468 58 dgisselq
 
1469
        assert(mptr > 0);
1470
 
1471 27 dgisselq
        if (autorun) {
1472
                bool    done = false;
1473 2 dgisselq
 
1474 27 dgisselq
                printf("Running in non-interactive mode\n");
1475
                tb->reset();
1476
                for(int i=0; i<2; i++)
1477
                        tb->tick();
1478
                tb->m_core->v__DOT__cmd_halt = 0;
1479
                while(!done) {
1480
                        tb->tick();
1481
 
1482
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1483
                                // tb->m_core->v__DOT__cmd_halt = 0;
1484
                                // tb->m_core->v__DOT__cmd_step = 0;
1485
 
1486 34 dgisselq
                        /*
1487 27 dgisselq
                        printf("PC = %08x:%08x (%08x)\n",
1488
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1489
                                tb->m_core->v__DOT__thecpu__DOT__upc,
1490
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1491 34 dgisselq
                        */
1492 27 dgisselq
 
1493
                        done = (tb->test_success())||(tb->test_failure());
1494 43 dgisselq
                        done = done || signalled;
1495 27 dgisselq
                }
1496 36 dgisselq
        } else if (autostep) {
1497
                bool    done = false;
1498
 
1499
                printf("Running in non-interactive mode, via step commands\n");
1500
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET);
1501
                while(!done) {
1502
                        tb->wb_write(CMD_REG, CMD_STEP);
1503
                        done = (tb->test_success())||(tb->test_failure());
1504 43 dgisselq
                        done = done || signalled;
1505 36 dgisselq
                }
1506 27 dgisselq
        } else { // Interactive
1507
                initscr();
1508
                raw();
1509
                noecho();
1510
                keypad(stdscr, true);
1511
 
1512 69 dgisselq
                // tb->reset();
1513
                // for(int i=0; i<2; i++)
1514
                        // tb->tick();
1515
                tb->m_core->v__DOT__cmd_reset = 1;
1516 27 dgisselq
                tb->m_core->v__DOT__cmd_halt = 0;
1517
 
1518
                int     chv = 'q';
1519
 
1520 43 dgisselq
                bool    done = false, halted = true, manual = true,
1521
                        high_speed = false;
1522 2 dgisselq
 
1523
                halfdelay(1);
1524 27 dgisselq
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1525 2 dgisselq
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1526
                        // tb->show_state();
1527
 
1528
                while(!done) {
1529 43 dgisselq
                        if ((high_speed)&&(!manual)&&(!halted)) {
1530
                                struct  pollfd  fds[1];
1531
                                fds[0].fd = STDIN_FILENO;
1532
                                fds[0].events = POLLIN;
1533
                                if (poll(fds, 1, 0) > 0)
1534
                                        chv = getch();
1535
                                else
1536
                                        chv = ERR;
1537
                        } else {
1538
                                chv = getch();
1539
                        }
1540 2 dgisselq
                        switch(chv) {
1541
                        case 'h': case 'H':
1542
                                tb->wb_write(CMD_REG, CMD_HALT);
1543
                                if (!halted)
1544
                                        erase();
1545
                                halted = true;
1546
                                break;
1547 43 dgisselq
                        case 'G':
1548
                                high_speed = true;
1549
                        case 'g':
1550 2 dgisselq
                                tb->wb_write(CMD_REG, 0);
1551
                                if (halted)
1552
                                        erase();
1553
                                halted = false;
1554
                                manual = false;
1555
                                break;
1556 43 dgisselq
                        case 'm':
1557
                                tb->show_user_timers(false);
1558
                                break;
1559 2 dgisselq
                        case 'q': case 'Q':
1560
                                done = true;
1561
                                break;
1562
                        case 'r': case 'R':
1563 36 dgisselq
                                if (manual)
1564
                                        tb->reset();
1565
                                else
1566
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1567 2 dgisselq
                                halted = true;
1568
                                erase();
1569
                                break;
1570 39 dgisselq
                        case 's':
1571 34 dgisselq
                                if (!halted)
1572 27 dgisselq
                                        erase();
1573 2 dgisselq
                                tb->wb_write(CMD_REG, CMD_STEP);
1574
                                manual = false;
1575 34 dgisselq
                                halted = true;
1576 43 dgisselq
                                high_speed = false;
1577 2 dgisselq
                                break;
1578 39 dgisselq
                        case 'S':
1579 34 dgisselq
                                if ((!manual)||(halted))
1580 27 dgisselq
                                        erase();
1581 2 dgisselq
                                manual = true;
1582 39 dgisselq
                                halted = true;
1583 43 dgisselq
                                high_speed = false;
1584 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 0;
1585
                                tb->m_core->v__DOT__cmd_step = 1;
1586
                                tb->eval();
1587
                                tb->tick();
1588
                                break;
1589
                        case 'T': // 
1590
                                if ((!manual)||(halted))
1591
                                        erase();
1592
                                manual = true;
1593
                                halted = true;
1594 43 dgisselq
                                high_speed = false;
1595 39 dgisselq
                                tb->m_core->v__DOT__cmd_halt = 1;
1596
                                tb->m_core->v__DOT__cmd_step = 0;
1597
                                tb->eval();
1598
                                tb->tick();
1599
                                break;
1600
                        case 't':
1601
                                if ((!manual)||(halted))
1602
                                        erase();
1603
                                manual = true;
1604 34 dgisselq
                                halted = false;
1605 43 dgisselq
                                high_speed = false;
1606 27 dgisselq
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
1607
                //              tb->m_core->v__DOT__cmd_halt = 0;
1608
                //              tb->m_core->v__DOT__cmd_step = 0;
1609 2 dgisselq
                                tb->tick();
1610
                                break;
1611 43 dgisselq
                        case 'u':
1612
                                tb->show_user_timers(true);
1613
                                break;
1614 34 dgisselq
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
1615
                                get_value(tb);
1616
                                break;
1617
                        case    KEY_UP:         tb->cursor_up();        break;
1618
                        case    KEY_DOWN:       tb->cursor_down();      break;
1619
                        case    KEY_LEFT:       tb->cursor_left();      break;
1620
                        case    KEY_RIGHT:      tb->cursor_right();     break;
1621 36 dgisselq
                        case CTRL('L'): redrawwin(stdscr); break;
1622 34 dgisselq
                        case ERR: case KEY_CLEAR:
1623 2 dgisselq
                        default:
1624
                                if (!manual)
1625
                                        tb->tick();
1626
                        }
1627
 
1628
                        if (manual) {
1629
                                tb->show_state();
1630
                        } else if (halted) {
1631
                                if (tb->dbg_fp)
1632
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
1633
                                tb->read_state();
1634
                        } else
1635
                                tb->show_state();
1636
 
1637
                        if (tb->m_core->i_rst)
1638
                                done =true;
1639 43 dgisselq
                        if ((tb->bomb)||(signalled))
1640 2 dgisselq
                                done = true;
1641 27 dgisselq
 
1642
                        if (exit_on_done) {
1643
                                if (tb->test_success())
1644
                                        done = true;
1645
                                if (tb->test_failure())
1646
                                        done = true;
1647
                        }
1648 2 dgisselq
                }
1649 27 dgisselq
                endwin();
1650
        }
1651
#ifdef  MANUAL_STEPPING_MODE
1652
         else { // Manual stepping mode
1653 2 dgisselq
                tb->show_state();
1654
 
1655
                while('q' != tolower(chv = getch())) {
1656
                        tb->tick();
1657
                        tb->show_state();
1658
 
1659
                        if (tb->test_success())
1660
                                break;
1661
                        else if (tb->test_failure())
1662
                                break;
1663 43 dgisselq
                        else if (signalled)
1664
                                break;
1665 2 dgisselq
                }
1666
        }
1667 27 dgisselq
#endif
1668 2 dgisselq
 
1669 43 dgisselq
        printf("\n");
1670 27 dgisselq
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
1671
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
1672 43 dgisselq
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
1673 27 dgisselq
        if (tb->m_core->v__DOT__mtc_data != 0)
1674
                printf("Instructions / Clock: %.2f\n",
1675
                        (double)tb->m_core->v__DOT__mic_data
1676
                        / (double)tb->m_core->v__DOT__mtc_data);
1677 36 dgisselq
 
1678
        int     rcode = 0;
1679
        if (tb->bomb) {
1680
                printf("TEST BOMBED\n");
1681
                rcode = -1;
1682
        } else if (tb->test_success()) {
1683 2 dgisselq
                printf("SUCCESS!\n");
1684 36 dgisselq
        } else if (tb->test_failure()) {
1685
                rcode = -2;
1686 2 dgisselq
                printf("TEST FAILED!\n");
1687 36 dgisselq
        } else
1688 27 dgisselq
                printf("User quit\n");
1689 43 dgisselq
        delete tb;
1690 36 dgisselq
        exit(rcode);
1691 2 dgisselq
}
1692
 

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