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[/] [zipcpu/] [trunk/] [bench/] [formal/] [mcve.v] - Blame information for rev 209

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1 209 dgisselq
module  mcve(i_clk, o_val);
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        input   wire    i_clk;
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        output  reg     o_val;
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        parameter [0:0]   THE_TEST = 1'b0;
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        generate if (THE_TEST)
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        begin
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                always @(*)
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                        o_val = 1'b1;
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                always @(*)
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                        assert(o_val);
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        end else begin
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                always @(*)
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                        o_val = 1'b0;
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        end endgenerate
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endmodule

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