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[/] [zipcpu/] [trunk/] [bench/] [rtl/] [zipmmu_tb.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipmmu_tb.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is a test-bench wrapper for the MMU.  It's used to
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//              test whether or not the MMU works independent of the ZipCPU
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//      itself.  The rest of the test bench is a C++ Verilator-enabled program.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module zipmmu_tb(i_clk, i_reset, i_ctrl_cyc_stb, i_wbm_cyc, i_wbm_stb, i_wb_we,
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                                i_exe, i_wb_addr, i_wb_data, i_wb_sel, i_gie,
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                        o_rtn_stall, o_rtn_ack, o_rtn_err,
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                                o_rtn_miss, o_rtn_data);
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        parameter       CPU_ADDRESS_WIDTH=30,
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                        MEMORY_ADDRESS_WIDTH=15;
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        localparam      AW= CPU_ADDRESS_WIDTH,
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                        MAW= MEMORY_ADDRESS_WIDTH,
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                        LGTBL = 6,
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                        LGPGSZB=12;
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        input                   i_clk, i_reset;
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        //
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        input                   i_ctrl_cyc_stb;
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        //
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        input                   i_wbm_cyc, i_wbm_stb;
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        //
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        input                   i_exe;
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        input                   i_wb_we;
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        input   [(32-3):0]       i_wb_addr;
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        input   [(32-1):0]       i_wb_data;
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        input   [(32/8-1):0]     i_wb_sel;
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        input                   i_gie;
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        //
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        // Here's where we return information on either our slave/control bus
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        // or the memory bus we are controlled from.  Note that we share these
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        // wires ...
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        output  wire            o_rtn_stall, o_rtn_ack, o_rtn_err, o_rtn_miss;
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        output  wire    [(32-1):0]       o_rtn_data;
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        wire                    mem_cyc /* verilator public_flat */,
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                                mem_stb /* verilator public_flat */,
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                                mem_we  /* verilator public_flat */,
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                                mem_ack /* verilator public_flat */,
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                                mem_stall       /* verilator public_flat */;
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        wire    [31:0]           mem_idata       /* verilator public_flat */,
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                                mem_odata       /* verilator public_flat */;
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        wire    [(32/8-1):0]     mem_sel;
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        wire    [(CPU_ADDRESS_WIDTH-1):0]        mem_addr /* verilator public_flat */;
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        reg                     mem_err /* verilator public_flat */;
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        wire            mmus_ack, mmus_stall;
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        wire    [31:0]   mmus_data;
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        wire            rtn_ack, rtn_stall;
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        wire    [31:0]   rtn_data;
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        wire    ign_stb, ign_we, ign_cache;
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        wire    [(32-LGPGSZB-1):0]       ign_p;
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        wire    [(32-LGPGSZB-1):0]       ign_v;
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        //
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        // mut = Module Under Test
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        //
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        zipmmu  #(.ADDRESS_WIDTH(CPU_ADDRESS_WIDTH),
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                .LGTBL(LGTBL),.PLGPGSZB(LGPGSZB))
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                mut(i_clk, i_reset,
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                        // Slave access
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                        i_ctrl_cyc_stb, i_wb_we, i_wb_addr[(LGTBL+1):0],
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                                i_wb_data,
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                                mmus_ack, mmus_stall, mmus_data,
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                        i_wbm_cyc, i_wbm_stb, i_wb_we, i_exe,
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                                i_wb_addr, i_wb_data, i_wb_sel, i_gie,
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                        mem_cyc, mem_stb, mem_we, mem_addr, mem_idata, mem_sel,
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                                mem_stall, (mem_ack)&&(!mem_err), mem_err, mem_odata,
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                        rtn_stall, rtn_ack, o_rtn_err, o_rtn_miss,
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                                rtn_data,
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                        ign_stb, ign_we, ign_p, ign_v, ign_cache);
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        memdev #(MAW+2) ram(i_clk,
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                mem_cyc, mem_stb, mem_we, mem_addr[(MAW-1):0], mem_idata,
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                                mem_sel,
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                        mem_ack, mem_stall, mem_odata);
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        always@(posedge i_clk)
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        if (i_reset)
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                mem_err <= 1'b0;
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        else if (!mem_cyc)
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                mem_err <= 1'b0;
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        else
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                mem_err <= (mem_err)||((mem_stb)&&(mem_addr[(AW-1):MAW]
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                                        != {{(AW-MAW-1){1'b0}}, 1'b1}));
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        assign  o_rtn_stall = (i_wbm_cyc)&&(rtn_stall);
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        assign  o_rtn_ack   = (i_wbm_cyc)?(rtn_ack) :mmus_ack;
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        assign  o_rtn_data  = (i_wbm_cyc)?(rtn_data):mmus_data;
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        // Make Verilator happy
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        // verilator lint_on UNUSED
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        wire    [2+(32-LGPGSZB)+(32-LGPGSZB)+1+1-1:0]    unused;
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        assign  unused = { ign_stb, ign_we, ign_p, ign_v, ign_cache, mmus_stall };
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        // verilator lint_off UNUSED
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endmodule

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