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1 202 dgisselq 
<HTML><HEAD><TITLE>Next Generation ZipCPU ISA</TITLE></HEAD><BODY>
2 
<H1 align=center>Next Generation Zip CPU ISA</H1>
3 
<P align=center><TABLE BORDER>
4 
<TR>
5 
        <TH>31</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
6 
        <TH>27</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
7 
        <TH>23</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
8 
        <TH>19</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
9 
        <TH>15</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
10 
        <TH>11</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
11 
        <TH>7</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
12 
        <TH>3</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>0</TH>
13 
        <TH>CC</TH><TH>Extra</TH></TR>
14 
<TR><TH>1'Zip</TH><TD colspan=9>&nbsp;</TD><TH colspan=3>3'Cond</TH><TD colspan=19>&nbsp;</TD></TR>
15 
<!-- -->
16 
<TR><TD rowspan=8 colspan=1>0</TD><TD rowspan=8 colspan=9>Any</TD><TD colspan=3><TT>000</TT></TD><TD colspan=19>Always</TD><TD>Y</TD></TR>
17 
<TR><TD colspan=3><TT>001</TT></TD><TD colspan=19>Less-Than</TD><TD rowspan=7>N</TD></TR>
18 
<TR><TD colspan=3><TT>010</TT></TD><TD colspan=19>On Zero</TD></TR>
19 
<TR><TD colspan=3><TT>011</TT></TD><TD colspan=19>Not Zero</TD></TR>
20 
<TR><TD colspan=3><TT>100</TT></TD><TD colspan=19>Greater Than</TD></TR>
21 
<TR><TD colspan=3><TT>101</TT></TD><TD colspan=19>Greater Than/Equal</TD></TR>
22 
<TR><TD colspan=3><TT>110</TT></TD><TD colspan=19>On Carry (unsigned overflow)</TD></TR>
23 
<TR><TD colspan=3><TT>111</TT></TD><TD colspan=19>On (signed) oVerflow</TD></TR>
24 
<!-- -->
25 
<TR><TD rowspan=14>0</TD>
26 
        <TH colspan=4>4'Reg</TH>
27 
        <TH colspan=5>5'OpCod</TH>
28 
        <TH colspan=3>Cond</TH>
29 
        <TH colspan=19>19'Op-B</TH>
30 
        <TH>CC</TH></TR>
31 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>0xxxx</TT></TD><TD colspan=3 rowspan=12 valign=center>Any</TD><TD colspan=19>ALU operation</TD><TD rowspan=1>(y)</TD></TR>
32 
<TR><TD colspan=9 rowspan=2>&nbsp;</TD><TD colspan=1>0</TD><TD colspan=18>18-bit Immediate</TD>
33 
        <TD rowspan=2>&nbsp;</TD></TR>
34 
<TR><TD colspan=1>1</TD><TD colspan=4>B-Reg</TD><TD colspan=14>14-bit Immediate</TD></TR>
35 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>01001</TT></TD><TD>0</TD><TD colspan=2>2'hx</TD><TD colspan=16>LDI(<STRIKE>HI/</STRIKE>LO), 16-bit Imm</TD><TD>N</TD></TR>
36 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>01111</TT></TD>
37 
        <TD colspan=1>AR</TD>
38 
        <TD colspan=4>Reg</TD>
39 
        <TD colspan=1>BR</TD>
40 
        <TD colspan=13>Move, 13-bit Imm</TD>
41 
        <TD>N</TD></TR>
42 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>1000x</TT></TD>
43 
        <TD colspan=19>Compare/Test (ALU)</TD>
44 
        <TD>Y</TD></TR>
45 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>1001w</TT></TD>
46 
        <TD colspan=19>Memory operation, w=write, Op-B=address</TD><TD>N</TD></TR>
47 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>1010x</TT></TD>
48 
        <TD colspan=19>IDIV(U/S), RA=RA/(RB+Imm), uses alt-A</TD><TD>Y</TD></TR>
49 
<TR><TD colspan=3 rowspan=3>3'h7</TD><TD rowspan=3>&nbsp;</TD><TD colspan=5><TT>11000</TT></TD><TD colspan=19>NOOP</TD>
50 
        <TD rowspan=3>N</TD></TR>
51 
<TR><TD colspan=5><TT>11001</TT></TD><TD colspan=19>Break</TD></TR>
52 
<TR><TD colspan=5><TT>11010</TT></TD><TD colspan=19>Bus Lock</TD></TR>
53 
<TR><TD colspan=4>Reg</TD><TD colspan=5><TT>11fff</TT></TD><TD colspan=19>Floating Point operation</TD><TD>Y</TD></TR>
54 
<TR><TD colspan=4>Reg</TD><TD colspan=4><TT>1011</TT></TD><TD colspan=23>Load Immediate (23 bit Immediate, unconditional)</TD><TD>N</TD></TR>
55 
<!-- -->
56 
<TR><TD rowspan=4>1</TD><TD colspan=9 rowspan=5>Any</TD><TD colspan=1 rowspan=4>x</TD><TD colspan=2>00</TD><TD colspan=19>Always</TD>
57 
        <TD rowspan=7>&nbsp;</TD></TR>
58 
<TR><TD colspan=2>01</TD><TD colspan=19>Less Than</TD></TR>
59 
<TR><TD colspan=2>10</TD><TD colspan=19>On Zero</TD></TR>
60 
<TR><TD colspan=2>11</TD><TD colspan=19>Not Zero</TD></TR>
61 
<TR><TD rowspan=1>1</TD><TD colspan=1>1</TD>
62 
        <TD colspan=2>2'bxx</TD><TD colspan=19>Apply condition to second half</TD>
63 
        </TR>
64 
<TR><TD rowspan=2>1</TD>
65 
        <TH colspan=4 rowspan=2>4'Reg</TH>
66 
        <TH colspan=5 rowspan=2>5'OpCod</TH>
67 
        <TD colspan=3 rowspan=2>Any</TD>
68 
        <TD colspan=1 rowspan=1>0</TD><TD colspan=4>4'Imm</TD>
69 
        <TH colspan=4 rowspan=2>4'Reg</TH>
70 
        <TH colspan=5 rowspan=2>5'OpCod</TH>
71 
        <TD colspan=1 rowspan=1>0</TD><TD colspan=4>4'Imm</TD>
72 
        </TR>
73 
<TR><TD>1</TD><TD colspan=4>4'Reg</TD>
74 
        <TD>1</TD><TD colspan=4>4'Reg</TD></TR>
75 
</TABLE>
76 
 
77 
 
78 
<P align=center><TABLE BORDER>
79 
<TR><TH colspan=2>ALU Operation</TH><TH>CC</TH></TR>
80 
<TR><TD><TT>A-0000</TT></TD><TD>SUB (Pairs w/ CMP)</TD><TD rowspan=8>Y</TD></TR>
81 
<TR><TD><TT>A-0001</TT></TD><TD>AND (Pairs w/ OR, and TST)</TD></TR>
82 
<TR><TD><TT>A-0010</TT></TD><TD>ADD (Pairs w/ SUB)</TD></TR>
83 
<TR><TD><TT>A-0011</TT></TD><TD>OR (Pairs w/ AND)</TD></TR>
84 
<TR><TD><TT>A-0100</TT></TD><TD>XOR</TD></TR>
85 
<TR><TD><TT>A-0101</TT></TD><TD>LSR</TD></TR>
86 
<TR><TD><TT>A-0110</TT></TD><TD>LSL (Pairs w/ ROL)</TD></TR>
87 
<TR><TD><TT>A-0111</TT></TD><TD>ASR (Pairs w/ LSR)</TD></TR>
88 
<!-- -->
89 
<TR><TD><TT>A-1000</TT></TD><TD>MPY</TD><TD><STRIKE>N</STRIKE>&nbsp; Y</TD></TR>
90 
<TR><TD><TT>A-1001</TT></TD><TD>LDILO</TD><TD>N</TD></TR>
91 
<TR><TD><TT>A-1010</TT></TD><TD>MPYUHI</TD><TD rowspan=2>Y</TD></TR>
92 
<TR><TD><TT>A-1011</TT></TD><TD>MPYSHI</TD></TR>
93 
<TR><TD><TT>A-1100</TT></TD><TD>BREV</TD><TD><STRIKE>Y</STRIKE>&nbsp; N</TD></TR>
94 
<TR><TD><TT>A-1101</TT></TD><TD><STRIKE>POPC</STRIKE> MOV</TD><TD rowspan=2><STRIKE>Y</STRIKE> N</TD></TR>
95 
<TR><TD><TT>A-1110</TT></TD><TD><STRIKE>ROL</STRIKE> LB</TD></TR>
96 
<TR><TD><TT>A-1111</TT></TD><TD><STRIKE>MOV</STRIKE> SB</TD><TD>N</TD></TR>
97 
</TABLE>
98 
 
99 
<P align=center><TABLE BORDER>
100 
<TR><TH colspan=3>FP Operation</TH><TH>CC</TH></TR>
101 
<TR><TD><TT>F-000</TT></TD><TD>FPADD</TD><TD>Floating point Add</TD><TD rowspan=8>Y</TD></TR>
102 
<TR><TD><TT>F-001</TT></TD><TD>FPSUB</TD><TD>Floating point Subtract &amp; Compare</TD></TR>
103 
<TR><TD><TT>F-010</TT></TD><TD>FPMPY</TD><TD>Floating point multiply</TD></TR>
104 
<TR><TD><TT>F-011</TT></TD><TD>FPDIV</TD><TD>Floating point divide</TD></TR>
105 
<TR><TD><TT>F-100</TT></TD><TD>FPI2F</TD><TD>Convert to floating point</TD></TR>
106 
<TR><TD><TT>F-101</TT></TD><TD>FPF2I</TD><TD>Convert to integer</TD></TR>
107 
<TR><TD><TT>F-110</TT></TD><TD>LH</TD><TD>Load Word</TD></TD></TR>
108 
<TR><TD><TT>F-111</TT></TD><TD>SH</TD><TD>Store Word</TD></TR>
109 
</TABLE>
110 
 
111 
<P align=center><TABLE BORDER>
112 
<TR><TD><TT>00000</TT></TD><TD bgcolor=fffbbb>SUB</TD> <TD><TT>10000</TT></TD><TD bgcolor=bbffff>CMP</TD></TR>
113 
<TR><TD><TT>00001</TT></TD><TD bgcolor=fffbbb>AND</TD> <TD><TT>10001</TT></TD><TD bgcolor=bbffff>TEST</TD></TR>
114 
<TR><TD><TT>00010</TT></TD><TD bgcolor=fffbbb>ADD</TD> <TD><TT>10010</TT></TD><TD bgcolor=d9ffbb>LOD</TD></TR>
115 
<TR><TD><TT>00011</TT></TD><TD bgcolor=fffbbb>OR </TD> <TD><TT>10011</TT></TD><TD bgcolor=d9ffbb>STO</TD></TR>
116 
<TR><TD><TT>00100</TT></TD><TD bgcolor=fffbbb>XOR</TD><TD><TT>10100</TT></TD><TD bgcolor=ffbbff>DIVU</TD></TR>
117 
<TR><TD><TT>00101</TT></TD><TD bgcolor=fffbbb>LSR</TD><TD><TT>10101</TT></TD><TD bgcolor=ffbbff>DIVS</TD></TR>
118 
<TR><TD><TT>00110</TT></TD><TD bgcolor=fffbbb>LSL</TD><TD><TT>10110</TT></TD><TD bgcolor=fff777 rowspan=2>LDI</TD></TR>
119 
<TR><TD><TT>00111</TT></TD><TD bgcolor=fffbbb>ASR</TD><TD><TT>10111</TT></TD></TR>
120 
<TR><TD><TT>01000</TT></TD><TD bgcolor=bbcfef>MPY</TD><TD><TT>11000</TT></TD><TD bgcolor=ffc8bb>FPADD</TD></TR>
121 
<TR><TD><TT>01001</TT></TD><TD bgcolor=fff777>LDILO</TD><TD><TT>11001</TT></TD><TD bgcolor=ffc8bb>FPSUB</TD></TR>
122 
<TR><TD><TT>01010</TT></TD><TD bgcolor=bbcfef>MPYUHI</TD><TD><TT>11010</TT></TD><TD bgcolor=ffc8bb>FPMPY</TD></TR>
123 
<TR><TD><TT>01011</TT></TD><TD bgcolor=bbcfef>MPYSHI</TD><TD><TT>11011</TT></TD><TD bgcolor=ffc8bb>FPDIV</TD></TR>
124 
<TR><TD><TT>01100</TT></TD><TD bgcolor=fff777>BREV</TD><TD><TT>11100</TT></TD><TD bgcolor=ffc8bb>FPI2F</TD></TR>
125 
<TR><TD><TT>01101</TT></TD><TD bgcolor=fff777>MOV</TD><TD><TT>11101</TT></TD><TD bgcolor=ffc8bb>FPF2I</TD></TR>
126 
<TR><TD><TT>01110</TT></TD><TD bgcolor=d9ffbb>LB</TD><TD><TT>11110</TT></TD><TD bgcolor=d9ffbb>LH</TD></TD></TR>
127 
<TR><TD><TT>01111</TT></TD><TD bgcolor=d9ffbb>SB</TD><TD><TT>11111</TT></TD><TD bgcolor=d9ffbb>SH</TD></TR>
128 
</TABLE>
129 
<HR>
130 
<P align=center><TABLE BORDER>
131 
<H1 align=center>Proposed instruction set change</H1>
132 
 
133 
<TABLE border>
134 
<TR>
135 
        <TH>31</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
136 
        <TH>27</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
137 
        <TH>23</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
138 
        <TH>19</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
139 
        <TH>15</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
140 
        <TH>11</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
141 
        <TH>7</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH>
142 
        <TH>3</TH> <TH>&nbsp;</TH> <TH>&nbsp;</TH> <TH>0</TH></TR>
143 
<TR><TD rowspan=2>0</TD><TD colspan=4 rowspan=2>4'DR</TD><TD colspan=5 rowspan=2>5'OpCode</TD><TD colspan=3 rowspan=2>3'Cond</TD><TD>0</TD><TD colspan=18>18'Immediate</TD></TR>
144 
        <TR><TD>1</TD><TD colspan=4>B-Reg</TD><TD colspan=14>14'Immediate</TD></TR>
145 
<TR><TD rowspan=2>1</TD><TD colspan=4 rowspan=2>4'DR</TD>
146 
        <TD colspan=3 rowspan=2>3'OpCode</TD><TD rowspan=2>A</TD>
147 
        <TD colspan=7 rowspan=2>7'Op-B</TD></TD>
148 
        <TD rowspan=2>&nbsp;</TD><TD colspan=4>4'DR</TD><TD colspan=3>3'OpCode</TD><TD>0</TD><TD colspan=7>7'Imm</TD></TR>
149 
<TR><TD colspan=4>4'DR</TD><TD colspan=3>3'OpCode</TD><TD>1</TD><TD colspan=4>B-Reg</TD><TD colspan=3>3'Imm</TD></TR>
150 
<!-- -->
151 
</TABLE>
152 
<P align=center><TABLE BORDER>
153 
<TR><TD><TT>00000</TT></TD><TD bgcolor=fffbbb>SUB</TD> <TD><TT>10000</TT></TD><TD bgcolor=bbffff>CMP</TD><TD><TT>000</TT></TD><TD bgcolor=fffbbb>SUB</TD></TR>
154 
<TR><TD><TT>00001</TT></TD><TD bgcolor=fffbbb>AND</TD> <TD><TT>10001</TT></TD><TD bgcolor=bbffff>TEST</TD><TD><TT>001</TT></TD><TD bgcolor=fffbbb>AND</TD></TR>
155 
<TR><TD><TT>00010</TT></TD><TD bgcolor=fffbbb>ADD</TD> <TD><TT>10010</TT></TD><TD bgcolor=d9ffbb>LW</TD><TD><TT>010</TT></TD><TD bgcolor=fffbbb>ADD</TD></TR>
156 
<TR><TD><TT>00011</TT></TD><TD bgcolor=fffbbb>OR</TD> <TD><TT>10011</TT></TD><TD bgcolor=d9ffbb>SW</TD><TD><TT>011</TT></TD><TD bgcolor=bbffff>CMP</TD></TR>
157 
<TR><TD><TT>00100</TT></TD><TD bgcolor=fffbbb>XOR</TD><TD><TT>10100</TT></TD><TD bgcolor=d9ffbb>LH</TD><TD><TT>100</TT></TD><TD bgcolor=d9ffbb>LW</TD></TR>
158 
<TR><TD><TT>00101</TT></TD><TD bgcolor=fffbbb>LSR</TD><TD><TT>10101</TT></TD><TD bgcolor=d9ffbb>SH</TD><TD><TT>101</TT></TD><TD bgcolor=d9ffbb>SW</TD></TR>
159 
<TR><TD><TT>00110</TT></TD><TD bgcolor=fffbbb>LSL</TD><TD><TT>10110</TT></TD><TD bgcolor=d9ffbb>LB</TD><TD><TT>110</TT></TD><TD bgcolor=dfdfbf>LDI</TD></TR>
160 
<TR><TD><TT>00111</TT></TD><TD bgcolor=fffbbb>ASR</TD><TD><TT>10111</TT></TD><TD bgcolor=d9ffbb>SB</TD><TD><TT>111</TT></TD><TD bgcolor=fff777>MOV</TD></TR>
161 
<TR><TD><TT>01000</TT></TD><TD bgcolor=dfdfbf>BREV</TD><TD><TT>11000</TT></TD><TD bgcolor=dfdfbf rowspan=2>LDI</TD></TR>
162 
<TR><TD><TT>01001</TT></TD><TD bgcolor=dfdfbf>LDILO</TD><TD><TT>11001</TT></TD></TR>
163 
<TR><TD><TT>01010</TT></TD><TD bgcolor=bbcfef>MPYUHI</TD><TD><TT>11010</TT></TD><TD bgcolor=ffc8bb>FPADD</TD></TR>
164 
<TR><TD><TT>01011</TT></TD><TD bgcolor=bbcfef>MPYSHI</TD><TD><TT>11011</TT></TD><TD bgcolor=ffc8bb>FPSUB</TD></TR>
165 
<TR><TD><TT>01100</TT></TD><TD bgcolor=bbcfef>MPY</TD><TD><TT>11100</TT></TD><TD bgcolor=ffc8bb>FPMPY</TD><TD><TT>11100</TT></TD><TD bgcolor=aaaa00ff>BREAK</TD></TR>
166 
<TR><TD><TT>01101</TT></TD><TD bgcolor=fff777>MOV</TD><TD><TT>11101</TT></TD><TD bgcolor=ffc8bb>FPDIV</TD><TD><TT>11101</TT></TD><TD bgcolor=aaaa00ff>LOCK</TD></TR>
167 
<TR><TD><TT>01110</TT></TD><TD bgcolor=ffbbff>DIVU</TD><TD><TT>11110</TT></TD><TD bgcolor=ffc8bb>FPI2F</TD><TD><TT>11110</TT></TD><TD bgcolor=aaaa00ff>SIM</TD></TR>
168 
<TR><TD><TT>01111</TT></TD><TD bgcolor=ffbbff>DIVS</TD><TD><TT>11111</TT></TD><TD bgcolor=ffc8bb>FPF2I</TD><TD><TT>11111</TT></TD><TD bgcolor=aaaa00ff>NOOP</TD></TR>
169 
</TABLE>
170 
 
171 
<H3>VLIW</H3>
172 
<P>The VLIW instructions take 3-bits only for their opcode.  They are designed
173 
to use only the most used opcodes.
174 
<P>LDI will use all opcode bits, and the immediate field will be dedicated to
175 
        its immediate, allowing us to load any 8-bit signed constant
176 
        (-128 to 127).
177 
<P>MOV will use all opcode bits, and the extra bit selecting reg/imm will
178 
        be extended to be an immediate bit, so that we can have any 4'bit
179 
        register offset (-8 to 7)
180 
<P>To make this more usable, the LOD/STO instructions will assume the register
181 
        is SP if no register is given.  This will allow us to offset the stack
182 
        by anything between -64 to 63.  Useful enough to get just about
183 
        anything.
184 
<H3>SIM Codes</H3>
185 
<P>SIM and NOOP instructions are both 32-bit instructions, and both take an
186 
        18-bit immediate.
187 
        This immediate, together with the destination register, is ignored by
188 
                the CPU--only the simulation pays attention to either.
189 
        SIM and NOOP instructions are to be treated identically by the
190 
                simulation (if the CPU is run within a simulation).
191 
        The CPU will create an illegal instruction on any SIM opcode outside
192 
        of the simulator, and ignore any NOOP instruction--no matter what
193 
                the immediate.
194 
        Particular immediate values include:
195 
<OL>
196 
<LI>SIMEXIT: with an 8-bit (signed) exit code
197 
<LI>SIMNOOP: useful for testing if the simulator is present.  Will cause an
198 
        ILLegal instruction if the simulator is not present, but ignored
199 
        otherwise.  This will be the immediate value of zero.
200 
<LI>SIMDUMP: dump the CPU state (all the registers) to the output
201 
<LI>(Console read/write can be done via UART, so not necessary here.)
202 
</OL>
203 
<H3>8-bit bytes</H3>
204 
<P>This particular change is designed to create support for 8-bit bytes.
205 
        Specifically, we added support for LH, SH, LB, and SB instructions
206 
        (Load and store 16-bits, or load and store 8-bits.)
207 
<P>As a consequence, the bottom 2-bits of any address no longer traverse the
208 
        bus.
209 
<H3>Together</H3>
210 
While the VLIW instruction set works well without this change, this
211 
change renders the 3'bit register offsets difficult to use.  Two examples:
212 
<OL>
213 
<LI>The original VLIW allowed a JSR instruction: MOV 1(PC),R0, LOD(PC),PC.  The
214 
        new version would need to be replaced with MOV 4(PC),R0 and LOD(PC),PC,
215 
        but 4 doesn't fit in 3-signed bits.
216 
<LI>  Further, a 3'bit offset to a LOD or STO instruction makes no sense.
217 
</OL>
218 
 
219 
<!-- Colors: FP = ffc8bb, DIV = ffbbff, MOV=fff777,
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                MPY=bbcfef, LOD=d9ffbb, NOOP==aaaa00ff,
221 
                LDI=dfdfbf
222 
 -->
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