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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename:    spec.tex
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%%
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%% Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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%%
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%% Purpose:     This LaTeX file contains all of the documentation/description
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%%              currently provided with this Zip CPU soft core.  It supercedes
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%%              any information about the instruction set or CPUs found
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%%              elsewhere.  It's not nearly as interesting, though, as the PDF
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%%              file it creates, so I'd recommend reading that before diving
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%%              into this file.  You should be able to find the PDF file in
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%%              the SVN distribution together with this PDF file and a copy of
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%%              the GPL-3.0 license this file is distributed under.  If not,
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%%              just type 'make' in the doc directory and it (should) build
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%%              without a problem.
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%%
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%%
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%% Creator:     Dan Gisselquist
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%%              Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of  the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program.  (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.)  If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License:     GPL, v3, as defined and found on www.gnu.org,
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%%              http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass{gqtekspec}
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\project{Zip CPU}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.2}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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58
This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of  the GNU General Public License as published
60
by the Free Software Foundation, either version 3 of the License, or (at
61
your option) any later version.
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63
This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
65
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
66
for more details.
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68
You should have received a copy of the GNU General Public License along
69
with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a
70
copy.
71
\end{license}
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\begin{revisionhistory}
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0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline
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0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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\listoffigures
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\listoftables
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\begin{preface}
82
Many people have asked me why I am building the Zip CPU. ARM processors are
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good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both
84
have better toolsets than the Zip CPU will ever have. OpenRISC is also
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available, RISC--V may be replacing it. Why build a new processor?
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87
The easiest, most obvious answer is the simple one: Because I can.
88
 
89
There's more to it, though. There's a lot that I would like to do with a
90
processor, and I want to be able to do it in a vendor independent fashion.
91
I would like to be able to generate Verilog code that can run equivalently
92
on both Xilinx and Altera chips, and that can be easily ported from one
93
manufacturer's chipsets to another. Even more, before purchasing a chip or a
94
board, I would like to know that my chip works. I would like to build a test
95
bench to test components with, and Verilator is my chosen test bench. This
96
forces me to use all Verilog, and it prevents me from using any proprietary
97
cores. For this reason, Microblaze and Nios are out of the question.
98
 
99
Why not OpenRISC? That's a hard question. The OpenRISC team has done some
100
wonderful work on an amazing processor, and I'll have to admit that I am
101
envious of what they've accomplished. I would like to port binutils to the
102
Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The
103
OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has
104
a lot of features of modern CPUs within it that ... well, let's just say it's
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not the little guy on the block. The Zip CPU is lighter weight, costing only
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about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic
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peripherals.
108
 
109
My final reason is that I'm building the Zip CPU as a learning experience. The
110
Zip CPU has allowed me to learn a lot about how CPUs work on a very micro
111
level. For the first time, I am beginning to understand many of the Computer
112
Architecture lessons from years ago.
113
 
114
To summarize: Because I can, because it is open source, because it is light
115
weight, and as an exercise in learning.
116
 
117
\end{preface}
118
 
119
\chapter{Introduction}
120
\pagenumbering{arabic}
121
\setcounter{page}{1}
122
 
123
 
124
The original goal of the ZIP CPU was to be a very simple CPU.   You might
125
think of it as a poor man's alternative to the OpenRISC architecture.
126
For this reason, all instructions have been designed to be as simple as
127
possible, and are all designed to be executed in one instruction cycle per
128
instruction, barring pipeline stalls.  Indeed, even the bus has been simplified
129
to a constant 32-bit width, with no option for more or less.  This has
130
resulted in the choice to drop push and pop instructions, pre-increment and
131
post-decrement addressing modes, and more.
132
 
133
For those who like buzz words, the Zip CPU is:
134
\begin{itemize}
135
\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits,
136
                instructions are 32-bits wide, etc.
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\item A RISC CPU.  There is no microcode for executing instructions.  All
138
        instructions are designed to be completed in one clock cycle.
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\item A Load/Store architecture.  (Only load and store instructions
140
                can access memory.)
141
\item Wishbone compliant.  All peripherals are accessed just like
142
                memory across this bus.
143
\item A Von-Neumann architecture.  (The instructions and data share a
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                common bus.)
145
\item A pipelined architecture, having stages for {\bf Prefetch},
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                {\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory}
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                unit, and {\bf Write-back}.  See Fig.~\ref{fig:cpu}
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\begin{figure}\begin{center}
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\includegraphics[width=3.5in]{../gfx/cpu.eps}
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\caption{Zip CPU internal pipeline architecture}\label{fig:cpu}
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\end{center}\end{figure}
152
                for a diagram of this structure.
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\item Completely open source, licensed under the GPL.\footnote{Should you
154
        need a copy of the Zip CPU licensed under other terms, please
155
        contact me.}
156
\end{itemize}
157
 
158
Now, however, that I've worked on the Zip CPU for a while, it is not nearly
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as simple as I originally hoped.  Worse, I've had to adjust to create
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capabilities that I was never expecting to need.  These include:
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\begin{itemize}
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\item {\bf Extenal Debug:} Once placed upon an FPGA, some external means is
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        still necessary to debug this CPU.  That means that there needs to be
164
        an external register that can control the CPU: reset it, halt it, step
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        it, and tell whether it is running or not.  My chosen interface
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        includes a second register similar to this control register.  This
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        second register allows the external controller or debugger to examine
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        registers internal to the CPU.
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170
\item {\bf Internal Debug:} Being able to run a debugger from within
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        a user process requires an ability to step a user process from
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        within a debugger.  It also requires a break instruction that can
173
        be substituted for any other instruction, and substituted back.
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        The break is actually difficult: the break instruction cannot be
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        allowed to execute.  That way, upon a break, the debugger should
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        be able to jump back into the user process to step the instruction
177
        that would've been at the break point initially, and then to
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        replace the break after passing it.
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        Incidentally, this break messes with the prefetch cache and the
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        pipeline: if you change an instruction partially through the pipeline,
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        the whole pipeline needs to be cleansed.  Likewise if you change
183
        an instruction in memory, you need to make sure the cache is reloaded
184
        with the new instruction.
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\item {\bf Prefetch Cache:} My original implementation had a very
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        simple prefetch stage.  Any time the PC changed the prefetch would go
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        and fetch the new instruction.  While this was perhaps this simplest
189
        approach, it cost roughly five clocks for every instruction.  This
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        was deemed unacceptable, as I wanted a CPU that could execute
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        instructions in one cycle.  I therefore have a prefetch cache that
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        issues pipelined wishbone accesses to memory and then pushes
193
        instructions at the CPU.  Sadly, this accounts for about 20\% of the
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        logic in the entire CPU, or 15\% of the logic in the entire system.
195
 
196
 
197
\item {\bf Operating System:} In order to support an operating system,
198
        interrupts and so forth, the CPU needs to support supervisor and
199
        user modes, as well as a means of switching between them.  For example,
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        the user needs a means of executing a system call.  This is the
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        purpose of the {\bf `trap'} instruction.  This instruction needs to
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        place the CPU into supervisor mode (here equivalent to disabling
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        interrupts), as well as handing it a parameter such as identifying
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        which O/S function was called.
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My initial approach to building a trap instruction was to create an external
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peripheral which, when written to, would generate an interrupt and could
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return the last value written to it.  In practice, this approach didn't work
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at all: the CPU executed two instructions while waiting for the
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trap interrupt to take place.  Since then, I've decided to keep the rest of
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the CC register for that purpose so that a write to the CC register, with the
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GIE bit cleared, could be used to execute a trap.  This has other problems,
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though, primarily in the limitation of the uses of the CC register.  In
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particular, the CC register is the best place to put CPU state information and
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to ``announce'' special CPU features (floating point, etc).  So the trap
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instruction still switches to interrupt mode, but the CC register is not
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nearly as useful for telling the supervisor mode processor what trap is being
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executed.
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220
Modern timesharing systems also depend upon a {\bf Timer} interrupt
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to handle task swapping.  For the Zip CPU, this interrupt is handled
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external to the CPU as part of the CPU System, found in {\tt zipsystem.v}.
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The timer module itself is found in {\tt ziptimer.v}.
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225
\item {\bf Pipeline Stalls:} My original plan was to not support pipeline
226
        stalls at all, but rather to require the compiler to properly schedule
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        all instructions so that stalls would never be necessary.  After trying
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        to build such an architecture, I gave up, having learned some things:
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230
        For example, in  order to facilitate interrupt handling and debug
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        stepping, the CPU needs to know what instructions have finished, and
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        which have not.  In other words, it needs to know where it can restart
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        the pipeline from.  Once restarted, it must act as though it had
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        never stopped.  This killed my idea of delayed branching, since what
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        would be the appropriate program counter to restart at?  The one the
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        CPU was going to branch to, or the ones in the delay slots?  This
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        also makes the idea of compressed instruction codes difficult, since,
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        again, where do you restart on interrupt?
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240
        So I switched to a model of discrete execution: Once an instruction
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        enters into either the ALU or memory unit, the instruction is
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        guaranteed to complete.  If the logic recognizes a branch or a
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        condition that would render the instruction entering into this stage
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        possibly inappropriate (i.e. a conditional branch preceeding a store
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        instruction for example), then the pipeline stalls for one cycle
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        until the conditional branch completes.  Then, if it generates a new
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        PC address, the stages preceeding are all wiped clean.
248
 
249
        The discrete execution model allows such things as sleeping: if the
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        CPU is put to ``sleep,'' the ALU and memory stages stall and back up
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        everything before them.  Likewise, anything that has entered the ALU
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        or memory stage when the CPU is placed to sleep continues to completion.
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        To handle this logic, each pipeline stage has three control signals:
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        a valid signal, a stall signal, and a clock enable signal.  In
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        general, a stage stalls if it's contents are valid and the next step
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        is stalled.  This allows the pipeline to fill any time a later stage
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        stalls.
258
 
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        This approach is also different from other pipeline approaches.  Instead
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        of keeping the entire pipeline filled, each stage is treated
261
        independently.  Therefore, individual stages may move forward as long
262
        as the subsequent stage is available, regardless of whether the stage
263
        behind it is filled.
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\item {\bf Verilog Modules:} When examining how other processors worked
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        here on open cores, many of them had one separate module per pipeline
267
        stage.  While this appeared to me to be a fascinating and commendable
268
        idea, my own implementation didn't work out quite so nicely.
269
 
270
        As an example, the decode module produces a {\em lot} of
271
        control wires and registers.  Creating a module out of this, with
272
        only the simplest of logic within it, seemed to be more a lesson
273
        in passing wires around, rather than encapsulating logic.
274
 
275
        Another example was the register writeback section.  I would love
276
        this section to be a module in its own right, and many have made them
277
        such.  However, other modules depend upon writeback results other
278
        than just what's placed in the register (i.e., the control wires).
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        For these reasons, I didn't manage to fit this section into it's
280
        own module.
281
 
282
        The result is that the majority of the CPU code can be found in
283
        the {\tt zipcpu.v} file.
284
\end{itemize}
285
 
286
With that introduction out of the way, let's move on to the instruction
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set.
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289
\chapter{CPU Architecture}\label{chap:arch}
290
 
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The Zip CPU supports a set of two operand instructions, where the second operand
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(always a register) is the result.  The only exception is the store instruction,
293
where the first operand (always a register) is the source of the data to be
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stored.
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\section{Simplified Bus}
297
The bus architecture of the Zip CPU is that of a simplified WISHBONE bus.
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It has been simplified in this fashion: all operations are 32--bit operations.
299
The bus is neither little endian nor bit endian.  For this reason, all words
300
are 32--bits.  All instructions are also 32--bits wide.  Everything has been
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built around the 32--bit word.
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\section{Register Set}
304
The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor
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and a user set as shown in Fig.~\ref{fig:regset}.
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\begin{figure}\begin{center}
307
\includegraphics[width=3.5in]{../gfx/regset.eps}
308
\caption{Zip CPU Register File}\label{fig:regset}
309
\end{center}\end{figure}
310
The supervisor set is used in interrupt mode when interrupts are disabled,
311
whereas the user set is used otherwise.  Of this register set, the Program
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Counter (PC) is register 15, whereas the status register (SR) or condition
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code register
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(CC) is register 14.  By convention, the stack pointer will be register 13 and
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noted as (SP)--although there is nothing special about this register other
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than this convention.
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The CPU can access both register sets via move instructions from the
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supervisor state, whereas the user state can only access the user registers.
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320
The status register is special, and bears further mention.  The lower
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10 bits of the status register form a set of CPU state and condition codes.
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Writes to other bits of this register are preserved.
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324
Of the eight condition codes, the bottom four are the current flags:
325
                Zero (Z),
326
                Carry (C),
327
                Negative (N),
328
                and Overflow (V).
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330
The next bit is a clock enable (0 to enable) or sleep bit (1 to put
331
        the CPU to sleep).  Setting this bit will cause the CPU to
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        wait for an interrupt (if interrupts are enabled), or to
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        completely halt (if interrupts are disabled).
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The sixth bit is a global interrupt enable bit (GIE).  When this
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        sixth bit is a `1' interrupts will be enabled, else disabled.  When
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        interrupts are disabled, the CPU will be in supervisor mode, otherwise
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        it is in user mode.  Thus, to execute a context switch, one only
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        need enable or disable interrupts.  (When an interrupt line goes
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        high, interrupts will automatically be disabled, as the CPU goes
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        and deals with its context switch.)  Special logic has been added to
341
        keep the user mode from setting the sleep register and clearing the
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        GIE register at the same time, with clearing the GIE register taking
343
        precedence.
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345
The seventh bit is a step bit.  This bit can be
346
        set from supervisor mode only.  After setting this bit, should
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        the supervisor mode process switch to user mode, it would then
348
        accomplish one instruction in user mode before returning to supervisor
349
        mode.  Then, upon return to supervisor mode, this bit will
350
        be automatically cleared.  This bit has no effect on the CPU while in
351
        supervisor mode.
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353
        This functionality was added to enable a userspace debugger
354
        functionality on a user process, working through supervisor mode
355
        of course.
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357
 
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The eighth bit is a break enable bit.  This controls whether a break
359
instruction in user mode will halt the processor for an external debugger
360
(break enabled), or whether the break instruction will simply send send the
361
CPU into interrupt mode.  Encountering a break in supervisor mode will
362
halt the CPU independent of the break enable bit.  This bit can only be set
363
within supervisor mode.
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% Should break enable be a supervisor mode bit, while the break enable bit
366
% in user mode is a break has taken place bit?
367
%
368
 
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This functionality was added to enable an external debugger to
370
        set and manage breakpoints.
371
 
372
The ninth bit is reserved for a floating point enable bit.  When set, the
373
arithmetic for the next instruction will be sent to a floating point unit.
374
Such a unit may later be added as an extension to the Zip CPU.  If the
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CPU does not support floating point instructions, this bit will never be set.
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The instruction set could also be simply extended to allow other data types
377
in this fashion, such as two by 16--bit vector operations or four by 8--bit
378
vector operations.
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380
The tenth bit is a trap bit.  It is set whenever the user requests a soft
381
interrupt, and cleared on any return to userspace command.  This allows the
382
supervisor, in supervisor mode, to determine whether it got to supervisor
383
mode from a trap or from an external interrupt or both.
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These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.
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\begin{table}
387
\begin{center}
388
\begin{tabular}{l|l}
389
Bit & Meaning \\\hline
390
9 & Soft trap, set on a trap from user mode, cleared when returing to user mode\\\hline
391
8 & (Reserved for) Floating point enable \\\hline
392
7 & Halt on break, to support an external debugger \\\hline
393
6 & Step, single step the CPU in user mode\\\hline
394
5 & GIE, or Global Interrupt Enable \\\hline
395
4 & Sleep \\\hline
396
3 & V, or overflow bit.\\\hline
397
2 & N, or negative bit.\\\hline
398
1 & C, or carry bit.\\\hline
399
 
400
\end{tabular}
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\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}
402
\end{center}\end{table}
403
 
404 21 dgisselq
\section{Conditional Instructions}
405
Most, although not quite all, instructions are conditionally executed.  From
406
the four condition code flags, eight conditions are defined.  These are shown
407
in Tbl.~\ref{tbl:conditions}.
408
\begin{table}
409
\begin{center}
410
\begin{tabular}{l|l|l}
411
Code & Mneumonic & Condition \\\hline
412
3'h0 & None & Always execute the instruction \\
413
3'h1 & {\tt .Z} & Only execute when 'Z' is set \\
414
3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\
415
3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\
416
3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\
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3'h5 & {\tt .LT} & Less than ('N' set) \\
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3'h6 & {\tt .C} & Carry set\\
419
3'h7 & {\tt .V} & Overflow set\\
420
\end{tabular}
421
\caption{Conditions for conditional operand execution}\label{tbl:conditions}
422
\end{center}
423
\end{table}
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There is no condition code for less than or equal, not C or not V.  Sorry,
425
I ran out of space in 3--bits.  Using these conditions will take an extra
426 32 dgisselq
instruction and a pipeline stall.  (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
427 21 dgisselq
 
428
\section{Operand B}
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Many instruction forms have a 21-bit source ``Operand B'' associated with them.
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This Operand B is either equal to a register plus a signed immediate offset,
431
or an immediate offset by itself.  This value is encoded as shown in
432
Tbl.~\ref{tbl:opb}.
433
\begin{table}\begin{center}
434
\begin{tabular}{|l|l|l|}\hline
435
Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline
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1'b0 & \multicolumn{2}{l|}{20--bit Signed Immediate value} \\\hline
437
1'b1 & 4-bit Register & 16--bit Signed immediate offset \\\hline
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\end{tabular}
439
\caption{Bit allocation for Operand B}\label{tbl:opb}
440
\end{center}\end{table}
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442
Sixteen and twenty bit immediates don't make sense for all instructions.  For
443
example, what is the point of a 20--bit immediate when executing a 16--bit
444
multiply?  Likewise, why have a 16--bit immediate when adding to a logical
445
or arithmetic shift?  In these cases, the extra bits are reserved for future
446
instruction possibilities.
447
 
448 21 dgisselq
\section{Address Modes}
449
The ZIP CPU supports two addressing modes: register plus immediate, and
450
immediate address.  Addresses are therefore encoded in the same fashion as
451
Operand B's, shown above.
452
 
453
A lot of long hard thought was put into whether to allow pre/post increment
454
and decrement addressing modes.  Finding no way to use these operators without
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taking two or more clocks per instruction,\footnote{The two clocks figure
456
comes from the design of the register set, allowing only one write per clock.
457
That write is either from the memory unit or the ALU, but never both.} these
458
addressing modes have been
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removed from the realm of possibilities.  This means that the Zip CPU has no
460
native way of executing push, pop, return, or jump to subroutine operations.
461 24 dgisselq
Each of these instructions can be emulated with a set of instructions from the
462
existing set.
463 21 dgisselq
 
464
\section{Move Operands}
465
The previous set of operands would be perfect and complete, save only that
466 24 dgisselq
the CPU needs access to non--supervisory registers while in supervisory mode.
467
Therefore, the MOV instruction is special and offers access to these registers
468
\ldots when in supervisory mode.  To keep the compiler simple, the extra bits
469
are ignored in non-supervisory mode (as though they didn't exist), rather than
470
being mapped to new instructions or additional capabilities.  The bits
471
indicating which register set each register lies within are the A-Usr and
472
B-Usr bits.  When set to a one, these refer to a user mode register.  When set
473
to a zero, these refer to a register in the current mode, whether user or
474
supervisor.  Further, because a load immediate instruction exists, there is no
475
move capability between an immediate and a register: all moves come from either
476
a register or a register plus an offset.
477 21 dgisselq
 
478 24 dgisselq
This actually leads to a bit of a problem: since the MOV instruction encodes
479
which register set each register is coming from or moving to, how shall a
480
compiler or assembler know how to compile a MOV instruction without knowing
481
the mode of the CPU at the time?  For this reason, the compiler will assume
482
all MOV registers are supervisor registers, and display them as normal.
483
Anything with the user bit set will be treated as a user register.  The CPU
484
will quietly ignore the supervisor bits while in user mode, and anything
485
marked as a user register will always be valid.  (Did I just say that in the
486
last paragraph?)
487 21 dgisselq
 
488
\section{Multiply Operations}
489 24 dgisselq
The Zip CPU supports two Multiply operations, a
490 21 dgisselq
16x16 bit signed multiply (MPYS) and the same but unsigned (MPYU).  In both
491
cases, the operand is a register plus a 16-bit immediate, subject to the
492
rule that the register cannot be the PC or CC registers.  The PC register
493
field has been stolen to create a multiply by immediate instruction.  The
494
CC register field is reserved.
495
 
496
\section{Floating Point}
497 32 dgisselq
The ZIP CPU does not support floating point operations.  However, the
498
instruction set reserves two possibilities for future floating point
499
operations.
500 21 dgisselq
 
501 32 dgisselq
The first floating point operation hole in the instruction set involves
502
setting the floating point bit in the CC register.  The next instruction
503
will simply interpret its operands as floating point instructions.
504
Not all instructions, however, have floating point equivalents.  Further, the
505
immediate fields do not apply in floating point mode, and must be set to
506
zero.  Not all instructions make sense as floating point operations.
507
Therefore, only the CMP, SUB, ADD, and MPY instructions may be issued as
508
floating point instructions.  Other instructions allow the examining of the
509
floating point bit in the CC register.  In all cases, the floating point bit
510
is cleared one instruction after it is set.
511 21 dgisselq
 
512 32 dgisselq
The other possibility for floating point operations involves exploiting the
513
hole in the instruction set that the NOOP and BREAK instructions reside within.
514
These two instructions use 24--bits of address space.  A simple adjustment
515
to this space could create instructions with 4--bit register addresses for
516
each register, a 3--bit field for conditional execution, and a 2--bit field
517
for which operation.  In this fashion, such a floating point capability would
518
only fill 13--bits of the 24--bit field, still leaving lots of room for
519
expansion.
520
 
521
In both cases, the Zip CPU would support 32--bit single precision floats
522
only.
523
 
524
The current architecture does not support a floating point not-implemented
525
interrupt.  Any soft floating point emulation must be done deliberately.
526
 
527 21 dgisselq
\section{Native Instructions}
528
The instruction set for the Zip CPU is summarized in
529
Tbl.~\ref{tbl:zip-instructions}.
530
\begin{table}\begin{center}
531
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline
532
Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}
533
        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}
534
        & Sets CC? \\\hline
535
CMP(Sub) & \multicolumn{4}{l|}{4'h0}
536
                & \multicolumn{4}{l|}{D. Reg}
537
                & \multicolumn{3}{l|}{Cond.}
538
                & \multicolumn{21}{l|}{Operand B}
539
                & Yes \\\hline
540 24 dgisselq
TST(And) & \multicolumn{4}{l|}{4'h1}
541 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
542
                & \multicolumn{3}{l|}{Cond.}
543
                & \multicolumn{21}{l|}{Operand B}
544
        & Yes \\\hline
545
MOV & \multicolumn{4}{l|}{4'h2}
546
                & \multicolumn{4}{l|}{D. Reg}
547
                & \multicolumn{3}{l|}{Cond.}
548
                & A-Usr
549
                & \multicolumn{4}{l|}{B-Reg}
550
                & B-Usr
551
                & \multicolumn{15}{l|}{15'bit signed offset}
552
                & \\\hline
553
LODI & \multicolumn{4}{l|}{4'h3}
554
                & \multicolumn{4}{l|}{R. Reg}
555
                & \multicolumn{24}{l|}{24'bit Signed Immediate}
556
                & \\\hline
557
NOOP & \multicolumn{4}{l|}{4'h4}
558
                & \multicolumn{4}{l|}{4'he}
559
                & \multicolumn{24}{l|}{24'h00}
560
                & \\\hline
561
BREAK & \multicolumn{4}{l|}{4'h4}
562
                & \multicolumn{4}{l|}{4'he}
563
                & \multicolumn{24}{l|}{24'h01}
564
                & \\\hline
565
{\em Rsrd} & \multicolumn{4}{l|}{4'h4}
566
                & \multicolumn{4}{l|}{4'he}
567
                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}
568
                & \\\hline
569
LODIHI & \multicolumn{4}{l|}{4'h4}
570
                & \multicolumn{4}{l|}{4'hf}
571
                & \multicolumn{3}{l|}{Cond.}
572
                & 1'b1
573
                & \multicolumn{4}{l|}{R. Reg}
574
                & \multicolumn{16}{l|}{16-bit Immediate}
575
                & \\\hline
576
LODILO & \multicolumn{4}{l|}{4'h4}
577
                & \multicolumn{4}{l|}{4'hf}
578
                & \multicolumn{3}{l|}{Cond.}
579
                & 1'b0
580
                & \multicolumn{4}{l|}{R. Reg}
581
                & \multicolumn{16}{l|}{16-bit Immediate}
582
                & \\\hline
583
16-b MPYU & \multicolumn{4}{l|}{4'h4}
584
                & \multicolumn{4}{l|}{R. Reg}
585
                & \multicolumn{3}{l|}{Cond.}
586
                & 1'b0 & \multicolumn{4}{l|}{Reg}
587
                & \multicolumn{16}{l|}{16-bit Offset}
588
                & Yes \\\hline
589
16-b MPYU(I) & \multicolumn{4}{l|}{4'h4}
590
                & \multicolumn{4}{l|}{R. Reg}
591
                & \multicolumn{3}{l|}{Cond.}
592
                & 1'b0 & \multicolumn{4}{l|}{4'hf}
593
                & \multicolumn{16}{l|}{16-bit Offset}
594
                & Yes \\\hline
595
16-b MPYS & \multicolumn{4}{l|}{4'h4}
596
                & \multicolumn{4}{l|}{R. Reg}
597
                & \multicolumn{3}{l|}{Cond.}
598
                & 1'b1 & \multicolumn{4}{l|}{Reg}
599
                & \multicolumn{16}{l|}{16-bit Offset}
600
                & Yes \\\hline
601
16-b MPYS(I) & \multicolumn{4}{l|}{4'h4}
602
                & \multicolumn{4}{l|}{R. Reg}
603
                & \multicolumn{3}{l|}{Cond.}
604
                & 1'b1 & \multicolumn{4}{l|}{4'hf}
605
                & \multicolumn{16}{l|}{16-bit Offset}
606
                & Yes \\\hline
607
ROL & \multicolumn{4}{l|}{4'h5}
608
                & \multicolumn{4}{l|}{R. Reg}
609
                & \multicolumn{3}{l|}{Cond.}
610
                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}
611
                & \\\hline
612
LOD & \multicolumn{4}{l|}{4'h6}
613
                & \multicolumn{4}{l|}{R. Reg}
614
                & \multicolumn{3}{l|}{Cond.}
615
                & \multicolumn{21}{l|}{Operand B address}
616
                & \\\hline
617
STO & \multicolumn{4}{l|}{4'h7}
618
                & \multicolumn{4}{l|}{D. Reg}
619
                & \multicolumn{3}{l|}{Cond.}
620
                & \multicolumn{21}{l|}{Operand B address}
621
                & \\\hline
622
SUB & \multicolumn{4}{l|}{4'h8}
623
        &       \multicolumn{4}{l|}{R. Reg}
624
        &       \multicolumn{3}{l|}{Cond.}
625 32 dgisselq
        &       \multicolumn{21}{l|}{Operand B}
626 21 dgisselq
        & Yes \\\hline
627
AND & \multicolumn{4}{l|}{4'h9}
628
        &       \multicolumn{4}{l|}{R. Reg}
629
        &       \multicolumn{3}{l|}{Cond.}
630
        &       \multicolumn{21}{l|}{Operand B}
631
        & Yes \\\hline
632
ADD & \multicolumn{4}{l|}{4'ha}
633
        &       \multicolumn{4}{l|}{R. Reg}
634
        &       \multicolumn{3}{l|}{Cond.}
635
        &       \multicolumn{21}{l|}{Operand B}
636
        & Yes \\\hline
637
OR & \multicolumn{4}{l|}{4'hb}
638
        &       \multicolumn{4}{l|}{R. Reg}
639
        &       \multicolumn{3}{l|}{Cond.}
640
        &       \multicolumn{21}{l|}{Operand B}
641
        & Yes \\\hline
642
XOR & \multicolumn{4}{l|}{4'hc}
643
        &       \multicolumn{4}{l|}{R. Reg}
644
        &       \multicolumn{3}{l|}{Cond.}
645
        &       \multicolumn{21}{l|}{Operand B}
646
        & Yes \\\hline
647
LSL/ASL & \multicolumn{4}{l|}{4'hd}
648
        &       \multicolumn{4}{l|}{R. Reg}
649
        &       \multicolumn{3}{l|}{Cond.}
650
        &       \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits}
651
        & Yes \\\hline
652
ASR & \multicolumn{4}{l|}{4'he}
653
        &       \multicolumn{4}{l|}{R. Reg}
654
        &       \multicolumn{3}{l|}{Cond.}
655
        &       \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits}
656
        & Yes \\\hline
657
LSR & \multicolumn{4}{l|}{4'hf}
658
        &       \multicolumn{4}{l|}{R. Reg}
659
        &       \multicolumn{3}{l|}{Cond.}
660
        &       \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits}
661
        & Yes \\\hline
662
\end{tabular}
663
\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions}
664
\end{center}\end{table}
665
 
666
As you can see, there's lots of room for instruction set expansion.  The
667 24 dgisselq
NOOP and BREAK instructions are the only instructions within one particular
668 32 dgisselq
24--bit hole.  This spaces are reserved for future enhancements.  For example,
669
floating point operations, consisting of a 3-bit floating point operation,
670
two 4-bit registers, no immediate offset, and a 3-bit condition would fit
671
nicely into 14--bits of this address space--making it so that the floating
672
point bit in the CC register need not be used.
673 21 dgisselq
 
674
\section{Derived Instructions}
675
The ZIP CPU supports many other common instructions, but not all of them
676 24 dgisselq
are single cycle instructions.  The derived instruction tables,
677 21 dgisselq
Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, and~\ref{tbl:derived-3},
678
help to capture some of how these other instructions may be implemented on
679
the ZIP CPU.  Many of these instructions will have assembly equivalents,
680
such as the branch instructions, to facilitate working with the CPU.
681
\begin{table}\begin{center}
682
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
683
Mapped & Actual  & Notes \\\hline
684
\parbox[t]{1.4in}{ADD Ra,Rx\\ADDC Rb,Ry}
685
        & \parbox[t]{1.5in}{Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
686
        & Add with carry \\\hline
687
BRA.Cond +/-\$Addr
688 24 dgisselq
        & \hbox{Mov.cond \$Addr+PC,PC}
689
        & Branch or jump on condition.  Works for 15--bit
690
                signed address offsets.\\\hline
691 21 dgisselq
BRA.Cond +/-\$Addr
692
        & \parbox[t]{1.5in}{LDI \$Addr,Rx \\ ADD.cond Rx,PC}
693
        & Branch/jump on condition.  Works for
694
        23 bit address offsets, but costs a register, an extra instruction,
695
        and setsthe flags. \\\hline
696
BNC PC+\$Addr
697
        & \parbox[t]{1.5in}{Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
698
        & Example of a branch on an unsupported
699
                condition, in this case a branch on not carry \\\hline
700
BUSY & MOV \$-1(PC),PC & Execute an infinite loop \\\hline
701
CLRF.NZ Rx
702
        & XOR.NZ Rx,Rx
703
        & Clear Rx, and flags, if the Z-bit is not set \\\hline
704
CLR Rx
705
        & LDI \$0,Rx
706
        & Clears Rx, leaves flags untouched.  This instruction cannot be
707
                conditional. \\\hline
708
EXCH.W Rx
709
        & ROL \$16,Rx
710
        & Exchanges the top and bottom 16'bit words of Rx \\\hline
711
HALT
712
        & Or \$SLEEP,CC
713
        & Executed while in interrupt mode.  In user mode this is simply a
714
        wait until interrupt instructioon. \\\hline
715
INT & LDI \$0,CC
716
        & Since we're using the CC register as a trap vector as well, this
717
        executes TRAP \#0. \\\hline
718
IRET
719
        & OR \$GIE,CC
720
        & Also an RTU instruction (Return to Userspace) \\\hline
721
JMP R6+\$Addr
722
        & MOV \$Addr(R6),PC
723
        & \\\hline
724
JSR PC+\$Addr
725
        & \parbox[t]{1.5in}{SUB \$1,SP \\\
726
        MOV \$3+PC,R0 \\
727
        STO R0,1(SP) \\
728
        MOV \$Addr+PC,PC \\
729
        ADD \$1,SP}
730 24 dgisselq
        & Jump to Subroutine. Note the required cleanup instruction after
731
        returning. \\\hline
732 21 dgisselq
JSR PC+\$Addr
733
        & \parbox[t]{1.5in}{MOV \$3+PC,R12 \\ MOV \$addr+PC,PC}
734
        &This is the high speed
735
        version of a subroutine call, necessitating a register to hold the
736
        last PC address.  In its favor, this method doesn't suffer the
737
        mandatory memory access of the other approach. \\\hline
738
LDI.l \$val,Rx
739
        & \parbox[t]{1.5in}{LDIHI (\$val$>>$16)\&0x0ffff, Rx \\
740
                        LDILO (\$val \& 0x0ffff)}
741
        & Sadly, there's not enough instruction
742
                space to load a complete immediate value into any register.
743
                Therefore, fully loading any register takes two cycles.
744
                The LDIHI (load immediate high) and LDILO (load immediate low)
745
                instructions have been created to facilitate this. \\\hline
746
\end{tabular}
747
\caption{Derived Instructions}\label{tbl:derived-1}
748
\end{center}\end{table}
749
\begin{table}\begin{center}
750
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
751
Mapped & Actual  & Notes \\\hline
752
LOD.b \$addr,Rx
753
        & \parbox[t]{1.5in}{%
754
        LDI     \$addr,Ra \\
755
        LDI     \$addr,Rb \\
756
        LSR     \$2,Ra \\
757
        AND     \$3,Rb \\
758
        LOD     (Ra),Rx \\
759
        LSL     \$3,Rb \\
760
        SUB     \$32,Rb \\
761
        ROL     Rb,Rx \\
762
        AND \$0ffh,Rx}
763
        & \parbox[t]{3in}{This CPU is designed for 32'bit word
764
        length instructions.  Byte addressing is not supported by the CPU or
765
        the bus, so it therefore takes more work to do.
766
 
767
        Note also that in this example, \$Addr is a byte-wise address, where
768 24 dgisselq
        all other addresses in this document are 32-bit wordlength addresses.
769
        For this reason,
770 21 dgisselq
        we needed to drop the bottom two bits.  This also limits the address
771
        space of character accesses using this method from 16 MB down to 4MB.}
772
                \\\hline
773
\parbox[t]{1.5in}{LSL \$1,Rx\\ LSLC \$1,Ry}
774
        & \parbox[t]{1.5in}{LSL \$1,Ry \\
775
        LSL \$1,Rx \\
776
        OR.C \$1,Ry}
777
        & Logical shift left with carry.  Note that the
778
        instruction order is now backwards, to keep the conditions valid.
779
        That is, LSL sets the carry flag, so if we did this the othe way
780
        with Rx before Ry, then the condition flag wouldn't have been right
781
        for an OR correction at the end. \\\hline
782
\parbox[t]{1.5in}{LSR \$1,Rx \\ LSRC \$1,Ry}
783
        & \parbox[t]{1.5in}{CLR Rz \\
784
        LSR \$1,Ry \\
785
        LDIHI.C \$8000h,Rz \\
786
        LSR \$1,Rx \\
787
        OR Rz,Rx}
788
        & Logical shift right with carry \\\hline
789
NEG Rx & \parbox[t]{1.5in}{XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline
790
NOOP & NOOP & While there are many
791
        operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these
792
        operations have consequences in that they might stall the bus if
793
        Rx isn't ready yet.  For this reason, we have a dedicated NOOP
794
        instruction. \\\hline
795
NOT Rx & XOR \$-1,Rx & \\\hline
796
POP Rx
797
        & \parbox[t]{1.5in}{LOD \$-1(SP),Rx \\ ADD \$1,SP}
798
        & Note
799
        that for interrupt purposes, one can never depend upon the value at
800
        (SP).  Hence you read from it, then increment it, lest having
801
        incremented it firost something then comes along and writes to that
802
        value before you can read the result. \\\hline
803
PUSH Rx
804
        & \parbox[t]{1.5in}{SUB \$1,SPa \\
805
        STO Rx,\$1(SP)}
806
        & \\\hline
807
RESET
808
        & \parbox[t]{1in}{STO \$1,\$watchdog(R12)\\NOOP\\NOOP}
809
        & \parbox[t]{3in}{This depends upon the peripheral base address being
810
        in R12.
811
 
812
        Another opportunity might be to jump to the reset address from within
813
        supervisor mode.}\\\hline
814 24 dgisselq
RET & \parbox[t]{1.5in}{LOD \$-1(SP),PC}
815
        & Note that this depends upon the calling context to clean up the
816
        stack, as outlined for the JSR instruction.  \\\hline
817 21 dgisselq
\end{tabular}
818
\caption{Derived Instructions, continued}\label{tbl:derived-2}
819
\end{center}\end{table}
820
\begin{table}\begin{center}
821
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
822
RET & MOV R12,PC
823
        & This is the high(er) speed version, that doesn't touch the stack.
824
        As such, it doesn't suffer a stall on memory read/write to the stack.
825
        \\\hline
826
STEP Rr,Rt
827
        & \parbox[t]{1.5in}{LSR \$1,Rr \\ XOR.C Rt,Rr}
828
        & Step a Galois implementation of a Linear Feedback Shift Register, Rr,
829
                using taps Rt \\\hline
830
STO.b Rx,\$addr
831
        & \parbox[t]{1.5in}{%
832
        LDI \$addr,Ra \\
833
        LDI \$addr,Rb \\
834
        LSR \$2,Ra \\
835
        AND \$3,Rb \\
836
        SUB \$32,Rb \\
837
        LOD (Ra),Ry \\
838
        AND \$0ffh,Rx \\
839
        AND \$-0ffh,Ry \\
840
        ROL Rb,Rx \\
841
        OR Rx,Ry \\
842
        STO Ry,(Ra) }
843
        & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized
844
        for byte-wise operations.
845
 
846
        Note that in this example, \$addr is a
847
        byte-wise address, whereas in all of our other examples it is a
848
        32-bit word address. This also limits the address space
849
        of character accesses from 16 MB down to 4MB.F
850
        Further, this instruction implies a byte ordering,
851
        such as big or little endian.} \\\hline
852
SWAP Rx,Ry
853
        & \parbox[t]{1.5in}{
854
        XOR Ry,Rx \\
855
        XOR Rx,Ry \\
856
        XOR Ry,Rx}
857
        & While no extra registers are needed, this example
858
        does take 3-clocks. \\\hline
859
TRAP \#X
860
        & LDILO \$x,CC
861
        & This approach uses the unused bits of the CC register as a TRAP
862 24 dgisselq
        address.  The user will need to make certain
863 21 dgisselq
        that the SLEEP and GIE bits are not set in \$x.  LDI would also work,
864
        however using LDILO permits the use of conditional traps.  (i.e.,
865
        trap if the zero flag is set.)  Should you wish to trap off of a
866
        register value, you could equivalently load \$x into the register and
867
        then MOV it into the CC register. \\\hline
868
TST Rx
869
        & TST \$-1,Rx
870
        & Set the condition codes based upon Rx.  Could also do a CMP \$0,Rx,
871
        ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc.  The TST and CMP
872
        approaches won't stall future pipeline stages looking for the value
873
        of Rx. \\\hline
874
WAIT
875
        & Or \$SLEEP,CC
876
        & Wait 'til interrupt.  In an interrupts disabled context, this
877
        becomes a HALT instruction.
878
\end{tabular}
879
\caption{Derived Instructions, continued}\label{tbl:derived-3}
880
\end{center}\end{table}
881
\iffalse
882
\fi
883
\section{Pipeline Stages}
884 32 dgisselq
As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},
885
the Zip CPU supports a five stage pipeline.
886 21 dgisselq
\begin{enumerate}
887
\item {\bf Prefetch}: Read instruction from memory (cache if possible).  This
888
        stage is actually pipelined itself, and so it will stall if the PC
889
        ever changes.  Stalls are also created here if the instruction isn't
890
        in the prefetch cache.
891
\item {\bf Decode}: Decode instruction into op code, register(s) to read, and
892 32 dgisselq
        immediate offset.  This stage also determines whether the flags will
893
        be set or whether the result will be written back.
894 21 dgisselq
\item {\bf Read Operands}: Read registers and apply any immediate values to
895 24 dgisselq
        them.  There is no means of detecting or flagging arithmetic overflow
896
        or carry when adding the immediate to the operand.  This stage will
897
        stall if any source operand is pending.
898 21 dgisselq
\item Split into two tracks: An {\bf ALU} which will accomplish a simple
899
        instruction, and the {\bf MemOps} stage which accomplishes memory
900
        read/write.
901
        \begin{itemize}
902
        \item Loads stall instructions that access the register until it is
903
                written to the register set.
904
        \item Condition codes are available upon completion
905
        \item Issuing an instruction to the memory while the memory is busy will
906 32 dgisselq
                stall the entire pipeline.  If the bus deadlocks, only a reset
907
                will release the CPU.  (Watchdog timer, anyone?)
908 24 dgisselq
        \item The Zip CPU currently has no means of reading and acting on any
909
        error conditions on the bus.
910 21 dgisselq
        \end{itemize}
911 32 dgisselq
\item {\bf Write-Back}: Conditionally write back the result to the register
912
        set, applying the condition.  This routine is bi-re-entrant: either the
913 21 dgisselq
        memory or the simple instruction may request a register write.
914
\end{enumerate}
915
 
916 24 dgisselq
The Zip CPU does not support out of order execution.  Therefore, if the memory
917
unit stalls, every other instruction stalls.  Memory stores, however, can take
918 32 dgisselq
place concurrently with ALU operations, although memory reads cannot.
919 24 dgisselq
 
920 21 dgisselq
\section{Pipeline Logic}
921
How the CPU handles some instruction combinations can be telling when
922
determining what happens in the pipeline.  The following lists some examples:
923
\begin{itemize}
924
\item {\bf Delayed Branching}
925
 
926
        I had originally hoped to implement delayed branching.  However, what
927
        happens in debug mode?
928
        That is, what happens when a debugger tries to single step an
929
        instruction?  While I can easily single step the computer in either
930
        user or supervisor mode from externally, this processor does not appear
931
        able to step the CPU in user mode from within user mode--gosh, not even
932
        from within supervisor mode--such as if a process had a debugger
933
        attached.  As the processor exists, I would have one result stepping
934
        the CPU from a debugger, and another stepping it externally.
935
 
936
        This is unacceptable, and so this CPU does not support delayed
937
        branching.
938
 
939
\item {\bf Register Result:} {\tt MOV R0,R1; MOV R1,R2 }
940
 
941
        What value does
942
        R2 get, the value of R1 before the first move or the value of R0?
943
        Placing the value of R0 into R1 requires a pipeline stall, and possibly
944
        two, as I have the pipeline designed.
945
 
946
        The ZIP CPU architecture requires that R2 must equal R0 at the end of
947 32 dgisselq
        this operation.  Even better, such combinations do not (normally)
948
        stall the pipeline.
949 21 dgisselq
 
950
\item {\bf Condition Codes Result:} {\tt CMP R0,R1;Mov.EQ \$x,PC}
951
 
952
 
953
        At issue is the same item as above, save that the CMP instruction
954
        updates the flags that the MOV instruction depends
955
        upon.
956
 
957
        The Zip CPU architecture requires that condition codes must be updated
958
        and available immediately for the next instruction without stalling the
959
        pipeline.
960
 
961
\item {\bf Condition Codes Register Result:} {\tt CMP R0,R1; MOV CC,R2}
962
 
963
        At issue is the
964
        fact that the logic supporting the CC register is more complicated than
965
        the logic supporting any other register.
966
 
967 32 dgisselq
        The ZIP CPU will stall for a cycle cycle on this instruction.
968 21 dgisselq
 
969
\item {\bf Delayed Branching: } {\tt ADD \$x,PC; MOV R0,R1}
970
 
971
        At issues is whether or not the instruction following the jump will
972
        take place before the jump.  In other words, is the MOV to the PC
973
        register handled differently from an ADD to the PC register?
974
 
975
        In the Zip architecture, MOV'es and ADD's use the same logic
976
        (simplifies the logic).
977
\end{itemize}
978
 
979
As I've studied  this, I find several approaches to handling pipeline
980
        issues.  These approaches (and their consequences) are listed below.
981
 
982
\begin{itemize}
983
\item {\bf All All issued instructions complete, Stages stall individually}
984
 
985
        What about a slow pre-fetch?
986
 
987
        Nominally, this works well: any issued instruction
988
        just runs to completion.  If there are four issued instructions in the
989
        pipeline, with the writeback instruction being a write-to-PC
990
        instruction, the other three instructions naturally finish.
991
 
992
        This approach fails when reading instructions from the flash,
993
        since such reads require N clocks to clocks to complete.  Thus
994
        there may be only one instruction in the pipeline if reading from flash,
995
        or a full pipeline if reading from cache.  Each of these approaches
996
        would produce a different response.
997
 
998
\item {\bf Issued instructions may be canceled}
999
 
1000
        Stages stall individually
1001
 
1002
        First problem:
1003
        Memory operations cannot be canceled, even reads may have side effects
1004
        on peripherals that cannot be canceled later.  Further, in the case of
1005
        an interrupt, it's difficult to know what to cancel.  What happens in
1006
        a \hbox{\tt MOV.C \$x,PC} followed by a \hbox{\tt MOV \$y,PC}
1007
        instruction?  Which get
1008
        canceled?
1009
 
1010
        Because it isn't clear what would need to be canceled,
1011
        this instruction combination is not recommended.
1012
 
1013
\item {\bf All issued instructions complete.}
1014
 
1015 32 dgisselq
        All stages are filled, or the entire pipeline stalls.
1016 21 dgisselq
 
1017
        What about debug control?  What about
1018
        register writes taking an extra clock stage?  MOV R0,R1; MOV R1,R2
1019
        should place the value of R0 into R2.  How do you restart the pipeline
1020
        after an interrupt?  What address do you use?  The last issued
1021
        instruction?  But the branch delay slots may make that invalid!
1022
 
1023
        Reading from the CPU debug port in this case yields inconsistent
1024
        results: the CPU will halt or step with instructions stuck in the
1025
        pipeline.  Reading registers will give no indication of what is going
1026
        on in the pipeline, just the results of completed operations, not of
1027
        operations that have been started and not yet completed.
1028
        Perhaps we should just report the state of the CPU based upon what
1029
        instructions (PC values) have successfully completed?  Thus the
1030
        debug instruction is the one that will write registers on the next
1031
        clock.
1032
 
1033
        Suggestion: Suppose we load extra information in the two
1034
        CC register(s) for debugging intermediate pipeline stages?
1035
 
1036
        The next problem, though, is how to deal with the read operand
1037 32 dgisselq
        pipeline stage needing the result from the register pipeline.
1038 21 dgisselq
 
1039
\item {\bf Memory instructions must complete}
1040
 
1041 32 dgisselq
        All instructions that enter into the memory module {\em must}
1042 21 dgisselq
        complete.  Issued instructions from the prefetch, decode, or operand
1043
        read stages may or may not complete.  Jumps into code must be valid,
1044
        so that interrupt returns may be valid.  All instructions entering the
1045
        ALU complete.
1046
 
1047
        This looks to be the simplest approach.
1048
        While the logic may be difficult, this appears to be the only
1049
        re-entrant approach.
1050
 
1051
        A {\tt new\_pc} flag will be high anytime the PC changes in an
1052
        unpredictable way (i.e., it doesn't increment).  This includes jumps
1053
        as well as interrupts and interrupt returns.  Whenever this flag may
1054
        go high, memory operations and ALU operations will stall until the
1055
        result is known.  When the flag does go high, anything in the prefetch,
1056
        decode, and read-op stage will be invalidated.
1057
 
1058
\end{itemize}
1059
 
1060 32 dgisselq
\section{Pipeline Stalls}
1061
The processing pipeline can and will stall for a variety of reasons.  Some of
1062
these are obvious, some less so.  These reasons are listed below:
1063
\begin{itemize}
1064
\item When the prefetch cache is exhausted
1065 21 dgisselq
 
1066 32 dgisselq
This should be obvious.  If the prefetch cache doesn't have the instruction
1067
in memory, the entire pipeline must stall until enough of the prefetch cache
1068
is loaded to support the next instruction.
1069 21 dgisselq
 
1070 32 dgisselq
\item While waiting for the pipeline to load following any taken branch, jump,
1071
        return from interrupt or switch to interrupt context (6 clocks)
1072
 
1073
If the PC suddenly changes, the pipeline is subsequently cleared and needs to
1074
be reloaded.  Given that there are five stages to the pipeline, that accounts
1075
for five of the six delay clocks.  The last clock is lost in the prefetch
1076
stage which needs at least one clock with a valid PC before it can produce
1077
a new output.  Hence, six clocks will always be lost anytime the pipeline needs
1078
to be cleared.
1079
 
1080
\item When reading from a prior register while also adding an immediate offset
1081
\begin{enumerate}
1082
\item\ {\tt OPCODE ?,RA}
1083
\item\ {\em (stall)}
1084
\item\ {\tt OPCODE I+RA,RB}
1085
\end{enumerate}
1086
 
1087
Since the addition of the immediate register within OpB decoding gets applied
1088
during the read operand stage so that it can be nicely settled before the ALU,
1089
any instruction that will write back an operand must be separated from the
1090
opcode that will read and apply an immediate offset by one instruction.  The
1091
good news is that this stall can easily be mitigated by proper scheduling.
1092
 
1093
\item When writing to the CC or PC Register
1094
\begin{enumerate}
1095
\item\ {\tt OPCODE RA,PC} {\em Ex: a branch opcode}
1096
\item\ {\em (stall, even if jump not taken)}
1097
\item\ {\tt OPCODE RA,RB}
1098
\end{enumerate}
1099
Since branches take place in the writeback stage, the Zip CPU will stall the
1100
pipeline for one clock anytime there may be a possible jump.  This prevents
1101
an instruction from executing a memory access after the jump but before the
1102
jump is recognized.
1103
 
1104
\item When reading from the CC register after setting the flags
1105
\begin{enumerate}
1106
\item\ {\tt ALUOP RA,RB}
1107
\item\ {\em (stall}
1108
\item\ {\tt TST sys.ccv,CC}
1109
\item\ {\tt BZ somewhere}
1110
\end{enumerate}
1111
 
1112
The reason for this stall is simply performance.  Many of the flags are
1113
determined via combinatorial logic after the writeback instruction is
1114
determined.  Trying to then place these into the input for one of the operands
1115
created a time delay loop that would no longer execute in a single 100~MHz
1116
clock cycle.  (The time delay of the multiply within the ALU wasn't helping
1117
either \ldots).
1118
 
1119
\item When waiting for a memory read operation to complete
1120
\begin{enumerate}
1121
\item\ {\tt LOD address,RA}
1122
\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
1123
\item\ {\tt OPCODE I+RA,RB}
1124
\end{enumerate}
1125
 
1126
Remember, the ZIP CPU does not support out of order execution.  Therefore,
1127
anytime the memory unit becomes busy both the memory unit and the ALU must
1128
stall until the memory unit is cleared.  This is especially true of a load
1129
instruction, which will write its operand back to the register file.  Store
1130
instructions are different, since they can be busy with no impact on later
1131
ALU write back operations.  Hence, only loads stall the pipeline.
1132
 
1133
This also assumes that the memory being accessed is a single cycle memory.
1134
Slower memories, such as the Quad SPI flash, will take longer--perhaps even
1135
as long as fourty clocks.   During this time the CPU and the external bus
1136
will be busy, and unable to do anything else.
1137
 
1138
\item Memory operation followed by a memory operation
1139
\begin{enumerate}
1140
\item\ {\tt STO address,RA}
1141
\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
1142
\item\ {\tt LOD address,RB}
1143
\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
1144
\end{enumerate}
1145
 
1146
In this case, the LOD instruction cannot start until the STALL is finished.
1147
With proper scheduling, it is possible to do something in the ALU while the
1148
STO is busy, but otherwise this pipeline will stall waiting for it to complete.
1149
 
1150
Note that even though the Wishbone bus can support pipelined accesses at
1151
one access per clock, only the prefetch stage can take advantage of this.
1152
Load and Store instructions are stuck at one wishbone cycle per instruction.
1153
\end{itemize}
1154
 
1155
 
1156 21 dgisselq
\chapter{Peripherals}\label{chap:periph}
1157 24 dgisselq
 
1158
While the previous chapter describes a CPU in isolation, the Zip System
1159
includes a minimum set of peripherals as well.  These peripherals are shown
1160
in Fig.~\ref{fig:zipsystem}
1161
\begin{figure}\begin{center}
1162
\includegraphics[width=3.5in]{../gfx/system.eps}
1163
\caption{Zip System Peripherals}\label{fig:zipsystem}
1164
\end{center}\end{figure}
1165
and described here.  They are designed to make
1166
the Zip CPU more useful in an Embedded Operating System environment.
1167
 
1168 21 dgisselq
\section{Interrupt Controller}
1169 24 dgisselq
 
1170
Perhaps the most important peripheral within the Zip System is the interrupt
1171
controller.  While the Zip CPU itself can only handle one interrupt, and has
1172
only the one interrupt state: disabled or enabled, the interrupt controller
1173
can make things more interesting.
1174
 
1175
The Zip System interrupt controller module supports up to 15 interrupts, all
1176
controlled from one register.  Bit~31 of the interrupt controller controls
1177
overall whether interrupts are enabled (1'b1) or disabled (1'b0).  Bits~16--30
1178
control whether individual interrupts are enabled (1'b0) or disabled (1'b0).
1179
Bit~15 is an indicator showing whether or not any interrupt is active, and
1180
bits~0--15 indicate whether or not an individual interrupt is active.
1181
 
1182
The interrupt controller has been designed so that bits can be controlled
1183
individually without having any knowledge of the rest of the controller
1184
setting.  To enable an interrupt, write to the register with the high order
1185
global enable bit set and the respective interrupt enable bit set.  No other
1186
bits will be affected.  To disable an interrupt, write to the register with
1187
the high order global enable bit cleared and the respective interrupt enable
1188
bit set.  To clear an interrupt, write a `1' to that interrupts status pin.
1189
Zero's written to the register have no affect, save that a zero written to the
1190
master enable will disable all interrupts.
1191
 
1192
As an example, suppose you wished to enable interrupt \#4.  You would then
1193
write to the register a {\tt 0x80100010} to enable interrupt \#4 and to clear
1194
any past active state.  When you later wish to disable this interrupt, you would
1195
write a {\tt 0x00100010} to the register.  As before, this both disables the
1196
interrupt and clears the active indicator.  This also has the side effect of
1197
disabling all interrupts, so a second write of {\tt 0x80000000} may be necessary
1198
to re-enable any other interrupts.
1199
 
1200
The Zip System currently hosts two interrupt controllers, a primary and a
1201
secondary.  The primary interrupt controller has one interrupt line which may
1202
come from an external interrupt controller, and one interrupt line from the
1203
secondary controller.  Other primary interrupts include the system timers,
1204
the jiffies interrupt, and the manual cache interrupt.  The secondary interrupt
1205
controller maintains an interrupt state for all of the processor accounting
1206
counters.
1207
 
1208 21 dgisselq
\section{Counter}
1209
 
1210
The Zip Counter is a very simple counter: it just counts.  It cannot be
1211
halted.  When it rolls over, it issues an interrupt.  Writing a value to the
1212
counter just sets the current value, and it starts counting again from that
1213
value.
1214
 
1215
Eight counters are implemented in the Zip System for process accounting.
1216
This may change in the future, as nothing as yet uses these counters.
1217
 
1218
\section{Timer}
1219
 
1220
The Zip Timer is also very simple: it simply counts down to zero.  When it
1221
transitions from a one to a zero it creates an interrupt.
1222
 
1223
Writing any non-zero value to the timer starts the timer.  If the high order
1224
bit is set when writing to the timer, the timer becomes an interval timer and
1225
reloads its last start time on any interrupt.  Hence, to mark seconds, one
1226
might set the timer to 100~million (the number of clocks per second), and
1227
set the high bit.  Ever after, the timer will interrupt the CPU once per
1228 24 dgisselq
second (assuming a 100~MHz clock).  This reload capability also limits the
1229
maximum timer value to $2^{31}-1$, rather than $2^{32}-1$.
1230 21 dgisselq
 
1231
\section{Watchdog Timer}
1232
 
1233
The watchdog timer is no different from any of the other timers, save for one
1234
critical difference: the interrupt line from the watchdog
1235
timer is tied to the reset line of the CPU.  Hence writing a `1' to the
1236
watchdog timer will always reset the CPU.
1237 32 dgisselq
To stop the Watchdog timer, write a `0' to it.  To start it,
1238 21 dgisselq
write any other number to it---as with the other timers.
1239
 
1240
While the watchdog timer supports interval mode, it doesn't make as much sense
1241
as it did with the other timers.
1242
 
1243
\section{Jiffies}
1244
 
1245
This peripheral is motivated by the Linux use of `jiffies' whereby a process
1246
can request to be put to sleep until a certain number of `jiffies' have
1247
elapsed.  Using this interface, the CPU can read the number of `jiffies'
1248
from the peripheral (it only has the one location in address space), add the
1249 24 dgisselq
sleep length to it, and write the result back to the peripheral.  The zipjiffies
1250 21 dgisselq
peripheral will record the value written to it only if it is nearer the current
1251
counter value than the last current waiting interrupt time.  If no other
1252
interrupts are waiting, and this time is in the future, it will be enabled.
1253
(There is currently no way to disable a jiffie interrupt once set, other
1254 24 dgisselq
than to disable the interrupt line in the interrupt controller.)  The processor
1255 21 dgisselq
may then place this sleep request into a list among other sleep requests.
1256
Once the timer expires, it would write the next Jiffy request to the peripheral
1257
and wake up the process whose timer had expired.
1258
 
1259
Indeed, the Jiffies register is nothing more than a glorified counter with
1260
an interrupt.  Unlike the other counters, the Jiffies register cannot be set.
1261
Writes to the jiffies register create an interrupt time.  When the Jiffies
1262
register later equals the value written to it, an interrupt will be asserted
1263
and the register then continues counting as though no interrupt had taken
1264
place.
1265
 
1266
The purpose of this register is to support alarm times within a CPU.  To
1267
set an alarm for a particular process $N$ clocks in advance, read the current
1268
Jiffies value, and $N$, and write it back to the Jiffies register.  The
1269
O/S must also keep track of values written to the Jiffies register.  Thus,
1270 32 dgisselq
when an `alarm' trips, it should be removed from the list of alarms, the list
1271 21 dgisselq
should be sorted, and the next alarm in terms of Jiffies should be written
1272
to the register.
1273
 
1274 24 dgisselq
\section{Manual Cache}
1275
 
1276
The manual cache is an experimental setting that may not remain with the Zip
1277
CPU for very long.  It is designed to facilitate running from FLASH or ROM
1278 32 dgisselq
memory, although the pipeline prefetch cache really makes this need obsolete.
1279
The manual
1280 24 dgisselq
cache works by copying data from a wishbone address (range) into the cache
1281
register, and then by making that memory available as memory to the Zip System.
1282
It is a {\em manual cache} because the processor must first specify what
1283
memory to copy, and then once copied the processor can only access the cache
1284
memory by the cache memory location.  There is no transparency.  It is perhaps
1285
best described as a combination DMA controller and local memory.
1286
 
1287
Worse, this cache is likely going to be removed from the ZipSystem.  Having used
1288
the ZipSystem now for some time, I have yet to find a need or use for the manual
1289
cache.  I will likely replace this peripheral with a proper DMA controller.
1290
 
1291 21 dgisselq
\chapter{Operation}\label{chap:ops}
1292
 
1293
\chapter{Registers}\label{chap:regs}
1294
 
1295 24 dgisselq
The ZipSystem registers fall into two categories, ZipSystem internal registers
1296
accessed via the ZipCPU shown in Tbl.~\ref{tbl:zpregs},
1297
\begin{table}[htbp]
1298
\begin{center}\begin{reglist}
1299 32 dgisselq
PIC   & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
1300
WDT   & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
1301
CCHE  & \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & Manual Cache Controller \\\hline
1302
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
1303
TMRA  & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
1304
TMRB  & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
1305
TMRC  & \scalebox{0.8}{\tt 0xc0000006} & 32 & R/W & Timer C\\\hline
1306
JIFF  & \scalebox{0.8}{\tt 0xc0000007} & 32 & R/W & Jiffies \\\hline
1307
MTASK  & \scalebox{0.8}{\tt 0xc0000008} & 32 & R/W & Master Task Clock Counter \\\hline
1308
MMSTL  & \scalebox{0.8}{\tt 0xc0000009} & 32 & R/W & Master Stall Counter \\\hline
1309
MPSTL  & \scalebox{0.8}{\tt 0xc000000a} & 32 & R/W & Master Pre--Fetch Stall Counter \\\hline
1310
MICNT  & \scalebox{0.8}{\tt 0xc000000b} & 32 & R/W & Master Instruction Counter\\\hline
1311
UTASK  & \scalebox{0.8}{\tt 0xc000000c} & 32 & R/W & User Task Clock Counter \\\hline
1312
UMSTL  & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
1313
UPSTL  & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
1314
UICNT  & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
1315
% Cache  & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
1316 24 dgisselq
\end{reglist}
1317
\caption{Zip System Internal/Peripheral Registers}\label{tbl:zpregs}
1318
\end{center}\end{table}
1319
and the two debug registers showin in Tbl.~\ref{tbl:dbgregs}.
1320
\begin{table}[htbp]
1321
\begin{center}\begin{reglist}
1322
ZIPCTRL & 0 & 32 & R/W & Debug Control Register \\\hline
1323
ZIPDATA & 1 & 32 & R/W & Debug Data Register \\\hline
1324
\end{reglist}
1325
\caption{Zip System Debug Registers}\label{tbl:dbgregs}
1326
\end{center}\end{table}
1327
 
1328
 
1329 21 dgisselq
\chapter{Wishbone Datasheet}\label{chap:wishbone}
1330 32 dgisselq
The Zip System supports two wishbone ports, a slave debug port and a master
1331 21 dgisselq
port for the system itself.  These are shown in Tbl.~\ref{tbl:wishbone-slave}
1332
\begin{table}[htbp]
1333
\begin{center}
1334
\begin{wishboneds}
1335
Revision level of wishbone & WB B4 spec \\\hline
1336
Type of interface & Slave, Read/Write, single words only \\\hline
1337 24 dgisselq
Address Width & 1--bit \\\hline
1338 21 dgisselq
Port size & 32--bit \\\hline
1339
Port granularity & 32--bit \\\hline
1340
Maximum Operand Size & 32--bit \\\hline
1341
Data transfer ordering & (Irrelevant) \\\hline
1342
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1343
Signal Names & \begin{tabular}{ll}
1344
                Signal Name & Wishbone Equivalent \\\hline
1345
                {\tt i\_clk} & {\tt CLK\_I} \\
1346
                {\tt i\_dbg\_cyc} & {\tt CYC\_I} \\
1347
                {\tt i\_dbg\_stb} & {\tt STB\_I} \\
1348
                {\tt i\_dbg\_we} & {\tt WE\_I} \\
1349
                {\tt i\_dbg\_addr} & {\tt ADR\_I} \\
1350
                {\tt i\_dbg\_data} & {\tt DAT\_I} \\
1351
                {\tt o\_dbg\_ack} & {\tt ACK\_O} \\
1352
                {\tt o\_dbg\_stall} & {\tt STALL\_O} \\
1353
                {\tt o\_dbg\_data} & {\tt DAT\_O}
1354
                \end{tabular}\\\hline
1355
\end{wishboneds}
1356 22 dgisselq
\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
1357 21 dgisselq
\end{center}\end{table}
1358
and Tbl.~\ref{tbl:wishbone-master} respectively.
1359
\begin{table}[htbp]
1360
\begin{center}
1361
\begin{wishboneds}
1362
Revision level of wishbone & WB B4 spec \\\hline
1363 24 dgisselq
Type of interface & Master, Read/Write, single cycle or pipelined\\\hline
1364
Address Width & 32--bit bits \\\hline
1365 21 dgisselq
Port size & 32--bit \\\hline
1366
Port granularity & 32--bit \\\hline
1367
Maximum Operand Size & 32--bit \\\hline
1368
Data transfer ordering & (Irrelevant) \\\hline
1369
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1370
Signal Names & \begin{tabular}{ll}
1371
                Signal Name & Wishbone Equivalent \\\hline
1372
                {\tt i\_clk} & {\tt CLK\_O} \\
1373
                {\tt o\_wb\_cyc} & {\tt CYC\_O} \\
1374
                {\tt o\_wb\_stb} & {\tt STB\_O} \\
1375
                {\tt o\_wb\_we} & {\tt WE\_O} \\
1376
                {\tt o\_wb\_addr} & {\tt ADR\_O} \\
1377
                {\tt o\_wb\_data} & {\tt DAT\_O} \\
1378
                {\tt i\_wb\_ack} & {\tt ACK\_I} \\
1379
                {\tt i\_wb\_stall} & {\tt STALL\_I} \\
1380
                {\tt i\_wb\_data} & {\tt DAT\_I}
1381
                \end{tabular}\\\hline
1382
\end{wishboneds}
1383 22 dgisselq
\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
1384 21 dgisselq
\end{center}\end{table}
1385
I do not recommend that you connect these together through the interconnect.
1386 24 dgisselq
Rather, the debug port of the CPU should be accessible regardless of the state
1387
of the master bus.
1388 21 dgisselq
 
1389 24 dgisselq
You may wish to notice that neither the {\tt ERR} nor the {\tt RETRY} wires
1390
have been implemented.  What this means is that the CPU is currently unable
1391
to detect a bus error condition, and so may stall indefinitely (hang) should
1392
it choose to access a value not on the bus, or a peripheral that is not
1393
yet properly configured.
1394 21 dgisselq
 
1395
\chapter{Clocks}\label{chap:clocks}
1396
 
1397 32 dgisselq
This core is based upon the Basys--3 development board sold by Digilent.
1398
The Basys--3 development board contains one external 100~MHz clock, which is
1399
sufficient to run the ZIP CPU core.
1400 21 dgisselq
\begin{table}[htbp]
1401
\begin{center}
1402
\begin{clocklist}
1403
i\_clk & External & 100~MHz & 100~MHz & System clock.\\\hline
1404
\end{clocklist}
1405
\caption{List of Clocks}\label{tbl:clocks}
1406
\end{center}\end{table}
1407
I hesitate to suggest that the core can run faster than 100~MHz, since I have
1408
had struggled with various timing violations to keep it at 100~MHz.  So, for
1409
now, I will only state that it can run at 100~MHz.
1410
 
1411
 
1412
\chapter{I/O Ports}\label{chap:ioports}
1413
 
1414
% Appendices
1415
% Index
1416
\end{document}
1417
 
1418
 

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