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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename:    spec.tex
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%%
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%% Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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%%
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%% Purpose:     This LaTeX file contains all of the documentation/description
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%%              currently provided with this Zip CPU soft core.  It supersedes
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%%              any information about the instruction set or CPUs found
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%%              elsewhere.  It's not nearly as interesting, though, as the PDF
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%%              file it creates, so I'd recommend reading that before diving
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%%              into this file.  You should be able to find the PDF file in
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%%              the SVN distribution together with this PDF file and a copy of
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%%              the GPL-3.0 license this file is distributed under.  If not,
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%%              just type 'make' in the doc directory and it (should) build
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%%              without a problem.
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%%
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%%
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%% Creator:     Dan Gisselquist
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%%              Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of  the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program.  (It's in the $(ROOT)/doc directory, run make with no 38 %% target there if the PDF file isn't present.) If not, see 39 %% <http://www.gnu.org/licenses/> for a copy. 40 %% 41 %% License: GPL, v3, as defined and found on www.gnu.org, 42 %% http://www.gnu.org/licenses/gpl.html 43 %% 44 %% 45 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 46 \documentclass{gqtekspec} 47 \project{Zip CPU} 48 \title{Specification} 49 \author{Dan Gisselquist, Ph.D.} 50 \email{dgisselq (at) opencores.org} 51 36 dgisselq \revision{Rev.~0.4} 52 \definecolor{webred}{rgb}{0.2,0,0} 53 \definecolor{webgreen}{rgb}{0,0.2,0} 54 \usepackage[dvips,ps2pdf,colorlinks=true, 55  anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames, 56  pdfauthor={Dan Gisselquist}, 57  pdfsubject={Zip CPU}]{hyperref} 58 21 dgisselq \begin{document} 59 \pagestyle{gqtekspecplain} 60 \titlepage 61 \begin{license} 62 Copyright (C) \theyear\today, Gisselquist Technology, LLC 63   64 This project is free software (firmware): you can redistribute it and/or 65 modify it under the terms of the GNU General Public License as published 66 by the Free Software Foundation, either version 3 of the License, or (at 67 your option) any later version. 68   69 This program is distributed in the hope that it will be useful, but WITHOUT 70 ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or 71 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 72 for more details. 73   74 You should have received a copy of the GNU General Public License along 75 with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a 76 copy. 77 \end{license} 78 \begin{revisionhistory} 79 36 dgisselq 0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline 80 33 dgisselq 0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline 81 24 dgisselq 0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline 82 21 dgisselq 0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline 83 \end{revisionhistory} 84 % Revision History 85 % Table of Contents, named Contents 86 \tableofcontents 87 24 dgisselq \listoffigures 88 21 dgisselq \listoftables 89 \begin{preface} 90 Many people have asked me why I am building the Zip CPU. ARM processors are 91 good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both 92 have better toolsets than the Zip CPU will ever have. OpenRISC is also 93 24 dgisselq available, RISC--V may be replacing it. Why build a new processor? 94 21 dgisselq   95 The easiest, most obvious answer is the simple one: Because I can. 96   97 There's more to it, though. There's a lot that I would like to do with a 98 processor, and I want to be able to do it in a vendor independent fashion. 99 36 dgisselq First, I would like to be able to place this processor inside an FPGA. Without 100 paying royalties, ARM is out of the question. I would then like to be able to 101 generate Verilog code, both for the processor and the system it sits within, 102 that can run equivalently on both Xilinx and Altera chips, and that can be 103 easily ported from one manufacturer's chipsets to another. Even more, before 104 purchasing a chip or a board, I would like to know that my soft core works. I 105 would like to build a test bench to test components with, and Verilator is my 106 chosen test bench. This forces me to use all Verilog, and it prevents me from 107 using any proprietary cores. For this reason, Microblaze and Nios are out of 108 the question. 109 21 dgisselq   110 Why not OpenRISC? That's a hard question. The OpenRISC team has done some 111 wonderful work on an amazing processor, and I'll have to admit that I am 112 envious of what they've accomplished. I would like to port binutils to the 113 Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The 114 OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has 115 a lot of features of modern CPUs within it that ... well, let's just say it's 116 not the little guy on the block. The Zip CPU is lighter weight, costing only 117 32 dgisselq about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic 118 21 dgisselq peripherals. 119   120 My final reason is that I'm building the Zip CPU as a learning experience. The 121 Zip CPU has allowed me to learn a lot about how CPUs work on a very micro 122 level. For the first time, I am beginning to understand many of the Computer 123 Architecture lessons from years ago. 124   125 To summarize: Because I can, because it is open source, because it is light 126 weight, and as an exercise in learning. 127   128 \end{preface} 129   130 \chapter{Introduction} 131 \pagenumbering{arabic} 132 \setcounter{page}{1} 133   134   135 36 dgisselq The original goal of the Zip CPU was to be a very simple CPU. You might 136 21 dgisselq think of it as a poor man's alternative to the OpenRISC architecture. 137 For this reason, all instructions have been designed to be as simple as 138 possible, and are all designed to be executed in one instruction cycle per 139 instruction, barring pipeline stalls. Indeed, even the bus has been simplified 140 to a constant 32-bit width, with no option for more or less. This has 141 resulted in the choice to drop push and pop instructions, pre-increment and 142 post-decrement addressing modes, and more. 143   144 For those who like buzz words, the Zip CPU is: 145 \begin{itemize} 146 \item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits, 147  instructions are 32-bits wide, etc. 148 24 dgisselq \item A RISC CPU. There is no microcode for executing instructions. All 149  instructions are designed to be completed in one clock cycle. 150 21 dgisselq \item A Load/Store architecture. (Only load and store instructions 151  can access memory.) 152 \item Wishbone compliant. All peripherals are accessed just like 153  memory across this bus. 154 \item A Von-Neumann architecture. (The instructions and data share a 155  common bus.) 156 \item A pipelined architecture, having stages for {\bf Prefetch}, 157  {\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory} 158 24 dgisselq  unit, and {\bf Write-back}. See Fig.~\ref{fig:cpu} 159 \begin{figure}\begin{center} 160 \includegraphics[width=3.5in]{../gfx/cpu.eps} 161 \caption{Zip CPU internal pipeline architecture}\label{fig:cpu} 162 \end{center}\end{figure} 163  for a diagram of this structure. 164 21 dgisselq \item Completely open source, licensed under the GPL.\footnote{Should you 165  need a copy of the Zip CPU licensed under other terms, please 166  contact me.} 167 \end{itemize} 168   169 Now, however, that I've worked on the Zip CPU for a while, it is not nearly 170 as simple as I originally hoped. Worse, I've had to adjust to create 171 capabilities that I was never expecting to need. These include: 172 \begin{itemize} 173 33 dgisselq \item {\bf External Debug:} Once placed upon an FPGA, some external means is 174 21 dgisselq  still necessary to debug this CPU. That means that there needs to be 175  an external register that can control the CPU: reset it, halt it, step 176 24 dgisselq  it, and tell whether it is running or not. My chosen interface 177  includes a second register similar to this control register. This 178  second register allows the external controller or debugger to examine 179 21 dgisselq  registers internal to the CPU. 180   181 \item {\bf Internal Debug:} Being able to run a debugger from within 182  a user process requires an ability to step a user process from 183  within a debugger. It also requires a break instruction that can 184  be substituted for any other instruction, and substituted back. 185  The break is actually difficult: the break instruction cannot be 186  allowed to execute. That way, upon a break, the debugger should 187  be able to jump back into the user process to step the instruction 188  that would've been at the break point initially, and then to 189  replace the break after passing it. 190   191 24 dgisselq  Incidentally, this break messes with the prefetch cache and the 192  pipeline: if you change an instruction partially through the pipeline, 193  the whole pipeline needs to be cleansed. Likewise if you change 194  an instruction in memory, you need to make sure the cache is reloaded 195  with the new instruction. 196   197 21 dgisselq \item {\bf Prefetch Cache:} My original implementation had a very 198  simple prefetch stage. Any time the PC changed the prefetch would go 199  and fetch the new instruction. While this was perhaps this simplest 200  approach, it cost roughly five clocks for every instruction. This 201  was deemed unacceptable, as I wanted a CPU that could execute 202  instructions in one cycle. I therefore have a prefetch cache that 203  issues pipelined wishbone accesses to memory and then pushes 204  instructions at the CPU. Sadly, this accounts for about 20\% of the 205  logic in the entire CPU, or 15\% of the logic in the entire system. 206   207   208 \item {\bf Operating System:} In order to support an operating system, 209  interrupts and so forth, the CPU needs to support supervisor and 210  user modes, as well as a means of switching between them. For example, 211  the user needs a means of executing a system call. This is the 212  purpose of the {\bf trap'} instruction. This instruction needs to 213  place the CPU into supervisor mode (here equivalent to disabling 214  interrupts), as well as handing it a parameter such as identifying 215  which O/S function was called. 216   217 24 dgisselq My initial approach to building a trap instruction was to create an external 218 peripheral which, when written to, would generate an interrupt and could 219 return the last value written to it. In practice, this approach didn't work 220 at all: the CPU executed two instructions while waiting for the 221 trap interrupt to take place. Since then, I've decided to keep the rest of 222 the CC register for that purpose so that a write to the CC register, with the 223 GIE bit cleared, could be used to execute a trap. This has other problems, 224 though, primarily in the limitation of the uses of the CC register. In 225 particular, the CC register is the best place to put CPU state information and 226 to announce'' special CPU features (floating point, etc). So the trap 227 instruction still switches to interrupt mode, but the CC register is not 228 nearly as useful for telling the supervisor mode processor what trap is being 229 executed. 230 21 dgisselq   231 Modern timesharing systems also depend upon a {\bf Timer} interrupt 232 24 dgisselq to handle task swapping. For the Zip CPU, this interrupt is handled 233 external to the CPU as part of the CPU System, found in {\tt zipsystem.v}. 234 The timer module itself is found in {\tt ziptimer.v}. 235 21 dgisselq   236 \item {\bf Pipeline Stalls:} My original plan was to not support pipeline 237  stalls at all, but rather to require the compiler to properly schedule 238 24 dgisselq  all instructions so that stalls would never be necessary. After trying 239 21 dgisselq  to build such an architecture, I gave up, having learned some things: 240   241  For example, in order to facilitate interrupt handling and debug 242  stepping, the CPU needs to know what instructions have finished, and 243  which have not. In other words, it needs to know where it can restart 244  the pipeline from. Once restarted, it must act as though it had 245 24 dgisselq  never stopped. This killed my idea of delayed branching, since what 246  would be the appropriate program counter to restart at? The one the 247  CPU was going to branch to, or the ones in the delay slots? This 248  also makes the idea of compressed instruction codes difficult, since, 249  again, where do you restart on interrupt? 250 21 dgisselq   251  So I switched to a model of discrete execution: Once an instruction 252  enters into either the ALU or memory unit, the instruction is 253  guaranteed to complete. If the logic recognizes a branch or a 254  condition that would render the instruction entering into this stage 255 33 dgisselq  possibly inappropriate (i.e. a conditional branch preceding a store 256 21 dgisselq  instruction for example), then the pipeline stalls for one cycle 257  until the conditional branch completes. Then, if it generates a new 258 33 dgisselq  PC address, the stages preceding are all wiped clean. 259 21 dgisselq   260  The discrete execution model allows such things as sleeping: if the 261 24 dgisselq  CPU is put to sleep,'' the ALU and memory stages stall and back up 262 21 dgisselq  everything before them. Likewise, anything that has entered the ALU 263  or memory stage when the CPU is placed to sleep continues to completion. 264  To handle this logic, each pipeline stage has three control signals: 265  a valid signal, a stall signal, and a clock enable signal. In 266  general, a stage stalls if it's contents are valid and the next step 267  is stalled. This allows the pipeline to fill any time a later stage 268  stalls. 269   270 24 dgisselq  This approach is also different from other pipeline approaches. Instead 271  of keeping the entire pipeline filled, each stage is treated 272  independently. Therefore, individual stages may move forward as long 273  as the subsequent stage is available, regardless of whether the stage 274  behind it is filled. 275   276 21 dgisselq \item {\bf Verilog Modules:} When examining how other processors worked 277  here on open cores, many of them had one separate module per pipeline 278  stage. While this appeared to me to be a fascinating and commendable 279  idea, my own implementation didn't work out quite so nicely. 280   281  As an example, the decode module produces a {\em lot} of 282  control wires and registers. Creating a module out of this, with 283  only the simplest of logic within it, seemed to be more a lesson 284  in passing wires around, rather than encapsulating logic. 285   286  Another example was the register writeback section. I would love 287  this section to be a module in its own right, and many have made them 288  such. However, other modules depend upon writeback results other 289  than just what's placed in the register (i.e., the control wires). 290  For these reasons, I didn't manage to fit this section into it's 291  own module. 292   293  The result is that the majority of the CPU code can be found in 294  the {\tt zipcpu.v} file. 295 \end{itemize} 296   297 With that introduction out of the way, let's move on to the instruction 298 set. 299   300 \chapter{CPU Architecture}\label{chap:arch} 301   302 24 dgisselq The Zip CPU supports a set of two operand instructions, where the second operand 303 21 dgisselq (always a register) is the result. The only exception is the store instruction, 304 where the first operand (always a register) is the source of the data to be 305 stored. 306   307 24 dgisselq \section{Simplified Bus} 308 The bus architecture of the Zip CPU is that of a simplified WISHBONE bus. 309 It has been simplified in this fashion: all operations are 32--bit operations. 310 36 dgisselq The bus is neither little endian nor big endian. For this reason, all words 311 24 dgisselq are 32--bits. All instructions are also 32--bits wide. Everything has been 312 built around the 32--bit word. 313   314 21 dgisselq \section{Register Set} 315 The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor 316 24 dgisselq and a user set as shown in Fig.~\ref{fig:regset}. 317 \begin{figure}\begin{center} 318 \includegraphics[width=3.5in]{../gfx/regset.eps} 319 \caption{Zip CPU Register File}\label{fig:regset} 320 \end{center}\end{figure} 321 The supervisor set is used in interrupt mode when interrupts are disabled, 322 whereas the user set is used otherwise. Of this register set, the Program 323 Counter (PC) is register 15, whereas the status register (SR) or condition 324 code register 325 21 dgisselq (CC) is register 14. By convention, the stack pointer will be register 13 and 326 24 dgisselq noted as (SP)--although there is nothing special about this register other 327 than this convention. 328 21 dgisselq The CPU can access both register sets via move instructions from the 329 supervisor state, whereas the user state can only access the user registers. 330   331 36 dgisselq The status register is special, and bears further mention. As shown in 332 Fig.~\ref{tbl:cc-register}, 333 \begin{table}\begin{center} 334 \begin{bitlist} 335 31\ldots 11 & R/W & Reserved for future uses\\\hline 336 10 & R & (Reserved for) Bus-Error Flag\\\hline 337 9 & R & Trap, or user interrupt, Flag. Cleared on return to userspace.\\\hline 338 8 & R & (Reserved for) Illegal Instruction Flag\\\hline 339 7 & R/W & Break--Enable\\\hline 340 6 & R/W & Step\\\hline 341 5 & R/W & Global Interrupt Enable (GIE)\\\hline 342 4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline 343 3 & R/W & Overflow\\\hline 344 2 & R/W & Negative. The sign bit was set as a result of the last ALU instruction.\\\hline 345 1 & R/W & Carry\\\hline 346   347 \end{bitlist} 348 \caption{Condition Code Register Bit Assignment}\label{tbl:cc-register} 349 \end{center}\end{table} 350 the lower 11~bits of the status register form 351 a set of CPU state and condition codes. Writes to other bits of this register 352 are preserved. 353 21 dgisselq   354 33 dgisselq Of the condition codes, the bottom four bits are the current flags: 355 21 dgisselq  Zero (Z), 356  Carry (C), 357  Negative (N), 358  and Overflow (V). 359   360 The next bit is a clock enable (0 to enable) or sleep bit (1 to put 361  the CPU to sleep). Setting this bit will cause the CPU to 362  wait for an interrupt (if interrupts are enabled), or to 363  completely halt (if interrupts are disabled). 364 33 dgisselq   365 21 dgisselq The sixth bit is a global interrupt enable bit (GIE). When this 366 32 dgisselq  sixth bit is a 1' interrupts will be enabled, else disabled. When 367 21 dgisselq  interrupts are disabled, the CPU will be in supervisor mode, otherwise 368  it is in user mode. Thus, to execute a context switch, one only 369  need enable or disable interrupts. (When an interrupt line goes 370  high, interrupts will automatically be disabled, as the CPU goes 371 32 dgisselq  and deals with its context switch.) Special logic has been added to 372  keep the user mode from setting the sleep register and clearing the 373  GIE register at the same time, with clearing the GIE register taking 374  precedence. 375 21 dgisselq   376 The seventh bit is a step bit. This bit can be 377  set from supervisor mode only. After setting this bit, should 378  the supervisor mode process switch to user mode, it would then 379  accomplish one instruction in user mode before returning to supervisor 380  mode. Then, upon return to supervisor mode, this bit will 381  be automatically cleared. This bit has no effect on the CPU while in 382  supervisor mode. 383   384  This functionality was added to enable a userspace debugger 385  functionality on a user process, working through supervisor mode 386  of course. 387   388   389 24 dgisselq The eighth bit is a break enable bit. This controls whether a break 390 instruction in user mode will halt the processor for an external debugger 391 (break enabled), or whether the break instruction will simply send send the 392 CPU into interrupt mode. Encountering a break in supervisor mode will 393 halt the CPU independent of the break enable bit. This bit can only be set 394 within supervisor mode. 395 21 dgisselq   396 32 dgisselq % Should break enable be a supervisor mode bit, while the break enable bit 397 % in user mode is a break has taken place bit? 398 % 399   400 21 dgisselq This functionality was added to enable an external debugger to 401  set and manage breakpoints. 402   403 36 dgisselq The ninth bit is reserved for an illegal instruction bit. When the CPU 404 tries to execute either a non-existant instruction, or an instruction from 405 an address that produces a bus error, the CPU will (once implemented) switch 406 to supervisor mode while setting this bit. The bit will automatically be 407 cleared upon any return to user mode. 408 21 dgisselq   409 The tenth bit is a trap bit. It is set whenever the user requests a soft 410 interrupt, and cleared on any return to userspace command. This allows the 411 supervisor, in supervisor mode, to determine whether it got to supervisor 412 mode from a trap or from an external interrupt or both. 413   414 \section{Conditional Instructions} 415 36 dgisselq Most, although not quite all, instructions may be conditionally executed. From 416 21 dgisselq the four condition code flags, eight conditions are defined. These are shown 417 in Tbl.~\ref{tbl:conditions}. 418 \begin{table} 419 \begin{center} 420 \begin{tabular}{l|l|l} 421 Code & Mneumonic & Condition \\\hline 422 3'h0 & None & Always execute the instruction \\ 423 3'h1 & {\tt .Z} & Only execute when 'Z' is set \\ 424 3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\ 425 3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\ 426 3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\ 427 24 dgisselq 3'h5 & {\tt .LT} & Less than ('N' set) \\ 428 21 dgisselq 3'h6 & {\tt .C} & Carry set\\ 429 3'h7 & {\tt .V} & Overflow set\\ 430 \end{tabular} 431 \caption{Conditions for conditional operand execution}\label{tbl:conditions} 432 \end{center} 433 \end{table} 434 24 dgisselq There is no condition code for less than or equal, not C or not V. Sorry, 435 36 dgisselq I ran out of space in 3--bits. Conditioning on a non--supported condition 436 is still possible, but it will take an extra instruction and a pipeline stall. (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
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Conditionally executed ALU instructions will not further adjust the
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condition codes.
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\section{Operand B}
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Many instruction forms have a 21-bit source Operand B'' associated with them.
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This Operand B is either equal to a register plus a signed immediate offset,
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or an immediate offset by itself.  This value is encoded as shown in
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Tbl.~\ref{tbl:opb}.
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\begin{table}\begin{center}
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\begin{tabular}{|l|l|l|}\hline
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Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline
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1'b0 & \multicolumn{2}{l|}{20--bit Signed Immediate value} \\\hline
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1'b1 & 4-bit Register & 16--bit Signed immediate offset \\\hline
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\end{tabular}
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\caption{Bit allocation for Operand B}\label{tbl:opb}
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\end{center}\end{table}
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Sixteen and twenty bit immediate values don't make sense for all instructions.
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For example, what is the point of a 20--bit immediate when executing a 16--bit
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multiply?  Likewise, why have a 16--bit immediate when adding to a logical
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or arithmetic shift?  In these cases, the extra bits are reserved for future
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instruction possibilities.
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\section{Address Modes}
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The Zip CPU supports two addressing modes: register plus immediate, and
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immediate address.  Addresses are therefore encoded in the same fashion as
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Operand B's, shown above.
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A lot of long hard thought was put into whether to allow pre/post increment
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and decrement addressing modes.  Finding no way to use these operators without
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taking two or more clocks per instruction,\footnote{The two clocks figure
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comes from the design of the register set, allowing only one write per clock.
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That write is either from the memory unit or the ALU, but never both.} these
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addressing modes have been
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removed from the realm of possibilities.  This means that the Zip CPU has no
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native way of executing push, pop, return, or jump to subroutine operations.
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Each of these instructions can be emulated with a set of instructions from the
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existing set.
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477
\section{Move Operands}
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The previous set of operands would be perfect and complete, save only that
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the CPU needs access to non--supervisory registers while in supervisory mode.
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Therefore, the MOV instruction is special and offers access to these registers
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\ldots when in supervisory mode.  To keep the compiler simple, the extra bits
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are ignored in non-supervisory mode (as though they didn't exist), rather than
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being mapped to new instructions or additional capabilities.  The bits
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indicating which register set each register lies within are the A-Usr and
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B-Usr bits.  When set to a one, these refer to a user mode register.  When set
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to a zero, these refer to a register in the current mode, whether user or
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supervisor.  Further, because a load immediate instruction exists, there is no
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move capability between an immediate and a register: all moves come from either
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a register or a register plus an offset.
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This actually leads to a bit of a problem: since the MOV instruction encodes
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which register set each register is coming from or moving to, how shall a
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compiler or assembler know how to compile a MOV instruction without knowing
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the mode of the CPU at the time?  For this reason, the compiler will assume
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all MOV registers are supervisor registers, and display them as normal.
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Anything with the user bit set will be treated as a user register.  The CPU
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will quietly ignore the supervisor bits while in user mode, and anything
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marked as a user register will always be valid.
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500
\section{Multiply Operations}
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The Zip CPU supports two Multiply operations, a 16x16 bit signed multiply
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({\tt MPYS}) and a 16x16 bit unsigned multiply ({\tt MPYU}).  In both
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cases, the operand is a register plus a 16-bit immediate, subject to the
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rule that the register cannot be the PC or CC registers.  The PC register
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field has been stolen to create a multiply by immediate instruction.  The
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CC register field is reserved.
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\section{Floating Point}
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The Zip CPU does not (yet) support floating point operations.  However, the
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instruction set reserves two possibilities for future floating point
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operations.
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The first floating point operation hole in the instruction set involves
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setting a proposed (but non-existent) floating point bit in the CC register.
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The next instruction
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would then simply interpret its operands as floating point instructions.
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Not all instructions, however, have floating point equivalents.  Further, the
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immediate fields do not apply in floating point mode, and must be set to
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zero.  Not all instructions make sense as floating point operations.
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Therefore, only the CMP, SUB, ADD, and MPY instructions may be issued as
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floating point instructions.  Other instructions allow the examining of the
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floating point bit in the CC register.  In all cases, the floating point bit
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is cleared one instruction after it is set.
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The other possibility for floating point operations involves exploiting the
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hole in the instruction set that the NOOP and BREAK instructions reside within.
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These two instructions use 24--bits of address space, when only a single bit
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is necessary.  A simple adjustment to this space could create instructions
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with 4--bit register addresses for each register, a 3--bit field for
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conditional execution, and a 2--bit field for which operation.
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In this fashion, such a floating point capability would only fill 13--bits of
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the 24--bit field, still leaving lots of room for expansion.
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In both cases, the Zip CPU would support 32--bit single precision floats
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only, since other choices would complicate the pipeline.
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537
The current architecture does not support a floating point not-implemented
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interrupt.  Any soft floating point emulation must be done deliberately.
539
 
540 21 dgisselq
\section{Native Instructions}
541
The instruction set for the Zip CPU is summarized in
542
Tbl.~\ref{tbl:zip-instructions}.
543
\begin{table}\begin{center}
544
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline
545 36 dgisselq
\rowcolor[gray]{0.85}
546 21 dgisselq
Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}
547
        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}
548 36 dgisselq
        & Sets CC? \\\hline\hline
549 21 dgisselq
CMP(Sub) & \multicolumn{4}{l|}{4'h0}
550
                & \multicolumn{4}{l|}{D. Reg}
551
                & \multicolumn{3}{l|}{Cond.}
552
                & \multicolumn{21}{l|}{Operand B}
553
                & Yes \\\hline
554 24 dgisselq
TST(And) & \multicolumn{4}{l|}{4'h1}
555 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
556
                & \multicolumn{3}{l|}{Cond.}
557
                & \multicolumn{21}{l|}{Operand B}
558
        & Yes \\\hline
559
MOV & \multicolumn{4}{l|}{4'h2}
560
                & \multicolumn{4}{l|}{D. Reg}
561
                & \multicolumn{3}{l|}{Cond.}
562
                & A-Usr
563
                & \multicolumn{4}{l|}{B-Reg}
564
                & B-Usr
565
                & \multicolumn{15}{l|}{15'bit signed offset}
566
                & \\\hline
567
LODI & \multicolumn{4}{l|}{4'h3}
568
                & \multicolumn{4}{l|}{R. Reg}
569
                & \multicolumn{24}{l|}{24'bit Signed Immediate}
570
                & \\\hline
571
NOOP & \multicolumn{4}{l|}{4'h4}
572
                & \multicolumn{4}{l|}{4'he}
573
                & \multicolumn{24}{l|}{24'h00}
574
                & \\\hline
575
BREAK & \multicolumn{4}{l|}{4'h4}
576
                & \multicolumn{4}{l|}{4'he}
577
                & \multicolumn{24}{l|}{24'h01}
578
                & \\\hline
579 36 dgisselq
{\em Reserved} & \multicolumn{4}{l|}{4'h4}
580 21 dgisselq
                & \multicolumn{4}{l|}{4'he}
581
                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}
582
                & \\\hline
583
LODIHI & \multicolumn{4}{l|}{4'h4}
584
                & \multicolumn{4}{l|}{4'hf}
585
                & \multicolumn{3}{l|}{Cond.}
586
                & 1'b1
587
                & \multicolumn{4}{l|}{R. Reg}
588
                & \multicolumn{16}{l|}{16-bit Immediate}
589
                & \\\hline
590
LODILO & \multicolumn{4}{l|}{4'h4}
591
                & \multicolumn{4}{l|}{4'hf}
592
                & \multicolumn{3}{l|}{Cond.}
593
                & 1'b0
594
                & \multicolumn{4}{l|}{R. Reg}
595
                & \multicolumn{16}{l|}{16-bit Immediate}
596
                & \\\hline
597
16-b MPYU & \multicolumn{4}{l|}{4'h4}
598
                & \multicolumn{4}{l|}{R. Reg}
599
                & \multicolumn{3}{l|}{Cond.}
600
                & 1'b0 & \multicolumn{4}{l|}{Reg}
601
                & \multicolumn{16}{l|}{16-bit Offset}
602
                & Yes \\\hline
603
16-b MPYU(I) & \multicolumn{4}{l|}{4'h4}
604
                & \multicolumn{4}{l|}{R. Reg}
605
                & \multicolumn{3}{l|}{Cond.}
606
                & 1'b0 & \multicolumn{4}{l|}{4'hf}
607
                & \multicolumn{16}{l|}{16-bit Offset}
608
                & Yes \\\hline
609
16-b MPYS & \multicolumn{4}{l|}{4'h4}
610
                & \multicolumn{4}{l|}{R. Reg}
611
                & \multicolumn{3}{l|}{Cond.}
612
                & 1'b1 & \multicolumn{4}{l|}{Reg}
613
                & \multicolumn{16}{l|}{16-bit Offset}
614
                & Yes \\\hline
615
16-b MPYS(I) & \multicolumn{4}{l|}{4'h4}
616
                & \multicolumn{4}{l|}{R. Reg}
617
                & \multicolumn{3}{l|}{Cond.}
618
                & 1'b1 & \multicolumn{4}{l|}{4'hf}
619
                & \multicolumn{16}{l|}{16-bit Offset}
620
                & Yes \\\hline
621
ROL & \multicolumn{4}{l|}{4'h5}
622
                & \multicolumn{4}{l|}{R. Reg}
623
                & \multicolumn{3}{l|}{Cond.}
624
                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}
625
                & \\\hline
626
LOD & \multicolumn{4}{l|}{4'h6}
627
                & \multicolumn{4}{l|}{R. Reg}
628
                & \multicolumn{3}{l|}{Cond.}
629
                & \multicolumn{21}{l|}{Operand B address}
630
                & \\\hline
631
STO & \multicolumn{4}{l|}{4'h7}
632
                & \multicolumn{4}{l|}{D. Reg}
633
                & \multicolumn{3}{l|}{Cond.}
634
                & \multicolumn{21}{l|}{Operand B address}
635
                & \\\hline
636
SUB & \multicolumn{4}{l|}{4'h8}
637
        &       \multicolumn{4}{l|}{R. Reg}
638
        &       \multicolumn{3}{l|}{Cond.}
639 32 dgisselq
        &       \multicolumn{21}{l|}{Operand B}
640 21 dgisselq
        & Yes \\\hline
641
AND & \multicolumn{4}{l|}{4'h9}
642
        &       \multicolumn{4}{l|}{R. Reg}
643
        &       \multicolumn{3}{l|}{Cond.}
644
        &       \multicolumn{21}{l|}{Operand B}
645
        & Yes \\\hline
646
ADD & \multicolumn{4}{l|}{4'ha}
647
        &       \multicolumn{4}{l|}{R. Reg}
648
        &       \multicolumn{3}{l|}{Cond.}
649
        &       \multicolumn{21}{l|}{Operand B}
650
        & Yes \\\hline
651
OR & \multicolumn{4}{l|}{4'hb}
652
        &       \multicolumn{4}{l|}{R. Reg}
653
        &       \multicolumn{3}{l|}{Cond.}
654
        &       \multicolumn{21}{l|}{Operand B}
655
        & Yes \\\hline
656
XOR & \multicolumn{4}{l|}{4'hc}
657
        &       \multicolumn{4}{l|}{R. Reg}
658
        &       \multicolumn{3}{l|}{Cond.}
659
        &       \multicolumn{21}{l|}{Operand B}
660
        & Yes \\\hline
661
LSL/ASL & \multicolumn{4}{l|}{4'hd}
662
        &       \multicolumn{4}{l|}{R. Reg}
663
        &       \multicolumn{3}{l|}{Cond.}
664 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
665 21 dgisselq
        & Yes \\\hline
666
ASR & \multicolumn{4}{l|}{4'he}
667
        &       \multicolumn{4}{l|}{R. Reg}
668
        &       \multicolumn{3}{l|}{Cond.}
669 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
670 21 dgisselq
        & Yes \\\hline
671
LSR & \multicolumn{4}{l|}{4'hf}
672
        &       \multicolumn{4}{l|}{R. Reg}
673
        &       \multicolumn{3}{l|}{Cond.}
674 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
675 21 dgisselq
        & Yes \\\hline
676
\end{tabular}
677
\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions}
678
\end{center}\end{table}
679
 
680
As you can see, there's lots of room for instruction set expansion.  The
681 24 dgisselq
NOOP and BREAK instructions are the only instructions within one particular
682 36 dgisselq
24--bit hole.  The rest of this space is reserved for future enhancements.
683 21 dgisselq
 
684
\section{Derived Instructions}
685 36 dgisselq
The Zip CPU supports many other common instructions, but not all of them
686 24 dgisselq
are single cycle instructions.  The derived instruction tables,
687 36 dgisselq
Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3}
688
and~\ref{tbl:derived-4},
689 21 dgisselq
help to capture some of how these other instructions may be implemented on
690 36 dgisselq
the Zip CPU.  Many of these instructions will have assembly equivalents,
691 21 dgisselq
such as the branch instructions, to facilitate working with the CPU.
692
\begin{table}\begin{center}
693
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
694
Mapped & Actual  & Notes \\\hline
695 36 dgisselq
ABS Rx
696
        & \parbox[t]{1.5in}{TST -1,Rx\\NEG.LT Rx}
697
        & Absolute value, depends upon derived NEG.\\\hline
698 21 dgisselq
\parbox[t]{1.4in}{ADD Ra,Rx\\ADDC Rb,Ry}
699
        & \parbox[t]{1.5in}{Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry} 700  & Add with carry \\\hline 701 BRA.Cond +/-\$Addr
702 33 dgisselq
        & \hbox{MOV.cond \$Addr+PC,PC} 703 24 dgisselq  & Branch or jump on condition. Works for 15--bit 704  signed address offsets.\\\hline 705 21 dgisselq BRA.Cond +/-\$Addr
706
        & \parbox[t]{1.5in}{LDI \$Addr,Rx \\ ADD.cond Rx,PC} 707  & Branch/jump on condition. Works for 708  23 bit address offsets, but costs a register, an extra instruction, 709 33 dgisselq  and sets the flags. \\\hline 710 21 dgisselq BNC PC+\$Addr
711
        & \parbox[t]{1.5in}{Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
712
        & Example of a branch on an unsupported
713
                condition, in this case a branch on not carry \\\hline
714
BUSY & MOV \$-1(PC),PC & Execute an infinite loop \\\hline 715 CLRF.NZ Rx 716  & XOR.NZ Rx,Rx 717  & Clear Rx, and flags, if the Z-bit is not set \\\hline 718 CLR Rx 719  & LDI \$0,Rx
720
        & Clears Rx, leaves flags untouched.  This instruction cannot be
721
                conditional. \\\hline
722
EXCH.W Rx
723
        & ROL \$16,Rx 724  & Exchanges the top and bottom 16'bit words of Rx \\\hline 725 HALT 726  & Or \$SLEEP,CC
727
        & Executed while in interrupt mode.  In user mode this is simply a
728 33 dgisselq
        wait until interrupt instruction. \\\hline
729 21 dgisselq
INT & LDI \$0,CC 730  & Since we're using the CC register as a trap vector as well, this 731  executes TRAP \#0. \\\hline 732 IRET 733  & OR \$GIE,CC
734
        & Also an RTU instruction (Return to Userspace) \\\hline
735
JMP R6+\$Addr 736  & MOV \$Addr(R6),PC
737
        & \\\hline
738
JSR PC+\$Addr 739  & \parbox[t]{1.5in}{SUB \$1,SP \\\
740
        MOV \$3+PC,R0 \\ 741  STO R0,1(SP) \\ 742  MOV \$Addr+PC,PC \\
743
        ADD \$1,SP} 744 24 dgisselq  & Jump to Subroutine. Note the required cleanup instruction after 745 36 dgisselq  returning. This could easily be turned into a three instruction 746  operand, removing the preliminary stack instruction before and 747  the cleanup after, by adjusting how any stack frame was built for 748  this routine to include space at the top of the stack for the PC. 749  \\\hline 750 21 dgisselq JSR PC+\$Addr
751
        & \parbox[t]{1.5in}{MOV \$3+PC,R12 \\ MOV \$addr+PC,PC}
752
        &This is the high speed
753
        version of a subroutine call, necessitating a register to hold the
754
        last PC address.  In its favor, this method doesn't suffer the
755
        mandatory memory access of the other approach. \\\hline
756
LDI.l \$val,Rx 757  & \parbox[t]{1.5in}{LDIHI (\$val$>>$16)\&0x0ffff, Rx \\
758
                        LDILO (\$val \& 0x0ffff)} 759  & Sadly, there's not enough instruction 760  space to load a complete immediate value into any register. 761  Therefore, fully loading any register takes two cycles. 762  The LDIHI (load immediate high) and LDILO (load immediate low) 763  instructions have been created to facilitate this. \\\hline 764 \end{tabular} 765 \caption{Derived Instructions}\label{tbl:derived-1} 766 \end{center}\end{table} 767 \begin{table}\begin{center} 768 \begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline 769 Mapped & Actual & Notes \\\hline 770 LOD.b \$addr,Rx
771
        & \parbox[t]{1.5in}{%
772
        LDI     \$addr,Ra \\ 773  LDI \$addr,Rb \\
774
        LSR     \$2,Ra \\ 775  AND \$3,Rb \\
776
        LOD     (Ra),Rx \\
777
        LSL     \$3,Rb \\ 778  SUB \$32,Rb \\
779
        ROL     Rb,Rx \\
780
        AND \$0ffh,Rx} 781  & \parbox[t]{3in}{This CPU is designed for 32'bit word 782  length instructions. Byte addressing is not supported by the CPU or 783  the bus, so it therefore takes more work to do. 784   785  Note also that in this example, \$Addr is a byte-wise address, where
786 24 dgisselq
        all other addresses in this document are 32-bit wordlength addresses.
787
        For this reason,
788 21 dgisselq
        we needed to drop the bottom two bits.  This also limits the address
789
        space of character accesses using this method from 16 MB down to 4MB.}
790
                \\\hline
791
\parbox[t]{1.5in}{LSL \$1,Rx\\ LSLC \$1,Ry}
792
        & \parbox[t]{1.5in}{LSL \$1,Ry \\ 793  LSL \$1,Rx \\
794
        OR.C \$1,Ry} 795  & Logical shift left with carry. Note that the 796  instruction order is now backwards, to keep the conditions valid. 797 33 dgisselq  That is, LSL sets the carry flag, so if we did this the other way 798 21 dgisselq  with Rx before Ry, then the condition flag wouldn't have been right 799  for an OR correction at the end. \\\hline 800 \parbox[t]{1.5in}{LSR \$1,Rx \\ LSRC \$1,Ry} 801  & \parbox[t]{1.5in}{CLR Rz \\ 802  LSR \$1,Ry \\
803
        LDIHI.C \$8000h,Rz \\ 804  LSR \$1,Rx \\
805
        OR Rz,Rx}
806
        & Logical shift right with carry \\\hline
807
NEG Rx & \parbox[t]{1.5in}{XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline
808 36 dgisselq
NEG.C Rx & \parbox[t]{1.5in}{MOV.C \$-1+Rx,Rx\\XOR.C \$-1,Rx} & \\\hline
809 21 dgisselq
NOOP & NOOP & While there are many
810
        operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these 811  operations have consequences in that they might stall the bus if 812  Rx isn't ready yet. For this reason, we have a dedicated NOOP 813  instruction. \\\hline 814 NOT Rx & XOR \$-1,Rx & \\\hline
815
POP Rx
816 37 dgisselq
        & \parbox[t]{1.5in}{LOD \$1(SP),Rx \\ ADD \$1,SP}
817 21 dgisselq
        & Note
818
        that for interrupt purposes, one can never depend upon the value at
819
        (SP).  Hence you read from it, then increment it, lest having
820 33 dgisselq
        incremented it first something then comes along and writes to that
821 21 dgisselq
        value before you can read the result. \\\hline
822 36 dgisselq
\end{tabular}
823
\caption{Derived Instructions, continued}\label{tbl:derived-2}
824
\end{center}\end{table}
825
\begin{table}\begin{center}
826
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
827 21 dgisselq
PUSH Rx
828 33 dgisselq
        & \parbox[t]{1.5in}{SUB \$1,SP \\ 829 21 dgisselq  STO Rx,\$1(SP)}
830
        & \\\hline
831 36 dgisselq
PUSH Rx-Ry
832
        & \parbox[t]{1.5in}{SUB \$n,SP \\ 833  STO Rx,\$n(SP)
834
        \ldots \\
835
        STO Ry,\$1(SP)} 836  & Multiple pushes at once only need the single subtract from the 837  stack pointer. This derived instruction is analogous to a similar one 838  on the Motoroloa 68k architecture, although the Zip Assembler 839  does not support this instruction (yet).\\\hline 840 21 dgisselq RESET 841  & \parbox[t]{1in}{STO \$1,\$watchdog(R12)\\NOOP\\NOOP} 842  & \parbox[t]{3in}{This depends upon the peripheral base address being 843  in R12. 844   845  Another opportunity might be to jump to the reset address from within 846  supervisor mode.}\\\hline 847 36 dgisselq RET & \parbox[t]{1.5in}{LOD \$1(SP),PC}
848 24 dgisselq
        & Note that this depends upon the calling context to clean up the
849
        stack, as outlined for the JSR instruction.  \\\hline
850 21 dgisselq
RET & MOV R12,PC
851
        & This is the high(er) speed version, that doesn't touch the stack.
852
        As such, it doesn't suffer a stall on memory read/write to the stack.
853
        \\\hline
854
STEP Rr,Rt
855
        & \parbox[t]{1.5in}{LSR \$1,Rr \\ XOR.C Rt,Rr} 856  & Step a Galois implementation of a Linear Feedback Shift Register, Rr, 857  using taps Rt \\\hline 858 STO.b Rx,\$addr
859
        & \parbox[t]{1.5in}{%
860
        LDI \$addr,Ra \\ 861  LDI \$addr,Rb \\
862
        LSR \$2,Ra \\ 863  AND \$3,Rb \\
864
        SUB \$32,Rb \\ 865  LOD (Ra),Ry \\ 866  AND \$0ffh,Rx \\
867
        AND \$-0ffh,Ry \\ 868  ROL Rb,Rx \\ 869  OR Rx,Ry \\ 870  STO Ry,(Ra) } 871  & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized 872  for byte-wise operations. 873   874  Note that in this example, \$addr is a
875
        byte-wise address, whereas in all of our other examples it is a
876
        32-bit word address. This also limits the address space
877
        of character accesses from 16 MB down to 4MB.F
878
        Further, this instruction implies a byte ordering,
879
        such as big or little endian.} \\\hline
880
SWAP Rx,Ry
881
        & \parbox[t]{1.5in}{
882
        XOR Ry,Rx \\
883
        XOR Rx,Ry \\
884
        XOR Ry,Rx}
885
        & While no extra registers are needed, this example
886
        does take 3-clocks. \\\hline
887
TRAP \#X
888 36 dgisselq
        & \parbox[t]{1.5in}{LDI \$x,R0 \\ AND ~\$GIE,CC }
889
        & This works because whenever a user lowers the \$GIE flag, it sets 890  a TRAP bit within the CC register. Therefore, upon entering the 891  supervisor state, the CPU only need check this bit to know that it 892  got there via a TRAP. The trap could be made conditional by making 893  the LDI and the AND conditional. In that case, the assembler would 894  quietly turn the LDI instruction into an LDILO and LDIHI pair, 895 37 dgisselq  but the effect would be the same. \\\hline 896 36 dgisselq \end{tabular} 897 \caption{Derived Instructions, continued}\label{tbl:derived-3} 898 \end{center}\end{table} 899 \begin{table}\begin{center} 900 \begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline 901 21 dgisselq TST Rx 902  & TST \$-1,Rx
903
        & Set the condition codes based upon Rx.  Could also do a CMP \$0,Rx, 904  ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc.  The TST and CMP
905
        approaches won't stall future pipeline stages looking for the value
906
        of Rx. \\\hline
907
WAIT
908
        & Or \$SLEEP,CC 909  & Wait 'til interrupt. In an interrupts disabled context, this 910  becomes a HALT instruction. 911 \end{tabular} 912 36 dgisselq \caption{Derived Instructions, continued}\label{tbl:derived-4} 913 21 dgisselq \end{center}\end{table} 914 \section{Pipeline Stages} 915 32 dgisselq As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu}, 916 the Zip CPU supports a five stage pipeline. 917 21 dgisselq \begin{enumerate} 918 36 dgisselq \item {\bf Prefetch}: Reads instruction from memory and into a cache, if so 919  configured. This 920 21 dgisselq  stage is actually pipelined itself, and so it will stall if the PC 921  ever changes. Stalls are also created here if the instruction isn't 922  in the prefetch cache. 923 36 dgisselq   924  The Zip CPU supports one of two prefetch methods, depending upon a flag 925  set at build time within the {\tt zipcpu.v} file. The simplest is a 926  non--cached implementation of a prefetch. This implementation is 927  fairly small, and ideal for 928  users of the Zip CPU who need the extra space on the FPGA fabric. 929  However, because this non--cached version has no cache, the maximum 930  number of instructions per clock is limited to about one per five. 931   932  The second prefetch module is a pipelined prefetch with a cache. This 933  module tries to keep the instruction address within a window of valid 934  instruction addresses. While effective, it is not a traditional 935  cache implementation. One unique feature of this cache implementation, 936  however, is that it can be cleared in a single clock. A disappointing 937  feature, though, was that it needs an extra internal pipeline stage 938  to be implemented. 939   940 \item {\bf Decode}: Decodes an instruction into op code, register(s) to read, 941  and immediate offset. This stage also determines whether the flags will 942 32 dgisselq  be set or whether the result will be written back. 943 21 dgisselq \item {\bf Read Operands}: Read registers and apply any immediate values to 944 24 dgisselq  them. There is no means of detecting or flagging arithmetic overflow 945  or carry when adding the immediate to the operand. This stage will 946  stall if any source operand is pending. 947 21 dgisselq \item Split into two tracks: An {\bf ALU} which will accomplish a simple 948 36 dgisselq  instruction, and the {\bf MemOps} stage which handles {\tt LOD} (load) 949  and {\tt STO} (store) instructions. 950 21 dgisselq  \begin{itemize} 951 36 dgisselq  \item Loads will stall the entire pipeline until complete. 952  \item Condition codes are available upon completion of the ALU stage 953  \item Issuing an instruction to the memory unit while the memory unit 954  is busy will stall the entire pipeline. If the bus deadlocks, 955  only a reset will release the CPU. (Watchdog timer, anyone?) 956 24 dgisselq  \item The Zip CPU currently has no means of reading and acting on any 957  error conditions on the bus. 958 21 dgisselq  \end{itemize} 959 32 dgisselq \item {\bf Write-Back}: Conditionally write back the result to the register 960 36 dgisselq  set, applying the condition. This routine is bi-entrant: either the 961 21 dgisselq  memory or the simple instruction may request a register write. 962 \end{enumerate} 963   964 24 dgisselq The Zip CPU does not support out of order execution. Therefore, if the memory 965 unit stalls, every other instruction stalls. Memory stores, however, can take 966 36 dgisselq place concurrently with ALU operations, although memory reads (loads) cannot. 967 24 dgisselq   968 32 dgisselq \section{Pipeline Stalls} 969 The processing pipeline can and will stall for a variety of reasons. Some of 970 these are obvious, some less so. These reasons are listed below: 971 \begin{itemize} 972 \item When the prefetch cache is exhausted 973 21 dgisselq   974 36 dgisselq This reason should be obvious. If the prefetch cache doesn't have the 975 instruction in memory, the entire pipeline must stall until enough of the 976 prefetch cache is loaded to support the next instruction. 977 21 dgisselq   978 32 dgisselq \item While waiting for the pipeline to load following any taken branch, jump, 979 36 dgisselq  return from interrupt or switch to interrupt context (5 stall cycles) 980 32 dgisselq   981 If the PC suddenly changes, the pipeline is subsequently cleared and needs to 982 be reloaded. Given that there are five stages to the pipeline, that accounts 983 36 dgisselq for four of the five stalls. The stall cycle is lost in the pipelined prefetch 984 32 dgisselq stage which needs at least one clock with a valid PC before it can produce 985 36 dgisselq a new output. 986 32 dgisselq   987 36 dgisselq The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and 988 {\tt LDI \$X,PC} instructions specially, however.  These instructions, when
989
not conditioned on the flags, can execute with only 3~stall cycles.
990
 
991 32 dgisselq
\item When reading from a prior register while also adding an immediate offset
992
\begin{enumerate}
993
\item\ {\tt OPCODE ?,RA}
994
\item\ {\em (stall)}
995
\item\ {\tt OPCODE I+RA,RB}
996
\end{enumerate}
997
 
998
Since the addition of the immediate register within OpB decoding gets applied
999
during the read operand stage so that it can be nicely settled before the ALU,
1000
any instruction that will write back an operand must be separated from the
1001
opcode that will read and apply an immediate offset by one instruction.  The
1002
good news is that this stall can easily be mitigated by proper scheduling.
1003 36 dgisselq
That is, any instruction that does not add an immediate to {\tt RA} may be
1004
scheduled into the stall slot.
1005 32 dgisselq
 
1006 36 dgisselq
\item When any write to either the CC or PC Register is followed by a memory
1007
        operation
1008 32 dgisselq
\begin{enumerate}
1009
\item\ {\tt OPCODE RA,PC} {\em Ex: a branch opcode}
1010
\item\ {\em (stall, even if jump not taken)}
1011 36 dgisselq
\item\ {\tt LOD \$X(RA),RB} 1012 32 dgisselq \end{enumerate} 1013 Since branches take place in the writeback stage, the Zip CPU will stall the 1014 pipeline for one clock anytime there may be a possible jump. This prevents 1015 an instruction from executing a memory access after the jump but before the 1016 jump is recognized. 1017   1018 36 dgisselq This stall may be mitigated by shuffling the operations immediately following 1019 a potential branch so that an ALU operation follows the branch instead of a 1020 memory operation. 1021 33 dgisselq   1022 32 dgisselq \item When reading from the CC register after setting the flags 1023 \begin{enumerate} 1024 36 dgisselq \item\ {\tt ALUOP RA,RB} {\em Ex: a compare opcode} 1025 \item\ {\em (stall)} 1026 32 dgisselq \item\ {\tt TST sys.ccv,CC} 1027 \item\ {\tt BZ somewhere} 1028 \end{enumerate} 1029   1030 The reason for this stall is simply performance. Many of the flags are 1031 determined via combinatorial logic after the writeback instruction is 1032 determined. Trying to then place these into the input for one of the operands 1033 created a time delay loop that would no longer execute in a single 100~MHz 1034 clock cycle. (The time delay of the multiply within the ALU wasn't helping 1035 either \ldots). 1036   1037 33 dgisselq This stall may be eliminated via proper scheduling, by placing an instruction 1038 that does not set flags in between the ALU operation and the instruction 1039 that references the CC register. For example, {\tt MOV \$addr+PC,uPC}
1040
followed by an {\tt RTU} ({\tt OR \$GIE,CC}) instruction will not incur 1041 this stall, whereas an {\tt OR \$BREAKEN,CC} followed by an {\tt OR \$STEP,CC} 1042 36 dgisselq will incur the stall, while a {\tt LDI \$BREAKEN|\$STEP,CC} will not. 1043 33 dgisselq   1044 32 dgisselq \item When waiting for a memory read operation to complete 1045 \begin{enumerate} 1046 \item\ {\tt LOD address,RA} 1047 36 dgisselq \item\ {\em (multiple stalls, bus dependent, 4 clocks best)} 1048 32 dgisselq \item\ {\tt OPCODE I+RA,RB} 1049 \end{enumerate} 1050   1051 36 dgisselq Remember, the Zip CPU does not support out of order execution. Therefore, 1052 32 dgisselq anytime the memory unit becomes busy both the memory unit and the ALU must 1053 stall until the memory unit is cleared. This is especially true of a load 1054 33 dgisselq instruction, which must still write its operand back to the register file. 1055 Store instructions are different, since they can be busy with no impact on 1056 later ALU write back operations. Hence, only loads stall the pipeline. 1057 32 dgisselq   1058 This also assumes that the memory being accessed is a single cycle memory. 1059 Slower memories, such as the Quad SPI flash, will take longer--perhaps even 1060 33 dgisselq as long as forty clocks. During this time the CPU and the external bus 1061 32 dgisselq will be busy, and unable to do anything else. 1062   1063 \item Memory operation followed by a memory operation 1064 \begin{enumerate} 1065 \item\ {\tt STO address,RA} 1066 36 dgisselq \item\ {\em (multiple stalls, bus dependent, 4 clocks best)} 1067 32 dgisselq \item\ {\tt LOD address,RB} 1068 36 dgisselq \item\ {\em (multiple stalls, bus dependent, 4 clocks best)} 1069 32 dgisselq \end{enumerate} 1070   1071 36 dgisselq In this case, the LOD instruction cannot start until the STO is finished. 1072 32 dgisselq With proper scheduling, it is possible to do something in the ALU while the 1073 36 dgisselq memory unit is busy with the STO instruction, but otherwise this pipeline will 1074 stall waiting for it to complete. 1075 32 dgisselq   1076 Note that even though the Wishbone bus can support pipelined accesses at 1077 one access per clock, only the prefetch stage can take advantage of this. 1078 Load and Store instructions are stuck at one wishbone cycle per instruction. 1079 36 dgisselq   1080 \item When waiting for a conditional memory read operation to complete 1081 \begin{enumerate} 1082 \item\ {\tt LOD.Z address,RA} 1083 \item\ {\em (multiple stalls, bus dependent, 7 clocks best)} 1084 \item\ {\tt OPCODE I+RA,RB} 1085 \end{enumerate} 1086   1087 In this case, the Zip CPU doesn't warn the prefetch cache to get off the bus 1088 two cycles before using the bus, so there's a potential for an extra three 1089 cycle cost due to bus contention between the prefetch and the CPU. 1090   1091 This is true for both the LOD and the STO instructions, with the exception that 1092 the STO instruction will continue in parallel with any ALU instructions that 1093 follow it. 1094   1095 32 dgisselq \end{itemize} 1096   1097   1098 21 dgisselq \chapter{Peripherals}\label{chap:periph} 1099 24 dgisselq   1100 While the previous chapter describes a CPU in isolation, the Zip System 1101 includes a minimum set of peripherals as well. These peripherals are shown 1102 in Fig.~\ref{fig:zipsystem} 1103 \begin{figure}\begin{center} 1104 \includegraphics[width=3.5in]{../gfx/system.eps} 1105 \caption{Zip System Peripherals}\label{fig:zipsystem} 1106 \end{center}\end{figure} 1107 and described here. They are designed to make 1108 the Zip CPU more useful in an Embedded Operating System environment. 1109   1110 21 dgisselq \section{Interrupt Controller} 1111 24 dgisselq   1112 Perhaps the most important peripheral within the Zip System is the interrupt 1113 controller. While the Zip CPU itself can only handle one interrupt, and has 1114 only the one interrupt state: disabled or enabled, the interrupt controller 1115 can make things more interesting. 1116   1117 The Zip System interrupt controller module supports up to 15 interrupts, all 1118 controlled from one register. Bit~31 of the interrupt controller controls 1119 overall whether interrupts are enabled (1'b1) or disabled (1'b0). Bits~16--30 1120 control whether individual interrupts are enabled (1'b0) or disabled (1'b0). 1121 Bit~15 is an indicator showing whether or not any interrupt is active, and 1122 bits~0--15 indicate whether or not an individual interrupt is active. 1123   1124 The interrupt controller has been designed so that bits can be controlled 1125 individually without having any knowledge of the rest of the controller 1126 setting. To enable an interrupt, write to the register with the high order 1127 global enable bit set and the respective interrupt enable bit set. No other 1128 bits will be affected. To disable an interrupt, write to the register with 1129 the high order global enable bit cleared and the respective interrupt enable 1130 bit set. To clear an interrupt, write a 1' to that interrupts status pin. 1131 Zero's written to the register have no affect, save that a zero written to the 1132 master enable will disable all interrupts. 1133   1134 As an example, suppose you wished to enable interrupt \#4. You would then 1135 write to the register a {\tt 0x80100010} to enable interrupt \#4 and to clear 1136 any past active state. When you later wish to disable this interrupt, you would 1137 write a {\tt 0x00100010} to the register. As before, this both disables the 1138 interrupt and clears the active indicator. This also has the side effect of 1139 disabling all interrupts, so a second write of {\tt 0x80000000} may be necessary 1140 to re-enable any other interrupts. 1141   1142 The Zip System currently hosts two interrupt controllers, a primary and a 1143 secondary. The primary interrupt controller has one interrupt line which may 1144 come from an external interrupt controller, and one interrupt line from the 1145 secondary controller. Other primary interrupts include the system timers, 1146 the jiffies interrupt, and the manual cache interrupt. The secondary interrupt 1147 controller maintains an interrupt state for all of the processor accounting 1148 counters. 1149   1150 21 dgisselq \section{Counter} 1151   1152 The Zip Counter is a very simple counter: it just counts. It cannot be 1153 halted. When it rolls over, it issues an interrupt. Writing a value to the 1154 counter just sets the current value, and it starts counting again from that 1155 value. 1156   1157 Eight counters are implemented in the Zip System for process accounting. 1158 This may change in the future, as nothing as yet uses these counters. 1159   1160 \section{Timer} 1161   1162 The Zip Timer is also very simple: it simply counts down to zero. When it 1163 transitions from a one to a zero it creates an interrupt. 1164   1165 Writing any non-zero value to the timer starts the timer. If the high order 1166 bit is set when writing to the timer, the timer becomes an interval timer and 1167 reloads its last start time on any interrupt. Hence, to mark seconds, one 1168 might set the timer to 100~million (the number of clocks per second), and 1169 set the high bit. Ever after, the timer will interrupt the CPU once per 1170 24 dgisselq second (assuming a 100~MHz clock). This reload capability also limits the 1171 maximum timer value to$2^{31}-1$, rather than$2^{32}-1$. 1172 21 dgisselq   1173 \section{Watchdog Timer} 1174   1175 The watchdog timer is no different from any of the other timers, save for one 1176 critical difference: the interrupt line from the watchdog 1177 timer is tied to the reset line of the CPU. Hence writing a 1' to the 1178 watchdog timer will always reset the CPU. 1179 32 dgisselq To stop the Watchdog timer, write a 0' to it. To start it, 1180 21 dgisselq write any other number to it---as with the other timers. 1181   1182 While the watchdog timer supports interval mode, it doesn't make as much sense 1183 as it did with the other timers. 1184   1185 \section{Jiffies} 1186   1187 This peripheral is motivated by the Linux use of jiffies' whereby a process 1188 can request to be put to sleep until a certain number of jiffies' have 1189 elapsed. Using this interface, the CPU can read the number of jiffies' 1190 from the peripheral (it only has the one location in address space), add the 1191 24 dgisselq sleep length to it, and write the result back to the peripheral. The zipjiffies 1192 21 dgisselq peripheral will record the value written to it only if it is nearer the current 1193 counter value than the last current waiting interrupt time. If no other 1194 interrupts are waiting, and this time is in the future, it will be enabled. 1195 (There is currently no way to disable a jiffie interrupt once set, other 1196 24 dgisselq than to disable the interrupt line in the interrupt controller.) The processor 1197 21 dgisselq may then place this sleep request into a list among other sleep requests. 1198 Once the timer expires, it would write the next Jiffy request to the peripheral 1199 and wake up the process whose timer had expired. 1200   1201 Indeed, the Jiffies register is nothing more than a glorified counter with 1202 an interrupt. Unlike the other counters, the Jiffies register cannot be set. 1203 Writes to the jiffies register create an interrupt time. When the Jiffies 1204 register later equals the value written to it, an interrupt will be asserted 1205 and the register then continues counting as though no interrupt had taken 1206 place. 1207   1208 The purpose of this register is to support alarm times within a CPU. To 1209 set an alarm for a particular process$N$clocks in advance, read the current 1210 Jiffies value, and$N$, and write it back to the Jiffies register. The 1211 O/S must also keep track of values written to the Jiffies register. Thus, 1212 32 dgisselq when an alarm' trips, it should be removed from the list of alarms, the list 1213 21 dgisselq should be sorted, and the next alarm in terms of Jiffies should be written 1214 to the register. 1215   1216 36 dgisselq \section{Direct Memory Access Controller} 1217 24 dgisselq   1218 36 dgisselq The Direct Memory Access (DMA) controller can be used to either move memory 1219 from one location to another, to read from a peripheral into memory, or to 1220 write from a peripheral into memory all without CPU intervention. Further, 1221 since the DMA controller can issue (and does issue) pipeline wishbone accesses, 1222 any DMA memory move will by nature be faster than a corresponding program 1223 accomplishing the same move. To put this to numbers, it may take a program 1224 18~clocks per word transferred, whereas this DMA controller can move one 1225 word in two clocks--provided it has bus access. (The CPU gets priority over the 1226 bus.) 1227 24 dgisselq   1228 36 dgisselq When copying memory from one location to another, the DMA controller will 1229 copy in units of a given transfer length--up to 1024 words at a time. It will 1230 read that transfer length into its internal buffer, and then write to the 1231 destination address from that buffer. If the CPU interrupts a DMA transfer, 1232 it will release the bus, let the CPU complete whatever it needs to do, and then 1233 restart its transfer by writing the contents of its internal buffer and then 1234 re-entering its read cycle again. 1235 24 dgisselq   1236 36 dgisselq When coupled with a peripheral, the DMA controller can be configured to start 1237 a memory copy on an interrupt line going high. Further, the controller can be 1238 configured to issue reads from (or two) the same address instead of incrementing 1239 the address at each clock. The DMA completes once the total number of items 1240 specified (not the transfer length) have been transferred. 1241   1242 In each case, once the transfer is complete and the DMA unit returns to 1243 idle, the DMA will issue an interrupt. 1244   1245   1246 21 dgisselq \chapter{Operation}\label{chap:ops} 1247   1248 33 dgisselq The Zip CPU, and even the Zip System, is not a System on a Chip (SoC). It 1249 needs to be connected to its operational environment in order to be used. 1250 Specifically, some per system adjustments need to be made: 1251 \begin{enumerate} 1252 \item The Zip System depends upon an external 32-bit Wishbone bus. This 1253  must exist, and must be connected to the Zip CPU for it to work. 1254 \item The Zip System needs to be told of its {\tt RESET\_ADDRESS}. This is 1255  the program counter of the first instruction following a reset. 1256 \item If you want the Zip System to start up on its own, you will need to 1257  set the {\tt START\_HALTED} parameter to zero. Otherwise, if you 1258  wish to manually start the CPU, that is if upon reset you want the 1259  CPU start start in its halted, reset state, then set this parameter to 1260  one. 1261 \item The third parameter to set is the number of interrupts you will be 1262  providing from external to the CPU. This can be anything from one 1263  to nine, but it cannot be zero. (Wire this line to a 1'b0 if you 1264  do not wish to support any external interrupts.) 1265 \item Finally, you need to place into some wishbone accessible address, whether 1266  RAM or (more likely) ROM, the initial instructions for the CPU. 1267 \end{enumerate} 1268 If you have enabled your CPU to start automatically, then upon power up the 1269 CPU will immediately start executing your instructions. 1270   1271 This is, however, not how I have used the Zip CPU. I have instead used the 1272 36 dgisselq Zip CPU in a more controlled environment. For me, the CPU starts in a 1273 33 dgisselq halted state, and waits to be told to start. Further, the RESET address is a 1274 location in RAM. After bringing up the board I am using, and further the 1275 bus that is on it, the RAM memory is then loaded externally with the program 1276 I wish the Zip System to run. Once the RAM is loaded, I release the CPU. 1277 The CPU then runs until its halt condition, at which point its task is 1278 complete. 1279   1280 Eventually, I intend to place an operating system onto the ZipSystem, I'm 1281 just not there yet. 1282   1283 36 dgisselq The rest of this chapter examines some common programming constructs, and 1284 how they might be applied to the Zip System. 1285 33 dgisselq   1286 36 dgisselq \section{Example: Idle Task} 1287 One task every operating system needs is the idle task, the task that takes 1288 place when nothing else can run. On the Zip CPU, this task is quite simple, 1289 and it is shown in assemble in Tbl.~\ref{tbl:idle-asm}. 1290 \begin{table}\begin{center} 1291 \begin{tabular}{ll} 1292 {\tt idle\_task:} \\ 1293 & {\em ; Wait for the next interrupt, then switch to supervisor task} \\ 1294 & {\tt WAIT} \\ 1295 & {\em ; When we come back, it's because the supervisor wishes to} \\ 1296 & {\em ; wait for an interrupt again, so go back to the top.} \\ 1297 & {\tt BRA idle\_task} \\ 1298 \end{tabular} 1299 \caption{Example Idle Loop}\label{tbl:idle-asm} 1300 \end{center}\end{table} 1301 When this task runs, the CPU will fill up all of the pipeline stages up the 1302 ALU. The {\tt WAIT} instruction, upon leaving the ALU, places the CPU into 1303 a sleep state where nothing more moves. Sure, there may be some more settling, 1304 the pipe cache continue to read until full, other instructions may issue until 1305 the pipeline fills, but then everything will stall. Then, once an interrupt 1306 takes place, control passes to the supervisor task to handle the interrupt. 1307 When control passes back to this task, it will be on the next instruction. 1308 Since that next instruction sends us back to the top of the task, the idle 1309 task thus does nothing but wait for an interrupt. 1310   1311 This should be the lowest priority task, the task that runs when nothing else 1312 can. It will help lower the FPGA power usage overall---at least its dynamic 1313 power usage. 1314   1315 \section{Example: Memory Copy} 1316 One common operation is that of a memory move or copy. Consider the C code 1317 shown in Tbl.~\ref{tbl:memcp-c}. 1318 \begin{table}\begin{center} 1319 \parbox{4in}{\begin{tabbing} 1320 {\tt void} \= {\tt memcp(void *dest, void *src, int len) \{} \\ 1321  \> {\tt for(int i=0; i<len; i++)} \\ 1322  \> \hspace{0.2in} {\tt *dest++ = *src++;} \\ 1323 \} 1324 \end{tabbing}} 1325 \caption{Example Memory Copy code in C}\label{tbl:memcp-c} 1326 \end{center}\end{table} 1327 This same code can be translated in Zip Assembly as shown in 1328 Tbl.~\ref{tbl:memcp-asm}. 1329 \begin{table}\begin{center} 1330 \begin{tabular}{ll} 1331 memcp: \\ 1332 & {\em ; R0 = *dest, R1 = *src, R2 = LEN} \\ 1333 & {\em ; The following will operate in 17 clocks per word minus one clock} \\ 1334 & {\tt CMP 0,R2} \\ 1335 & {\tt LOD.Z -1(SP),PC} {\em ; A conditional return }\\ 1336 & {\em ; (One stall on potentially writing to PC)} \\ 1337 & {\tt LOD (R1),R3} \\ 1338 & {\em ; (4 stalls, cannot be scheduled away)} \\ 1339 & {\tt STO R3,(R2)} {\em ; (4 schedulable stalls, has no impact now)} \\ 1340 & {\tt ADD 1,R1} \\ 1341 & {\tt SUB 1,R2} \\ 1342 & {\tt BNZ loop} \\ 1343 & {\em ; (5 stalls, if branch taken, to clear and refill the pipeline)} \\ 1344 & {\tt RET} \\ 1345 \end{tabular} 1346 \caption{Example Memory Copy code in Zip Assembly}\label{tbl:memcp-asm} 1347 \end{center}\end{table} 1348 This example points out several things associated with the Zip CPU. First, 1349 a straightforward implementation of a for loop is not the fastest loop 1350 structure. For this reason, we have placed the test to continue at the 1351 end. Second, all pointers are {\tt void} pointers to arbitrary 32--bit 1352 data types. The Zip CPU does not have explicit support for smaller or larger 1353 data types, and so this memory copy cannot be applied at a byte level. 1354 Third, we've optimized the conditional jump to a return instruction into a 1355 conditional return instruction. 1356   1357 \section{Context Switch} 1358   1359 Fundamental to any multiprocessing system is the ability to switch from one 1360 task to the next. In the ZipSystem, this is accomplished in one of a couple 1361 ways. The first step is that an interrupt happens. Anytime an interrupt 1362 happens, the CPU needs to execute the following tasks in supervisor mode: 1363 \begin{enumerate} 1364 \item Check for a trap instruction. That is, if the user task requested a 1365  trap, we may not wish to adjust the context, check interrupts, or call 1366  the scheduler. Tbl.~\ref{tbl:trap-check} 1367 \begin{table}\begin{center} 1368 \begin{tabular}{ll} 1369 {\tt return\_to\_user:} \\ 1370 & {\em; The instruction before the context switch processing must} \\ 1371 & {\em; be the RTU instruction that enacted user mode in the first} \\ 1372 & {\em; place. We show it here just for reference.} \\ 1373 & {\tt RTU} \\ 1374 {\tt trap\_check:} \\ 1375 & {\tt MOV uCC,R0} \\ 1376 & {\tt TST \$TRAP,R0} \\
1377
&       {\tt BNZ swap\_out} \\
1378
&       {; \em Do something here to execute the trap} \\
1379
&       {; \em Don't need to call the scheduler, so we can just return} \\
1380
&       {\tt BRA return\_to\_user} \\
1381
\end{tabular}
1382
\caption{Checking for whether the user issued a TRAP instruction}\label{tbl:trap-check}
1383
\end{center}\end{table}
1384
        shows the rudiments of this code, while showing nothing of how the
1385
        actual trap would be implemented.
1386
 
1387
You may also wish to note that the instruction before the first instruction
1388
in our context swap {\em must be} a return to userspace instruction.
1389
Remember, the supervisor process is re--entered where it left off.  This is
1390
different from many other processors that enter interrupt mode at some vector
1391
or other.  In this case, we always enter supervisor mode right where we last
1392
left.\footnote{The one exception to this rule is upon reset where supervisor
1393
mode is entered at a pre--programmed wishbone memory address.}
1394
 
1395
\item Capture user counters.  If the operating system is keeping track of
1396
        system usage via the accounting counters, those counters need to be
1397
        copied and accumulated into some master counter at this point.
1398
 
1399
\item Preserve the old context.  This involves pushing all the user registers
1400
        onto the user stack and then copying the resulting stack address
1401
        into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.
1402
\begin{table}\begin{center}
1403
\begin{tabular}{ll}
1404
{\tt swap\_out:} \\
1405
&        {\tt MOV -15(uSP),R1} \\
1406
&        {\tt STO R1,stack(R12)} \\
1407
&        {\tt MOV uPC,R0} \\
1408
&        {\tt STO R0,15(R1)} \\
1409
&        {\tt MOV uCC,R0} \\
1410
&        {\tt STO R0,14(R1)} \\
1411
&       {\em ; We can skip storing the stack, uSP, since it'll be stored}\\
1412
&       {\em ; elsewhere (in the task structure) }\\
1413
&        {\tt MOV uR13,R0} \\
1414
&        {\tt STO R0,13(R1)} \\
1415
        & \ldots {\em ; Need to repeat for all user registers} \\
1416
&        {\tt MOV uR0,R0} \\
1417
&        {\tt STO R0,1(R1)} \\
1418
\end{tabular}
1419
\caption{Example Storing User Task Context}\label{tbl:context-out}
1420
\end{center}\end{table}
1421
For the sake of discussion, we assume the supervisor maintains a
1422
pointer to the current task's structure in supervisor register
1423
{\tt R12}, and that {\tt stack} is an offset to the beginning of this
1424
structure indicating where the stack pointer is to be kept within it.
1425
 
1426
        For those who are still interested, the full code for this context
1427
        save can be found as an assembler macro within the assembler
1428
        include file, {\tt sys.i}.
1429
 
1430
\item Reset the watchdog timer.  If you are using the watchdog timer, it should
1431
        be reset on a context swap, to know that things are still working.
1432
        Example code for this is shown in Tbl.~\ref{tbl:reset-watchdog}.
1433
\begin{table}\begin{center}
1434
\begin{tabular}{ll}
1435
\multicolumn{2}{l}{{\tt define WATCHDOG\_ADDRESS 32'hc000\_0002}}\\
1436
\multicolumn{2}{l}{{\tt define WATCHDOG\_TICKS 32'd1\_000\_000} {; \em = 10 ms}}\\
1437
&       {\tt LDI WATCHDOG\_ADDRESS,R0} \\
1438
&       {\tt LDI WATCHDOG\_TICKS,R1} \\
1439
&       {\tt STO R1,(R0)}
1440
\end{tabular}
1441
\caption{Example Watchdog Reset}\label{tbl:reset-watchdog}
1442
\end{center}\end{table}
1443
 
1444
\item Interrupt handling.  An interrupt handler within the Zip System is nothing
1445
        more than a task.  At context swap time, the supervisor needs to
1446
        disable all of the interrupts that have tripped, and then enable
1447
        all of the tasks that would deal with each of these interrupts.
1448
        These can be user tasks, run at higher priority than any other user
1449
        tasks.  Either way, they will need to re--enable their own interrupt
1450
        themselves, if the interrupt is still relevant.
1451
 
1452
        An example of this master interrut handling is shown in
1453
        Tbl.~\ref{tbl:pre-handler}.
1454
\begin{table}\begin{center}
1455
\begin{tabular}{ll}
1456
{\tt pre\_handler:} \\
1457
&       {\tt LDI PIC\_ADDRESS,R0 } \\
1458
&       {\em ; Start by grabbing the interrupt state from the interrupt}\\
1459
&       {\em ; controller.  We'll store this into the register R7 so that }\\
1460
&       {\em ; we can keep and preserve this information for the scheduler}\\
1461
&       {\em ; to use later. }\\
1462
&       {\tt LOD (R0),R1} \\
1463
&       {\tt MOV R1,R7 } \\
1464
&       {\em ; As a next step, we need to acknowledge and disable all active}\\
1465
&       {\em ; interrupts. We'll start by calculating all of our active}\\
1466
&       {\em ; interrupts.}\\
1467
&       {\tt AND 0x07fff,R1 } \\
1468
&       {\em ; Put the active interrupts into the upper half of R1} \\
1469
&       {\tt ROL 16,R1 } \\
1470
&       {\tt LDILO 0x0ffff,R1   } \\
1471
&       {\tt AND R7,R1}\\
1472
&       {\em ; Acknowledge and disable active interrupts}\\
1473
&       {\em ; This also disables all interrupts from the controller, so}\\
1474
&       {\em ; we'll need to re-enable interrupts in general shortly } \\
1475
&       {\tt STO R1,(R0) } \\
1476
&       {\em ; We leave our active interrupt mask in R7 so the scheduler can}\\
1477
&       {\em ; release any tasks that depended upon them. } \\
1478
\end{tabular}
1479
\caption{Example checking for active interrupts}\label{tbl:pre-handler}
1480
\end{center}\end{table}
1481
 
1482
\item Calling the scheduler.  This needs to be done to pick the next task
1483
        to switch to.  It may be an interrupt handler, or it may  be a normal
1484
        user task.  From a priority standpoint, it would make sense that the
1485
        interrupt handlers all have a higher priority than the user tasks,
1486
        and that once they have been called the user tasks may then be called
1487
        again.  If no task is ready to run, run the idle task to wait for an
1488
        interrupt.
1489
 
1490
        This suggests a minimum of four task priorities:
1491
        \begin{enumerate}
1492
        \item Interrupt handlers, executed with their interrupts disabled
1493
        \item Device drivers, executed with interrupts re-enabled
1494
        \item User tasks
1495
        \item The idle task, executed when nothing else is able to execute
1496
        \end{enumerate}
1497
 
1498
        For our purposes here, we'll just assume that a pointer to the current
1499
        task is maintained in {\tt R12}, that a {\tt JSR scheduler} is
1500
        called, and that the next current task is likewise placed into
1501
        {\tt R12}.
1502
 
1503
\item Restore the new tasks context.  Given that the scheduler has returned a
1504
        task that can be run at this time, the stack pointer needs to be
1505
        pulled out of the tasks task structure, placed into the user
1506
        register, and then the rest of the user registers need to be popped
1507
        back off of the stack to run this task.  An example of this is
1508
        shown in Tbl.~\ref{tbl:context-in},
1509
\begin{table}\begin{center}
1510
\begin{tabular}{ll}
1511
{\tt swap\_in:} \\
1512
&       {\tt LOD stack(R12),R1} \\
1513
&       {\tt MOV 15(R1),uSP} \\
1514
&       {\tt LOD 15(R1),R0} \\
1515
&       {\tt MOV R0,uPC} \\
1516
&       {\tt LOD 14(R1),R0} \\
1517
&       {\tt MOV R0,uCC} \\
1518
&       {\tt LOD 13(R1),R0} \\
1519
&       {\tt MOV R0,uR12} \\
1520
        & \ldots {\em ; Need to repeat for all user registers} \\
1521
&       {\tt LOD 1(R1),R0} \\
1522
&       {\tt MOV R0,uR0} \\
1523
&       {\tt BRA return\_to\_user} \\
1524
\end{tabular}
1525
\caption{Example Restoring User Task Context}\label{tbl:context-in}
1526
\end{center}\end{table}
1527
        assuming as before that the task
1528
        pointer is found in supervisor register {\tt R12}.
1529
        As with storing the user context, the full code associated with
1530
        restoring the user context can be found in the assembler include
1531
        file, {\tt sys.i}.
1532
 
1533
\item Clear the userspace accounting registers.  In order to keep track of
1534
        per process system usage, these registers need to be cleared before
1535
        reactivating the userspace process.  That way, upon the next
1536
        interrupt, we'll know how many clocks the userspace program has
1537
        encountered, and how many instructions it was able to issue in
1538
        those many clocks.
1539
 
1540
\item Jump back to the instruction just before saving the last tasks context,
1541
        because that location in memory contains the return from interrupt
1542
        command that we are going to need to execute, in order to guarantee
1543
        that we return back here again.
1544
\end{enumerate}
1545
 
1546 21 dgisselq
\chapter{Registers}\label{chap:regs}
1547
 
1548 24 dgisselq
The ZipSystem registers fall into two categories, ZipSystem internal registers
1549
accessed via the ZipCPU shown in Tbl.~\ref{tbl:zpregs},
1550
\begin{table}[htbp]
1551
\begin{center}\begin{reglist}
1552 32 dgisselq
PIC   & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
1553
WDT   & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
1554 36 dgisselq
  & \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & {\em (Reserved for future use)} \\\hline
1555 32 dgisselq
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
1556
TMRA  & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
1557
TMRB  & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
1558
TMRC  & \scalebox{0.8}{\tt 0xc0000006} & 32 & R/W & Timer C\\\hline
1559
JIFF  & \scalebox{0.8}{\tt 0xc0000007} & 32 & R/W & Jiffies \\\hline
1560
MTASK  & \scalebox{0.8}{\tt 0xc0000008} & 32 & R/W & Master Task Clock Counter \\\hline
1561
MMSTL  & \scalebox{0.8}{\tt 0xc0000009} & 32 & R/W & Master Stall Counter \\\hline
1562
MPSTL  & \scalebox{0.8}{\tt 0xc000000a} & 32 & R/W & Master Pre--Fetch Stall Counter \\\hline
1563
MICNT  & \scalebox{0.8}{\tt 0xc000000b} & 32 & R/W & Master Instruction Counter\\\hline
1564
UTASK  & \scalebox{0.8}{\tt 0xc000000c} & 32 & R/W & User Task Clock Counter \\\hline
1565
UMSTL  & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
1566
UPSTL  & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
1567
UICNT  & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
1568 36 dgisselq
DMACTRL  & \scalebox{0.8}{\tt 0xc0000010} & 32 & R/W & DMA Control Register\\\hline
1569
DMALEN  & \scalebox{0.8}{\tt 0xc0000011} & 32 & R/W & DMA total transfer length\\\hline
1570
DMASRC  & \scalebox{0.8}{\tt 0xc0000012} & 32 & R/W & DMA source address\\\hline
1571
DMADST  & \scalebox{0.8}{\tt 0xc0000013} & 32 & R/W & DMA destination address\\\hline
1572 32 dgisselq
% Cache  & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
1573 24 dgisselq
\end{reglist}
1574
\caption{Zip System Internal/Peripheral Registers}\label{tbl:zpregs}
1575
\end{center}\end{table}
1576 33 dgisselq
and the two debug registers shown in Tbl.~\ref{tbl:dbgregs}.
1577 24 dgisselq
\begin{table}[htbp]
1578
\begin{center}\begin{reglist}
1579
ZIPCTRL & 0 & 32 & R/W & Debug Control Register \\\hline
1580
ZIPDATA & 1 & 32 & R/W & Debug Data Register \\\hline
1581
\end{reglist}
1582
\caption{Zip System Debug Registers}\label{tbl:dbgregs}
1583
\end{center}\end{table}
1584
 
1585 33 dgisselq
\section{Peripheral Registers}
1586
The peripheral registers, listed in Tbl.~\ref{tbl:zpregs}, are shown in the
1587
CPU's address space.  These may be accessed by the CPU at these addresses,
1588
and when so accessed will respond as described in Chapt.~\ref{chap:periph}.
1589
These registers will be discussed briefly again here.
1590 24 dgisselq
 
1591 33 dgisselq
The Zip CPU Interrupt controller has four different types of bits, as shown in
1592
Tbl.~\ref{tbl:picbits}.
1593
\begin{table}\begin{center}
1594
\begin{bitlist}
1595
31 & R/W & Master Interrupt Enable\\\hline
1596
30\ldots 16 & R/W & Interrupt Enables, write '1' to change\\\hline
1597
15 & R & Current Master Interrupt State\\\hline
1598
15\ldots 0 & R/W & Input Interrupt states, write '1' to clear\\\hline
1599
\end{bitlist}
1600
\caption{Interrupt Controller Register Bits}\label{tbl:picbits}
1601
\end{center}\end{table}
1602
The high order bit, or bit--31, is the master interrupt enable bit.  When this
1603
bit is set, then any time an interrupt occurs the CPU will be interrupted and
1604
will switch to supervisor mode, etc.
1605
 
1606
Bits 30~\ldots 16 are interrupt enable bits.  Should the interrupt line go
1607
ghile while enabled, an interrupt will be generated.  To set an interrupt enable
1608
bit, one needs to write the master interrupt enable while writing a 1' to this
1609
the bit.  To clear, one need only write a 0' to the master interrupt enable,
1610
while leaving this line high.
1611
 
1612
Bits 15\ldots 0 are the current state of the interrupt vector.  Interrupt lines
1613
trip when they go high, and remain tripped until they are acknowledged.  If
1614
the interrupt goes high for longer than one pulse, it may be high when a clear
1615
is requested.  If so, the interrupt will not clear.  The line must go low
1616
again before the status bit can be cleared.
1617
 
1618
As an example, consider the following scenario where the Zip CPU supports four
1619
interrupts, 3\ldots0.
1620
\begin{enumerate}
1621
\item The Supervisor will first, while in the interrupts disabled mode,
1622
        write a {\tt 32'h800f000f} to the controller.  The supervisor may then
1623
        switch to the user state with interrupts enabled.
1624
\item When an interrupt occurs, the supervisor will switch to the interrupt
1625
        state.  It will then cycle through the interrupt bits to learn which
1626
        interrupt handler to call.
1627
\item If the interrupt handler expects more interrupts, it will clear its
1628
        current interrupt when it is done handling the interrupt in question.
1629
        To do this, it will write a '1' to the low order interrupt mask,
1630
        such as writing a {\tt 32'h80000001}.
1631
\item If the interrupt handler does not expect any more interrupts, it will
1632
        instead clear the interrupt from the controller by writing a
1633
        {\tt 32'h00010001} to the controller.
1634
\item Once all interrupts have been handled, the supervisor will write a
1635
        {\tt 32'h80000000} to the interrupt register to re-enable interrupt
1636
        generation.
1637
\item The supervisor should also check the user trap bit, and possible soft
1638
        interrupt bits here, but this action has nothing to do with the
1639
        interrupt control register.
1640
\item The supervisor will then leave interrupt mode, possibly adjusting
1641
        whichever task is running, by executing a return from interrupt
1642
        command.
1643
\end{enumerate}
1644
 
1645
Leaving the interrupt controller, we show the timer registers bit definitions
1646
in Tbl.~\ref{tbl:tmrbits}.
1647
\begin{table}\begin{center}
1648
\begin{bitlist}
1649
31 & R/W & Auto-Reload\\\hline
1650
30\ldots 0 & R/W & Current timer value\\\hline
1651
\end{bitlist}
1652
\caption{Timer Register Bits}\label{tbl:tmrbits}
1653
\end{center}\end{table}
1654
As you may recall, the timer just counts down to zero and then trips an
1655
interrupt.  Writing to the current timer value sets that value, and reading
1656
from it returns that value.  Writing to the current timer value while also
1657
setting the auto--reload bit will send the timer into an auto--reload mode.
1658
In this mode, upon setting its interrupt bit for one cycle, the timer will
1659
also reset itself back to the value of the timer that was written to it when
1660
the auto--reload option was written to it.  To clear and stop the timer,
1661
just simply write a 32'h00' to this register.
1662
 
1663
The Jiffies register is somewhat similar in that the register always changes.
1664
In this case, the register counts up, whereas the timer always counted down.
1665
Reads from this register, as shown in Tbl.~\ref{tbl:jiffybits},
1666
\begin{table}\begin{center}
1667
\begin{bitlist}
1668
31\ldots 0 & R & Current jiffy value\\\hline
1669
31\ldots 0 & W & Value/time of next interrupt\\\hline
1670
\end{bitlist}
1671
\caption{Jiffies Register Bits}\label{tbl:jiffybits}
1672
\end{center}\end{table}
1673
always return the time value contained in the register.  Writes greater than
1674
the current Jiffy value, that is where the new value minus the old value is
1675
greater than zero while ignoring truncation, will set a new Jiffy interrupt
1676
time.  At that time, the Jiffy vector will clear, and another interrupt time
1677
may either be written to it, or it will just continue counting without
1678
activating any more interrupts.
1679
 
1680
The Zip CPU also supports several counter peripherals, mostly in the way of
1681
process accounting.  This peripherals have a single register associated with
1682
them, shown in Tbl.~\ref{tbl:ctrbits}.
1683
\begin{table}\begin{center}
1684
\begin{bitlist}
1685
31\ldots 0 & R/W & Current counter value\\\hline
1686
\end{bitlist}
1687
\caption{Counter Register Bits}\label{tbl:ctrbits}
1688
\end{center}\end{table}
1689
Writes to this register set the new counter value.  Reads read the current
1690
counter value.
1691
 
1692
The current design operation of these counters is that of performance counting.
1693
Two sets of four registers are available for keeping track of performance.
1694
The first is a task counter.  This just counts clock ticks.  The second
1695
counter is a prefetch stall counter, then an master stall counter.  These
1696
allow the CPU to be evaluated as to how efficient it is.  The fourth and
1697
final counter is an instruction counter, which counts how many instructions the
1698
CPU has issued.
1699
 
1700
It is envisioned that these counters will be used as follows: First, every time
1701
a master counter rolls over, the supervisor (Operating System) will record
1702
the fact.  Second, whenever activating a user task, the Operating System will
1703
set the four user counters to zero.  When the user task has completed, the
1704
Operating System will read the timers back off, to determine how much of the
1705
CPU the process had consumed.
1706
 
1707 36 dgisselq
The final peripheral to discuss is the DMA controller.  This controller
1708
has four registers.  Of these four, the length, source and destination address
1709
registers should need no further explanation.  They are full 32--bit registers
1710
specifying the entire transfer length, the starting address to read from, and
1711
the starting address to write to.  The registers can be written to when the
1712
DMA is idle, and read at any time.  The control register, however, will need
1713
some more explanation.
1714
 
1715
The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.
1716
\begin{table}\begin{center}
1717
\begin{bitlist}
1718
31 & R & DMA Active\\\hline
1719
30 & R & Wishbone error, transaction aborted (cleared on any write)\\\hline
1720
29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline
1721
28 & R/W & Set to '0' to prevent the controller from incrementing the
1722
        destination address, '0' for normal memory copy. \\\hline
1723
27 \ldots 16 & W & The DMA Key.  Write a 12'hfed to these bits to start the
1724
        activate any DMA transfer.  \\\hline
1725
27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline
1726
26 \ldots 16 & R & Indicates the number of items in the transfer buffer that
1727
        have yet to be written. \\\hline
1728
15 & R/W & Set to '1' to trigger on an interrupt, or '0' to start immediately
1729
        upon receiving a valid key.\\\hline
1730
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
1731
9\ldots 0 & R/W & Intermediate transfer length minus one.  Thus, to transfer
1732
        one item at a time set this value to 0. To transfer 1024 at a time,
1733
        set it to 1024.\\\hline
1734
\end{bitlist}
1735
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
1736
\end{center}\end{table}
1737
This control register has been designed so that the common case of memory
1738
access need only set the key and the transfer length.  Hence, writing a
1739
\hbox{32'h0fed03ff} to the control register will start any memory transfer.
1740
On the other hand, if you wished to read from a serial port (constant address)
1741
and put the result into a buffer every time a word was available, you
1742
might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
1743
have a serial port wired to the zero bit of this interrupt control.  (The
1744
DMA controller does not use the interrupt controller, and cannot clear
1745
interrupts.)  As a third example, if you wished to write to an external
1746
FIFO anytime it was less than half full (had fewer than 512 items), and
1747
interrupt line 2 indicated this condition, you might wish to issue a
1748
\hbox{32'h1fed8dff} to this port.
1749
 
1750 33 dgisselq
\section{Debug Port Registers}
1751
Accessing the Zip System via the debug port isn't as straight forward as
1752
accessing the system via the wishbone bus.  The debug port itself has been
1753
reduced to two addresses, as outlined earlier in Tbl.~\ref{tbl:dbgregs}.
1754
Access to the Zip System begins with the Debug Control register, shown in
1755
Tbl.~\ref{tbl:dbgctrl}.
1756
\begin{table}\begin{center}
1757
\begin{bitlist}
1758
31\ldots 14 & R & Reserved\\\hline
1759
13 & R & CPU GIE setting\\\hline
1760
12 & R & CPU is sleeping\\\hline
1761
11 & W & Command clear PF cache\\\hline
1762
10 & R/W & Command HALT, Set to '1' to halt the CPU\\\hline
1763
9 & R & Stall Status, '1' if CPU is busy\\\hline
1764 36 dgisselq
8 & R/W & Step Command, set to '1' to step the CPU, also sets the halt bit\\\hline
1765 33 dgisselq
7 & R & Interrupt Request \\\hline
1766
6 & R/W & Command RESET \\\hline
1767
5\ldots 0 & R/W & Debug Register Address \\\hline
1768
\end{bitlist}
1769
\caption{Debug Control Register Bits}\label{tbl:dbgctrl}
1770
\end{center}\end{table}
1771
 
1772
The first step in debugging access is to determine whether or not the CPU
1773
is halted, and to halt it if not.  To do this, first write a '1' to the
1774
Command HALT bit.  This will halt the CPU and place it into debug mode.
1775
Once the CPU is halted, the stall status bit will drop to zero.  Thus,
1776
if bit 10 is high and bit 9 low, the debug port is open to examine the
1777
internal state of the CPU.
1778
 
1779
At this point, the external debugger may examine internal state information
1780
from within the CPU.  To do this, first write again to the command register
1781
a value (with command halt still high) containing the address of an internal
1782
register of interest in the bottom 6~bits.  Internal registers that may be
1783
accessed this way are listed in Tbl.~\ref{tbl:dbgaddrs}.
1784
\begin{table}\begin{center}
1785
\begin{reglist}
1786
sR0 & 0 & 32 & R/W & Supervisor Register R0 \\\hline
1787
sR1 & 0 & 32 & R/W & Supervisor Register R1 \\\hline
1788
sSP & 13 & 32 & R/W & Supervisor Stack Pointer\\\hline
1789
sCC & 14 & 32 & R/W & Supervisor Condition Code Register \\\hline
1790
sPC & 15 & 32 & R/W & Supervisor Program Counter\\\hline
1791
uR0 & 16 & 32 & R/W & User Register R0 \\\hline
1792
uR1 & 17 & 32 & R/W & User Register R1 \\\hline
1793
uSP & 29 & 32 & R/W & User Stack Pointer\\\hline
1794
uCC & 30 & 32 & R/W & User Condition Code Register \\\hline
1795
uPC & 31 & 32 & R/W & User Program Counter\\\hline
1796
PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline
1797
WDT & 33 & 32 & R/W & Watchdog Timer\\\hline
1798
CCHE & 34 & 32 & R/W & Manual Cache Controller\\\hline
1799
CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline
1800
TMRA & 36 & 32 & R/W & Timer A\\\hline
1801
TMRB & 37 & 32 & R/W & Timer B\\\hline
1802
TMRC & 38 & 32 & R/W & Timer C\\\hline
1803
JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline
1804
MTASK & 40 & 32 & R/W & Master task clock counter\\\hline
1805
MMSTL & 41 & 32 & R/W & Master memory stall counter\\\hline
1806
MPSTL & 42 & 32 & R/W & Master Pre-Fetch Stall counter\\\hline
1807
MICNT & 43 & 32 & R/W & Master instruction counter\\\hline
1808
UTASK & 44 & 32 & R/W & User task clock counter\\\hline
1809
UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline
1810
UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline
1811
UICNT & 47 & 32 & R/W & User instruction counter\\\hline
1812
\end{reglist}
1813
\caption{Debug Register Addresses}\label{tbl:dbgaddrs}
1814
\end{center}\end{table}
1815
Primarily, these registers'' include access to the entire CPU register
1816 36 dgisselq
set, as well as the internal peripherals.  To read one of these registers
1817 33 dgisselq
once the address is set, simply issue a read from the data port.  To write
1818
one of these registers or peripheral ports, simply write to the data port
1819
after setting the proper address.
1820
 
1821
In this manner, all of the CPU's internal state may be read and adjusted.
1822
 
1823
As an example of how to use this, consider what would happen in the case
1824
of an external break point.  If and when the CPU hits a break point that
1825
causes it to halt, the Command HALT bit will activate on its own, the CPU
1826
will then raise an external interrupt line and wait for a debugger to examine
1827
its state.  After examining the state, the debugger will need to remove
1828
the breakpoint by writing a different instruction into memory and by writing
1829
to the command register while holding the clear cache, command halt, and
1830
step CPU bits high, (32'hd00).  The debugger may then replace the breakpoint
1831
now that the CPU has gone beyond it, and clear the cache again (32'h500).
1832
 
1833
To leave this debug mode, simply write a 32'h0' value to the command register.
1834
 
1835
\chapter{Wishbone Datasheets}\label{chap:wishbone}
1836 32 dgisselq
The Zip System supports two wishbone ports, a slave debug port and a master
1837 21 dgisselq
port for the system itself.  These are shown in Tbl.~\ref{tbl:wishbone-slave}
1838
\begin{table}[htbp]
1839
\begin{center}
1840
\begin{wishboneds}
1841
Revision level of wishbone & WB B4 spec \\\hline
1842
Type of interface & Slave, Read/Write, single words only \\\hline
1843 24 dgisselq
Address Width & 1--bit \\\hline
1844 21 dgisselq
Port size & 32--bit \\\hline
1845
Port granularity & 32--bit \\\hline
1846
Maximum Operand Size & 32--bit \\\hline
1847
Data transfer ordering & (Irrelevant) \\\hline
1848
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1849
Signal Names & \begin{tabular}{ll}
1850
                Signal Name & Wishbone Equivalent \\\hline
1851
                {\tt i\_clk} & {\tt CLK\_I} \\
1852
                {\tt i\_dbg\_cyc} & {\tt CYC\_I} \\
1853
                {\tt i\_dbg\_stb} & {\tt STB\_I} \\
1854
                {\tt i\_dbg\_we} & {\tt WE\_I} \\
1855
                {\tt i\_dbg\_addr} & {\tt ADR\_I} \\
1856
                {\tt i\_dbg\_data} & {\tt DAT\_I} \\
1857
                {\tt o\_dbg\_ack} & {\tt ACK\_O} \\
1858
                {\tt o\_dbg\_stall} & {\tt STALL\_O} \\
1859
                {\tt o\_dbg\_data} & {\tt DAT\_O}
1860
                \end{tabular}\\\hline
1861
\end{wishboneds}
1862 22 dgisselq
\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
1863 21 dgisselq
\end{center}\end{table}
1864
and Tbl.~\ref{tbl:wishbone-master} respectively.
1865
\begin{table}[htbp]
1866
\begin{center}
1867
\begin{wishboneds}
1868
Revision level of wishbone & WB B4 spec \\\hline
1869 24 dgisselq
Type of interface & Master, Read/Write, single cycle or pipelined\\\hline
1870
Address Width & 32--bit bits \\\hline
1871 21 dgisselq
Port size & 32--bit \\\hline
1872
Port granularity & 32--bit \\\hline
1873
Maximum Operand Size & 32--bit \\\hline
1874
Data transfer ordering & (Irrelevant) \\\hline
1875
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1876
Signal Names & \begin{tabular}{ll}
1877
                Signal Name & Wishbone Equivalent \\\hline
1878
                {\tt i\_clk} & {\tt CLK\_O} \\
1879
                {\tt o\_wb\_cyc} & {\tt CYC\_O} \\
1880
                {\tt o\_wb\_stb} & {\tt STB\_O} \\
1881
                {\tt o\_wb\_we} & {\tt WE\_O} \\
1882
                {\tt o\_wb\_addr} & {\tt ADR\_O} \\
1883
                {\tt o\_wb\_data} & {\tt DAT\_O} \\
1884
                {\tt i\_wb\_ack} & {\tt ACK\_I} \\
1885
                {\tt i\_wb\_stall} & {\tt STALL\_I} \\
1886
                {\tt i\_wb\_data} & {\tt DAT\_I}
1887
                \end{tabular}\\\hline
1888
\end{wishboneds}
1889 22 dgisselq
\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
1890 21 dgisselq
\end{center}\end{table}
1891
I do not recommend that you connect these together through the interconnect.
1892 24 dgisselq
Rather, the debug port of the CPU should be accessible regardless of the state
1893
of the master bus.
1894 21 dgisselq
 
1895 24 dgisselq
You may wish to notice that neither the {\tt ERR} nor the {\tt RETRY} wires
1896
have been implemented.  What this means is that the CPU is currently unable
1897
to detect a bus error condition, and so may stall indefinitely (hang) should
1898
it choose to access a value not on the bus, or a peripheral that is not
1899
yet properly configured.
1900 21 dgisselq
 
1901
\chapter{Clocks}\label{chap:clocks}
1902
 
1903 32 dgisselq
This core is based upon the Basys--3 development board sold by Digilent.
1904
The Basys--3 development board contains one external 100~MHz clock, which is
1905 36 dgisselq
sufficient to run the Zip CPU core.
1906 21 dgisselq
\begin{table}[htbp]
1907
\begin{center}
1908
\begin{clocklist}
1909
i\_clk & External & 100~MHz & 100~MHz & System clock.\\\hline
1910
\end{clocklist}
1911
\caption{List of Clocks}\label{tbl:clocks}
1912
\end{center}\end{table}
1913
I hesitate to suggest that the core can run faster than 100~MHz, since I have
1914
had struggled with various timing violations to keep it at 100~MHz.  So, for
1915
now, I will only state that it can run at 100~MHz.
1916
 
1917
 
1918
\chapter{I/O Ports}\label{chap:ioports}
1919 33 dgisselq
The I/O ports to the Zip CPU may be grouped into three categories.  The first
1920
is that of the master wishbone used by the CPU, then the slave wishbone used
1921
to command the CPU via a debugger, and then the rest.  The first two of these
1922
were already discussed in the wishbone chapter.  They are listed here
1923
for completeness in Tbl.~\ref{tbl:iowb-master}
1924
\begin{table}
1925
\begin{center}\begin{portlist}
1926
{\tt o\_wb\_cyc}   &  1 & Output & Indicates an active Wishbone cycle\\\hline
1927
{\tt o\_wb\_stb}   &  1 & Output & WB Strobe signal\\\hline
1928
{\tt o\_wb\_we}    &  1 & Output & Write enable\\\hline
1929
{\tt o\_wb\_addr}  & 32 & Output & Bus address \\\hline
1930
{\tt o\_wb\_data}  & 32 & Output & Data on WB write\\\hline
1931
{\tt i\_wb\_ack}   &  1 & Input  & Slave has completed a R/W cycle\\\hline
1932
{\tt i\_wb\_stall} &  1 & Input  & WB bus slave not ready\\\hline
1933
{\tt i\_wb\_data}  & 32 & Input  & Incoming bus data\\\hline
1934
\end{portlist}\caption{CPU Master Wishbone I/O Ports}\label{tbl:iowb-master}\end{center}\end{table}
1935
and~\ref{tbl:iowb-slave} respectively.
1936
\begin{table}
1937
\begin{center}\begin{portlist}
1938
{\tt i\_wb\_cyc}   &  1 & Input & Indicates an active Wishbone cycle\\\hline
1939
{\tt i\_wb\_stb}   &  1 & Input & WB Strobe signal\\\hline
1940
{\tt i\_wb\_we}    &  1 & Input & Write enable\\\hline
1941
{\tt i\_wb\_addr}  &  1 & Input & Bus address, command or data port \\\hline
1942
{\tt i\_wb\_data}  & 32 & Input & Data on WB write\\\hline
1943
{\tt o\_wb\_ack}   &  1 & Output  & Slave has completed a R/W cycle\\\hline
1944
{\tt o\_wb\_stall} &  1 & Output  & WB bus slave not ready\\\hline
1945
{\tt o\_wb\_data}  & 32 & Output  & Incoming bus data\\\hline
1946
\end{portlist}\caption{CPU Debug Wishbone I/O Ports}\label{tbl:iowb-slave}\end{center}\end{table}
1947 21 dgisselq
 
1948 33 dgisselq
There are only four other lines to the CPU: the external clock, external
1949
reset, incoming external interrupt line(s), and the outgoing debug interrupt
1950
line.  These are shown in Tbl.~\ref{tbl:ioports}.
1951
\begin{table}
1952
\begin{center}\begin{portlist}
1953
{\tt i\_clk} & 1 & Input & The master CPU clock \\\hline
1954
{\tt i\_rst} & 1 & Input &  Active high reset line \\\hline
1955
{\tt i\_ext\_int} & 1\ldots 6 & Input &  Incoming external interrupts \\\hline
1956
{\tt o\_ext\_int} & 1 & Output & CPU Halted interrupt \\\hline
1957
\end{portlist}\caption{I/O Ports}\label{tbl:ioports}\end{center}\end{table}
1958
The clock line was discussed briefly in Chapt.~\ref{chap:clocks}.  We
1959
typically run it at 100~MHz.  The reset line is an active high reset.  When
1960
asserted, the CPU will start running again from its reset address in
1961
memory.  Further, depending upon how the CPU is configured and specifically on
1962
the {\tt START\_HALTED} parameter, it may or may not start running
1963
automatically.  The {\tt i\_ext\_int} line is for an external interrupt.  This
1964
line may be as wide as 6~external interrupts, depending upon the setting of
1965
the {\tt EXTERNAL\_INTERRUPTS} line.  As currently configured, the ZipSystem
1966
only supports one such interrupt line by default.  For us, this line is the
1967
output of another interrupt controller, but that's a board specific setup
1968
detail.  Finally, the Zip System produces one external interrupt whenever
1969
the CPU halts to wait for the debugger.
1970
 
1971 36 dgisselq
\chapter{Initial Assessment}\label{chap:assessment}
1972
 
1973
Having now worked with the Zip CPU for a while, it is worth offering an
1974
honest assessment of how well it works and how well it was designed. At the
1975
end of this assessment, I will propose some changes that may take place in a
1976
later version of this Zip CPU to make it better.
1977
 
1978
\section{The Good}
1979
\begin{itemize}
1980
\item The Zip CPU is light weight and fully featured as it exists today. For
1981
        anyone who wishes to build a general purpose CPU and then to
1982
        experiment with building and adding particular features, the Zip CPU
1983
        makes a good starting point--it is fairly simple. Modifications should
1984
        be simple enough.
1985
\item As an estimate of the weight'' of this implementation, the CPU has
1986
        cost me less than 150 hours to implement from its inception.
1987
\item The Zip CPU was designed to be an implementable soft core that could be
1988
        placed within an FPGA, controlling actions internal to the FPGA. It
1989
        fits this role rather nicely. It does not fit the role of a system on
1990
        a chip very well, but then it was never intended to be a system on a
1991
        chip but rather a system within a chip.
1992
\item The extremely simplified instruction set of the Zip CPU was a good
1993
        choice. Although it does not have many of the commonly used
1994
        instructions, PUSH, POP, JSR, and RET among them, the simplified
1995
        instruction set has demonstrated an amazing versatility. I will contend
1996
        therefore and for anyone who will listen, that this instruction set
1997
        offers a full and complete capability for whatever a user might wish
1998
        to do with two exceptions: bytewise character access and accelerated
1999
        floating-point support.
2000
\item This simplified instruction set is easy to decode.
2001
\item The simplified bus transactions (32-bit words only) were also very easy
2002
        to implement.
2003
\item The novel approach of having a single interrupt vector, which just
2004
        brings the CPU back to the instruction it left off at within the last
2005
        interrupt context doesn't appear to have been that much of a problem.
2006
        If most modern systems handle interrupt vectoring in software anyway,
2007
        why maintain hardware support for it?
2008
\item My goal of a high rate of instructions per clock may not be the proper
2009
        measure. For example, if instructions are being read from a SPI flash
2010
        device, such as is common among FPGA implementations, these same
2011
        instructions may suffer stalls of between 64 and 128 cycles per
2012
        instruction just to read the instruction from the flash. Executing the
2013
        instruction in a single clock cycle is no longer the appropriate
2014
        measure. At the same time, it should be possible to use the DMA
2015
        peripheral to copy instructions from the FLASH to a temporary memory
2016
        location, after which they may be executed at a single instruction
2017
        cycle per access again.
2018
\end{itemize}
2019
 
2020
\section{The Not so Good}
2021
\begin{itemize}
2022
\item While one of the stated goals was to use a small amount of logic,
2023
        3k~LUTs isn't that impressively small. Indeed, it's really much
2024
        too expensive when compared against other 8 and 16-bit CPUs that have
2025
        less than 1k LUTs.
2026
 
2027
        Still, \ldots it's not bad, it's just not astonishingly good.
2028
 
2029
\item The fact that the instruction width equals the bus width means that the
2030
        instruction fetch cycle will always be interfering with any load or
2031
        store memory operation, with the only exception being if the
2032
        instruction is already in the cache.  {\em This has become the
2033
        fundamental limit on the speed and performance of the CPU!}
2034
        Those familiar with the Von--Neumann approach of sharing a bus
2035
        between data and instructions will not be surprised by this assessment.
2036
 
2037
        This could be fixed in one of three ways: the instruction set
2038
        architecture could be modified to handle Very Long Instruction Words
2039
        (VLIW) so that each 32--bit word would encode two or more instructions,
2040
        the instruction fetch bus width could be increased from 32--bits to
2041
        64--bits or more, or the instruction bus could be separated from the
2042
        data bus.  Any and all of these approaches would increase the overall
2043
        LUT count.
2044
 
2045
\item The (non-existant) floating point unit was an after-thought, isn't even
2046
        built as a potential option, and most likely won't support the full
2047
        IEEE standard set of FPU instructions--even for single point precision.
2048
        This (non-existant) capability would benefit the most from an
2049
        out-of-order execution capability, which the Zip CPU does not have.
2050
 
2051
        Still, sharing FPU registers with the main register set was a good
2052
        idea and worth preserving, as it simplifies context swapping.
2053
 
2054
        Perhaps this really isn't a problem, but rather a feature.  By not
2055
        implementing FPU instructions, the Zip CPU maintains a lower LUT count
2056
        than it would have if it did implement these instructions.
2057
 
2058
\item The CPU has no character support. This is both good and bad.
2059
        Realistically, the CPU works just fine without it. Characters can be
2060
        supported as subsets of 32-bit words without any problem. Practically,
2061
        though, it will make compiling non-Zip CPU code difficult--especially
2062
        anything that assumes sizeof(int)=4*sizeof(char), or that tries to
2063
        create unions with characters and integers and then attempts to
2064
        reference the address of the characters within that union.
2065
 
2066
\item The Zip CPU does not support a data cache. One can still be built
2067
        externally, but this is a limitation of the CPU proper as built.
2068
        Further, under the theory of the Zip CPU design (that of an embedded
2069
        soft-core processor within an FPGA, where any address'' may reference
2070
        either memory or a peripheral that may have side-effects), any data
2071
        cache would need to be based upon an initial knowledge of whether or
2072
        not it is supporting memory (cachable) or peripherals. This knowledge
2073
        must exist somewhere, and that somewhere is currently (and by design)
2074
        external to the CPU.
2075
 
2076
        This may also be written off as a feature'' of the Zip CPU, since
2077
        the addition of a data cache can greatly increase the LUT count of
2078
        a soft core.
2079
 
2080
\item Many other instruction sets offer three operand instructions, whereas
2081
        the Zip CPU only offers two operand instructions. This means that it
2082
        takes the Zip CPU more instructions to do many of the same operations.
2083
        The good part of this is that it gives the Zip CPU a greater amount of
2084
        flexibility in its immediate operand mode, although that increased
2085
        flexibility isn't necessarily as valuable as one might like.
2086
 
2087
\item The Zip CPU does not currently detect and trap on either illegal
2088
        instructions or bus errors.  Attempts to access non--existent
2089
        memory quietly return erroneous results, rather than halting the
2090
        process (user mode) or halting or resetting the CPU (supervisor mode).
2091
 
2092
\item The Zip CPU doesn't support out of order execution. I suppose it could
2093
        be modified to do so, but then it would no longer be the simple''
2094
        and low LUT count CPU it was designed to be. The two primary results
2095
        are that 1) loads may unnecessarily stall the CPU, even if other
2096
        things could be done while waiting for the load to complete, 2)
2097
        bus errors on stores will never be caught at the point of the error,
2098
        and 3) branch prediction becomes more difficult.
2099
 
2100
\item Although switching to an interrupt context in the Zip CPU design doesn't
2101
        require a tremendous swapping of registers, in reality it still
2102
        does--since any task swap still requires saving and restoring all
2103
        16~user registers. That's a lot of memory movement just to service
2104
        an interrupt.
2105
 
2106
\item The Zip CPU is by no means generic: it will never handle addresses
2107
        larger than 32-bits (16GB) without a complete and total redesign.
2108
        This may limit its utility as a generic CPU in the future, although
2109
        as an embedded CPU within an FPGA this isn't really much of a limit
2110
        or restriction.
2111
 
2112
\item While the Zip CPU has its own assembler, it has no linker and does not
2113
        (yet) support a compiler. The standard C library is an even longer
2114
        shot. My dream of having binutils and gcc support has not been
2115
        realized and at this rate may not be realized. (I've been intimidated
2116
        by the challenge everytime I've looked through those codes.)
2117
 
2118
\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle
2119
        execution, the Zip CPU is unable to exploit this parallelism. Instead,
2120
        apart from the DMA and the pipelined prefetch, all loads and stores
2121
        are single wishbone bus operations requiring a minimum of 3 clocks.
2122
        (In practice, this has turned into 7-clocks.)
2123
 
2124
\iffalse
2125
\item There is no control over whether or not an instruction sets the
2126
        condition codes--certain instructions always set the condition codes,
2127
        other instructions never set them. This effectively limits conditional
2128
        instructions to a single instruction only (with two or more
2129
        instructions as an exception), as the first instruction that sets
2130
        condition codes will break the condition code chain.
2131
 
2132
        {\em (A proposed change below address this.)}
2133
 
2134
\item Using the CC register as a trap address was a bad idea--it limits the CC
2135
        registers ability to be used in future expansion, such as by adding
2136
        exception indication flags: bus error, floating point exception, etc.
2137
 
2138
        {\em (This can be changed by a different O/S implementation of the trap
2139
        instruction.)}
2140
\item The current implementation suffers from too many stalls on any
2141
        branch--even if the branch is known early on.
2142
 
2143
        {\em (This is addressed in proposals below.)}
2144
        % Addressed, 20150918
2145
 
2146
\item In a similar fashion, a switch to interrupt context forces the pipeline
2147
        to be cleared, whereas it might make more sense to just continue
2148
        executing the instructions already in the pipeline while the prefetch
2149
        stage is working on switching to the interrupt context.
2150
 
2151
        {\em (Also addressed in proposals below.)}
2152
        % This should happen so rarely that it is not really a problem
2153
\fi
2154
 
2155
\end{itemize}
2156
 
2157
\section{The Next Generation}
2158
This section could also be labeled as my To do'' list.
2159
 
2160
Given the feedback listed above, perhaps its time to consider what changes could be made to improve the Zip CPU in the future. I offer the following as proposals:
2161
 
2162
\begin{itemize}
2163
\item {\bf Remove the low LUT goal.} It wasn't really achieved, and the
2164
        proposals below will only increase the amount of logic the Zip CPU
2165
        requires.  While I expect that the Zip CPU will always be somewhat
2166
        of a light weight, it will never be the smallest kid on the block.
2167
 
2168
        I'm actually struggling with this idea.  The whole goal of the Zip
2169
        CPU was to be light weight.  Wouldn't it make more sense to create and
2170
        maintain options whereby it would remain lightweight?  For example, if
2171
        the process accounting registers are anything but light weight, why
2172
        keep them?  Why not instead make some compile flags that just turn them
2173
        off, keeping the CPU lightweight?  The same holds for the prefetch
2174
        cache.
2175
 
2176
\iffalse
2177
\item {\bf Adjust the Zip CPU so that conditional instructions do not set
2178
        flags}, although they may explicitly set condition codes if writing
2179
        to the CC register.
2180
 
2181
        This is a simple change to the core, and may show up in new releases.
2182
        % Fixed, 20150918
2183
\fi
2184
 
2185
\item The {\tt .V}' condition was never used in any code other than my test
2186
        code.  Suggest changing it to a {\tt .LE}' condition, which seems
2187
        to be more useful.
2188
 
2189
\iffalse
2190
\item Add in an {\bf unpredictable branch delay slot}, so that on any branch
2191
        the delay slot may or may not be executed before the branch.
2192
        Instructions that do not depend upon the branch, and that should be
2193
        executed were the branch not taken, could be placed into the delay
2194
        slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,
2195
        whereas it wouldn't affect the timing of the branch if taken. It would
2196
        just do something irrelevant.
2197
 
2198
        % Changes made, 20150918, make this option no longer relevant
2199
 
2200
\item {\bf Re-engineer Branch Processing.}  There's no reason why a {\tt BRA}
2201
        instruction should create five stall cycles.  The decode stage, plus
2202
        the prefetch engine, should be able to drop this number of stalls via
2203
        better branch handling.
2204
 
2205
        Indeed, this could turn into a simple means of branch prediction:
2206
        if {\tt BRA} suffered a single stall only, whereas {\tt BRA.C}
2207
        suffered five stalls, then {\tt BRA.!C} followed by {\tt BRA} would
2208
        be faster than a {\tt BRA.C} instruction.  This would then allow a
2209
        compiler to do explicit branch optimizations.
2210
 
2211
        Of course, longer branches using {\tt ADD X,PC} would still not be
2212
        optimized.
2213
 
2214
        % DONE: 20150918 -- to include the ADD X,PC instructions
2215
 
2216
\item {\bf Request bus access for Load/Store two cycles earlier.}  The problem
2217
        here is the contention for the bus between the memory unit and the
2218
        prefetch unit.  Currently, the memory unit must ask the prefetch
2219
        unit to release the bus if it is in the middle of a bus cycle.  At this
2220
        point, the prefetch drops the {\tt STB} line on the next clock and must
2221
        then wait for the last {\tt ACK} before releasing the bus.  If the
2222
        request takes one clock, dropping the strobe line the next, waiting
2223
        for an acknowledgement takes another, and then the bus must be idle
2224
        for one cycle before starting again, these extra cycles add up.
2225
        It should be possible to tell the prefetch stage to give up the bus
2226
        as soon as the decoder knows the instruction will need the bus.
2227
        Indeed, if done in the decode stage, this might drop the seven cycle
2228
        access down by two cycles.
2229
 
2230
        % FIXED: 20150918
2231
\fi
2232
 
2233
\item {\bf Consider a more traditional Instruction Cache.}  The current
2234
        pipelined instruction cache just reads a window of memory into
2235
        its cache.  If the CPU leaves that window, the entire cache is
2236
        invalidated.  A more traditional cache, however, might allow
2237
        common subroutines to stay within the cache without invalidating the
2238
        entire cache structure.
2239
 
2240
\iffalse
2241
\item {\bf Very Long Instruction Word (VLIW).}  Now, to speed up operation, I
2242
        propose that the Zip CPU instruction set be modified towards a Very
2243
        Long Instruction Word (VLIW) implementation. In this implementation,
2244
        an instruction word may contain either one or two separate
2245
        instructions. The first instruction would take up the high order bits,
2246
        the second optional instruction the lower 16-bits. Further, I propose
2247
        that any of the ALU instructions (SUB through LSR) automatically have
2248
        a second instruction whenever their operand B' is a register, and use
2249
        the full 20-bit immediate if not. This will effectively eliminate the
2250
        register plus immediate mode for all of these instructions.
2251
 
2252
        This is the minimal required change to increase the number of
2253
        instructions per clock cycle. Other changes would need to take place
2254
        as well to support this. These include:
2255
        \begin{itemize}
2256
        \item Instruction words containing two instructions would take two
2257
                clocks to complete, while requiring only a single cycle
2258
                instruction fetch.
2259
        \item Instructions preceded by a label in the asseembler must always
2260
                start in the high order word.
2261
        \item VLIW's, once started, must always execute to completion. The
2262
                upper word may set the PC, the lower word may not. Regardless
2263
                of whether the upper word sets the PC, the lower word must
2264
                still be guaranteed to complete before the PC changes. On any
2265
                switch to (or from) interrupt context, both instructions must
2266
                complete or none of the instructions in the word shall
2267
                complete prior to the switch.
2268
        \item STEP commands and BREAK instructions will only take place after
2269
                the entire word is executed.
2270
        \end{itemize}
2271
 
2272
        If done well, the assembler should be able to handle these changes
2273
        with the biggest impacts to the user being increased performance and
2274
        a loss of the register plus immediate ALU modes. (These weren't really
2275
        relevant for the XOR, OR, AND, etc. operations anyway.) Machine code
2276
        compatibility will not be maintained.
2277
 
2278
        A proposed secondary instruction set might consist of: a four bit
2279
        operand (any of the prior instructions would be supported, with some
2280
        exceptions such as moves to and from user registers while in
2281
        supervisor mode not being supported), a 4-bit register result (PC not
2282
        allowed), a 3-bit conditional (identical to the conditional for the
2283
        upper word), a single bit for whether or not an immediate is present
2284
        or not, followed by either a 4-bit register or a 4-bit signed
2285
        immediate. The multiply instruction would steal the immediate flag to
2286
        be used as a sign indication, forcing both operands to be registers
2287
        without any immediate offsets.
2288
 
2289
        {\em Initial conversion of several library functions to this secondary
2290
        instruction set has demonstrated little to no gain.   The problem was
2291
        that the new instruction set was made by joining a rarely used
2292
        instruction (ALU with register and not immediate) with a more common
2293
        instruction.  The utility was then limited by the utility of the rare
2294
        instrction, which limited the impact of the entire approach.  }
2295
\else
2296
\item {\bf Very Long Instruction Word (VLIW).}  The goal here would be to
2297
        create a new instruction set whereby two instructions would be encoded
2298
        in each 32--bit word.  While this may speed up
2299
        CPU operation, it would necessitate an instruction redesign.
2300
\fi
2301
 
2302
\end{itemize}
2303
 
2304
 
2305 21 dgisselq
% Appendices
2306
% Index
2307
\end{document}
2308
 
2309